a
AC Vector Processor
FEATURES
Complete Vector Coordinate Transformation on Silicon
Mixed Signal Data Acquisition
Three-Phase 1208 and Orthogonal 908 Signal
Transformation
Three-Phase Balance Diagnostic–Homopolar Output
FUNCTIONAL BLOCK DIAGRAM
Cosθ Sinθ
Cosθ
APPLICATIONS
AC Induction and DC Permanent
Magnet Motor Control
HVAC, Pump, Fan Control
Material Handling
Robotics
Spindle Drives
Gyroscopes
Dryers
Washing Machines
Electric Cars
Actuator
Three-Phase Power Measurement
Digital-to-Resolver & Synchro Conversion
GENERAL DESCRIPTION
The AD2S100 performs the vector rotation of three-phase 120
degree or two-phase 90 degree sine and cosine signals by transferring these inputs into a new reference frame which is controlled
by the digital input angle φ. Two transforms are included in the
AD2S100. The first is the Clarke transform which computes
the sine and cosine orthogonal components of a three-phase
input. These signals represent real and imaginary components
which then form the input to the Park transform. The Park
transform relates the angle of the input signals to a reference
frame controlled by the digital input port. The digital input
port is a 12-bit parallel binary representation.
If the input signals are represented by Vds and Vqs, respectively,
where Vds and Vqs are the real and imaginary components, then
the transformation can be described as follows:
Vds' = Vds Cosφ – Vqs Sinφ
Vqs' = Vds Sinφ + Vqs Cosφ
Cos (θ + 120°)
Cos (θ + 240°)
Sinθ
CONV1
Ia
Vds
INPUT
DATA
STROBE
φ POSITION
PARALLEL
DATA
12 BITS
SINE AND
SECTOR
COSINE
MULTIPLIER MULTIPLIER
BUSY
Va
Vds'
Ib
2φ -3φ
30-20
Ic
Vqs
Vb
Cos θ + φ
Cos (θ + 120° + φ)
Vc Cos (θ + 240° + φ)
SINE AND
SECTOR
COSINE
MULTIPLIER MULTIPLIER
Vqs'
Sin θ + φ
Ia + Ib + Ic
3
DECODE
CONV2
HOMOPOLAR
OUTPUT
HOMOPOLAR
REFERENCE
+5V GND –5V
The digital input section will accept a resolution of up to 12 bits
(AD2S100). An input data strobe signal is required to synchronize the position data and load this information into the device
counters. A busy output is provided to identify the conversion
status of the AD2S100. The busy period represents the conversion time of the vector rotation.
Two analog output formats are available. A two-phase rotated
output facilitates multiple rotation blocks. Three phase format
signals are available for use with a PWM inverter.
PRODUCT HIGHLIGHTS
Hardware Peripheral for Standard Microcontrollers and
DSP Systems
The AD2S100 removes the time consuming cartesian transformations from digital processors and benchmarks a speed improvement of 30:1 on standard 20 MHz processors. AD2S100
transformation time = 2 µs (typ).
Field Oriented Control of AC and DC Brushless Motors
The AD2S100 accommodates all the necessary functions to
provide a hardware solution for ac vector control of induction
motors and dc brushless motors.
Where Vds' and Vqs' are the output of the Park transform
and Sinφ, and Cosφ are the values internally derived by the
AD2S100 from the binary digital data.
Three-Phase Imbalance Detection
The input section of the device can be configured to accept
either three-phase inputs, two-phase inputs of a three-phase
system, or two 90 degree input signals. The homopolar output
detects the imbalance of a three-phase input only. Under normal conditions, this output will be zero.
Resolver-to-Digital Converter Interface
The AD2S100 can be used to sense overcurrent situations or
imbalances in a three-phase system via the homopolar output.
The AD2S100 provides general purpose interface for position
sensors used in the application of dc brushless and ac induction
motor control.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
(VDD = +5 V 6 5%; VSS = –5 V 6 5% AGND = DGND = O V; TA = –408C to
Parameter
Min
SIGNAL INPUTS
PH/IP1, 2, 3, 4 Voltage Level
PH/IPH1, 2, 3 Voltage Level
Input Impedance
PH/IP1, 2, 3
PH/IPH1, 2, 3
PH/IP1, 4
Gain
PH/IP1, 2, 3, 4
PH/IPH1, 2, 3
Conditions
± 2.8
63.3
± 4.25
V p-p
V p-p
DC to 50 kHz
DC to 50 kHz
kΩ
kΩ
MΩ
Mode 1 Only (2 Phase) Sin & Cos
0.98
1
0.56
1.02
0.35
9
0.7
18
24
50
200
± 2.8
2
2
1
3.0
2
± 3.3
5
Positive Pulse
µs
V dc
V dc
Conversion in Process
IOH = 0.5 mA
IOL = 0.5 mA
2.5
1.5
610
V dc
V dc
µA
pF
1.5
100
V dc
V dc
µA
pF
10
3.5
10
CONV2
DGND
VDD
V DD
1° Input to Settle to ± 1 LSB
(Input to Output)
ns
kHz
3.5
VDD
PH/IP, PH/IPH INPUTS
DC to 50 kHz
Inputs = 0 V
366
1
DGND
V p-p
mV
V/µs
µs
50
1.7
CONVERT MODE
(CONV1, CONV2)
VIH
VIL
Input Current
Input Capacitance
DC to 600 Hz
DC to 600 Hz
DC to 600 Hz
Guaranteed Monotonic
Ω
mA
kΩ
pF
15
4.0
4
DIGITAL INPUTS
DB1–DB12
VIH
VIL
Input Current, IIN
Input Capacitance, CIN
%
arc min
arc min
kHz
kHz
100
BUSY
Pulse Width
VOH
VOL
CONVERT LOGIC
CONV1
NO CONNECT
Units
10
18
ANALOG SIGNAL OUTPUTS
PH/OP1, 2, 3, 4
Output Voltage3
Offset Voltage
Slew Rate
Small Signal Step Response
STROBE
Write
Max Update Rate
Max
7.5
13.5
1
VECTOR PERFORMANCE
3θ Input-Output
Angular Error1, 2 (PH/IP)
(PH/IPH)
Monotonicity
Full Power Bandwidth
Small Signal Bandwidth
Output Resistance
Output Drive Current
Typ
Outputs to AGND
Internal 50 kΩ Pull-Up Resistor
2-Phase Orthogonal with 2 Inputs
Nominal Input Level
3-Phase (0°, 120°, 240°) with 3 Inputs
Nominal Input Level
3-Phase (0°, 120°, 240°) with 2 Inputs
Nominal Input Level
–2–
REV. A
Parameter
Min
HOMOPOLAR OUTPUT
HPOP–Output
VOH
VOL
HPREF–REFERENCE
4
HPFILT-FILTER
POWER SUPPLY
VDD
VSS
IDD
ISS
4.75
–5.25
Typ
Max
Units
Conditions
1
0.5
V dc
V dc
V dc
100
kΩ
IOH = 0.5 mA
IOL = 0.5 mA
Homopolar Output-Internal
ISOURCE = 25 µA and 20 kΩ
to AGND
Internal Resistor with External
Capacitor = 220 nF
5
–5
4
4
5.25
–4.75
10
10
V dc
V dc
mA
mA
Quiescent Current
Quiescent Current
NOTES
1
Angular accuracy includes offset and gain errors. Stationary digital input and maximum analog frequency inputs.
2
Included in the angular error is an allowance for the additional error caused by the phase delay as a function of input frequency. For example, if
fINPUT = 600 Hz, the contribution to the error due to phase delay is: 650 ns × fINPUT × 60 × 360 = 8.4 arc minutes.
3
Output subject to input voltage and gain.
Specifications in boldface are production tested.
Specifications subject to change without notice.
RECOMMENDED OPERATING CONDITIONS
ABSOLUTE MAXIMUM RATINGS (TA = +25°C)
Power Supply Voltage (+VDD, –VSS) . . . . . . . . . ± 5 V dc ± 5%
Analog Input Voltage (PH/IP1, 2, 3, 4) . . . . . . 2 V rms ± 10%
Analog Input Voltage (PH/IPH1, 2, 3) . . . . . . 3 V rms ± 10%
Ambient Operating Temperature Range
Industrial (AP) . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V dc
VSS to AGND . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V dc
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 0.3 V dc
Analog Input Voltage to AGND . . . . . . . . . . . . . . . VSS to VDD
Digital Input Voltage to DGND . . . . –0.3 V to VDD + 0.3 V dc
Digital Output Voltage to DGND . . . –0.3 V to VDD + 0.3 V dc
Analog Output Voltage to AGND
. . . . . . . . . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V dc
Analog Output Load Condition (PH/OP1, 2, 3, 4
Sinθ, Cosθ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 kΩ
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 mW
Operating Temperature
Industrial (AP) . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
ORDERING GUIDE
Model
Temperature Range
Accuracy
Option*
–40°C to +85°C
18 arc min
P-44A
*P = Plastic Leaded Chip Carrier.
CAUTION
1. Absolute Maximum Ratings are those values beyond which
damage to the device may occur.
2. Correct polarity voltages must be maintained on the +VDD
and –VSS pins.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD2S100 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
–3–
WARNING!
ESD SENSITIVE DEVICE
PIN DESIGNATIONS1, 2, 3
VDD
STROBE
NC
NC
BUSY
NC
DGND
VDD
NC
Begin Conversion
Positive Power Supply
Negative Power Supply
Sin (θ + φ)
Cos (θ + φ)
Cos (θ + 240° + φ)
Cos (θ + 120° + φ)
Analog Ground
Sin θ Input
High Level Cos (θ + 240°) Input
Cos (θ + 240°) Input
High Level Cos (θ + 120°) Input
Cos (θ + 120°) Input
High Level Cos θ Input
Cos (θ) Input
Negative Power Supply
Homopolar Reference
Homopolar Output
Homopolar Filter
Select Input Format (3 Phase/3 Wire, Sin θ
Cos θ/Input, 3 Phase/2 Wire)
Cos Output
Sin Output
(DB1 = MSB, DB12 = LSB
Parallel Input Data)
Positive Power Supply
Digital Ground
Conversion in Progress
VSS
6
5
4
3
2
1
44
43
42
41
40
PH/OP1 7
39 NC
PH/OP3
8
38 DB1
PH/OP2
9
37 DB2
AGND
10
PH/IP4
11
35 DB4
12
TOP VIEW
(NOT TO SCALE)
34 DB5
PH/IPH3
36 DB3
PH/IP3 13
PH/IPH2
33 DB6
14
32 DB7
PH/IP2 15
31 DB8
PH/IPH1 16
30 DB9
PH/IP1 17
22
23
24
25
26
27
28
COS
SIN
DB12
DB11
21
CONV2
20
CONV1
19
HPOP
18
HPFILT
29 DB10
HPREF
STROBE
VDD
VSS
PH/OP4
PH/OP1
PH/OP3
PH/OP2
AGND
PH/IP4
PH/IPH3
PH/IP3
PH/IPH2
PH/IP2
PH/IPH1
PH/IP1
VSS
HPREF
HPOP
HPFILT
CONV1
CONV2
COS
SIN
DB12
DB1
VDD
DGND
BUSY
PH/OP4
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
19
20
21
22
23
24
25
26
27
38
41
42
44
NC
Mnemonic Description
VSS
Pin
PIN CONFIGURATION
NC = NO CONNECT
NOTES
Signal Inputs Ph/IP and PH/IPH on Pin Nos 11 through 17.
1
90° orthogonal signals = Sin θ, Cos θ (Resolver) = PH/IP4 and PH/IP1.
2
Three phase, 120°, three-wire signals
= Cos θ, Cos (θ + 120°), Cos (θ + 240°).
= PH/IP1, PH/IP2, PH/IP3
High Level = PH/IPH1, PH/IPH2, PH/IPH3.
3
Three Phase, 120°, two-wire signals = Cos (θ + 120°), Cos (θ + 240°)
= PH/IP2, PH/IP3.
In all cases where any of the input Pins 11 through 17 are not used, they must
be left unconnected.
–4–
REV. A
To relate these stator current to the reference frame the rotor
currents assume the same rectangular coordinates, but are now
rotated by the operator ejf, where ejf = Cos f + jSin f.
THEORY OF OPERATION
A fundamental requirement for high quality induction motor
drives is that the magnitude and position of the rotating air-gap
rotor flux be known. This is normally carried out by measuring
the rotor position via a position sensor and establishing a rotor
reference frame that can be related to stator current coordinates.
Here the term vector rotator comes into play where the stator
current vector can be represented in rotor-based coordinates or
vice versa.
To generate a flux component in the rotor, stator current is applied. A build-up of rotor flux is concluded which must be
maintained by controlling the stator current, ids, parallel to the
rotor flux. The rotor flux current component is the magnetizing
current, imr.
The AD2S100 uses ejf as the core operator. Here f represents
the digital position angle which rotates as the rotor moves. In
terms of the mathematical function, it rotates the orthogonal ids
and iqs components as follows:
Torque is generated by applying a current component which is
perpendicular to the magnetizing current. This current is normally called the torque generating current, iqs.
where ids', iqs' = stator currents in the rotor reference frame. And
ids' + jiqs' = (Ids + jIqs) ejf
ejf = Cos f + jSin f
= (Ids + jIqs)(Cos f + jSin f)
To orient and control both the torque and flux stator current
vectors, a coordinate transformation is carried out to establish a
new reference frame related to the rotor. This complex calculation is carried out by the AD2S100 vector processor.
The output from the AD2S100 takes the form of:
ids' = Ids Cos f – Iqs Sin f
iqs' = Ids Sin f + Iqs Cos f
To expand upon the vector operator a description of a single
vector rotation is of assistance. If it is considered that the moduli of a vector is OP and that through the movement of rotor
position by f, we require the new position of this vector it can
be deduced as follows:
The matrix equation is:
[ ] [
ids'
iqs'
Let original vector OP = A (Cos u + jSIN u) where A is a
constant;
so if OQ = OP ejf
=
Cos f
– Sin f
Sin f
Cos f
] [ ]
Ids
Iqs
and it is shown in Figure 2.
φ
(1)
and: ejf = Cos f + jSin f
OQ = A (Cos (u + f) + jSin (u + f))
= A [Cos u Cos φ – Sin u Sin φ + jSin u Cos φ + jCos u Sin φ]
= A [(Cos u + jSin u) (Cos f + jSin f)]
ids
ids'
e jφ
(2)
iqs
iqs'
a
Q
Figure 2. AD2S100 Vector Rotation Operation
θ+φ
P
φ
INPUT CLARK
θ
COSθ
COSθ + 120°
COSθ + 240°
SINθ
d
O
3φ + 2φ
TRANSFORMATION
SINE AND
COSINE
MULTIPLIER
(DAC)
LATCH
Cos(θ + φ)
Figure 1. Vector Rotation in Polar Coordinate
DIGITAL
φ
The complex stator current vector can be represented as is = ias
j 2π
j 4π
and a2 = e
. This can be re3
3
placed by rectangular coordinates as
PARK
SINE AND
COSINE
MULTIPLIER
(DAC)
Cos(θ +(120° + φ))
Cos(θ +(240° + φ))
OUTPUT CLARK
(3)
Figure 3. Converter Operation Diagram
In this equation ids and iqs represent the equivalent of a twophase stator winding which establishes the same magnitude of
MMF in a three-phase system. These inputs can be seen after
the three-phase to two-phase transformation in the AD2S100
block diagram. Equation (3) therefore represents a three-phase
to two-phase conversion.
REV. A
2φ–3φ
LATCH
+ aibs + a2ics where a = e
is = ids + jiqs
LATCH
–5–
CONVERTER OPERATION
ANALOG SIGNAL INPUT AND OUTPUT CONNECTIONS
Input Analog Signals
The architecture of the AD2S100 is illustrated in Figure 3. The
AD2S100 is configured in the forward transformation which rotates the stator coordinates to the rotor reference frame.
All analog signal inputs to AD2S100 are voltages. There are two
different voltage levels of three-phase (0°, 120°, 240°) signal inputs. One is the nominal level, which is ± 2.8 V dc or 2 V rms
and the corresponding input pins are PH/IP1 (Pin 17), PH/IP2
(Pin 15), PH/IP3 (Pin 13) and PH/IP4 (Pin 11).
Forward Rotation
In this configuration the 3φ–2φ Clark is bypassed, and inputs are
fed directly into the quadrature (PH/IP4) and direct (PH/ IPI)
inputs to the Park transform, eiφ, where φ is defined by the
AD2S100’s digital input. Position data, φ, is loaded into the input latch on the positive edge of the strobe pulse. (For detail on
the timing, please refer to the “timing diagram.”) The negative
edge of the strobe signifies that conversion has commenced. A
busy pulse is subsequently produced as data is passed from the
of the multiplier, the busy pulse remains high to ensure simultaneous setting of φ in both the Sin and Cos registers.
The high level inputs can accommodate voltages from nominal
up to a maximum of ± VDD/VSS. The corresponding input pins
are PH/IPH1 (Pin 16), PH/IPH2 (Pin 14) and PH/IPH3 (Pin
12). The homopolar output can only be used in the three-phase
connection mode.
The converter can accept both two-phase format and threephase format input signals. For the two-phase format input, the
two inputs must be orthogonal to each other. For the threephase format input, there is the choice of using all three inputs
or using two of the three inputs. In the latter case, the third input signal will be generated internally by using the information
of other two inputs. The high level input mode, however, can
only be selected with three-phase/three-input format. All these
different conversion modes, including nominal/high input level
and two/three-phase input format can be selected using two select pins (Pin 23, Pin 24). The functions are summarized in
Table I.
The negative edge of the busy pulse signifies that the multipliers
time. The resultant two outputs are accessed via the PH/OPI
(Pin 7) and PH/OP4 (Pin 6), alternatively they can be directly
applied to the output Clark transform. The Clark output is the
vector sum of the analog input vector (Cosθ (PH/OPl), Cos (θ +
120°) (PH/OP2), Cos (θ + 240°) (PH/OP3) and the digital input vector φ.
For other configurations, please refer to “Forward and Reverse
Transformation.”
Table I. Conversion Mode Selection
CONV1
(Pin 23)
CONNECTING THE CONVERTER
Power Supply Connection
Mode
The power supply voltages connected to VDD and VSS pins
should be +5 V dc and –5 V dc and must not be reversed. Pin 4
(VDD) and Pin 41 (VDD) should both be connected to +5 V;
similarly, Pin 5 (VSS) and Pin 19 (VSS) should both be connected to –5 V dc.
MODE1 2-Phase Orthogonal with 2 Inputs
NC
Nominal Input Level
MODE2 3-Phase (0°, 120°, 240°) with 3 Inputs DGND
Nominal/High Input Level*
MODE3 3-Phase (0°, 120°, 240°) with 2 Inputs VDD
Nominal Input Level
It is recommended that decoupling capacitors, 100 nF (ceramic)
and 10 µF (tantalum) or other high quality capacitors, are connected in parallel between the power line VDD, VSS and AGND
adjacent to the converter. Separate decoupling capacitors should
be used for each converter. The connections are shown in Figure 4.
In this mode, either nominal or high level inputs can be used.
For nominal level input operation, PH/IP1, PH/IP2 and PH/IP3
are the inputs, and there should be no connections to PH/IPH1,
PH/IPH2 and PH/IPH3; similarly, for high level input operation, the PH/IPH1, PH/IPH2 and PH/IPH3 are the inputs, and
there should be no connections to PH/IP1, PH/IP2 and PH/IP3.
In both cases, the PH/IP4 should be left unconnected. For high
level signal input operation, select MODE2 only.
AGND
TOP VIEW
10µF
100nF
12
VDD
MODE2: 3-Phase/3 Inputs with Nominal/High Input Level
10µF
+
VDD
In this mode, PH/IP1 and PH/IP4 are the inputs and the Pins
12 through 16 must be left unconnected.
100nF
GND
DGND
MODE1: 2-Phase/2 Inputs with Nominal Input Level
VDD
VSS
VDD
1
CONV2
(Pin 24)
*The high level input mode can only be selected with MODE2.
+5V
+
Description
34
VSS
MODE3: 3-Phase/2 Inputs with Nominal Input Level
In this mode, PH/IP2 and PH/IP3 are the inputs and the third
signal will be generated internally by using the information of
other two inputs. It is recommended that PH/IP1, PH/IPH1,
PH/IPH2, PH/IP4 and PH/IPH3 should be left unconnected.
23
–5V
Figure 4. AD2S100 Power Supply Connection
–6–
REV. A
Output Analog Signals
Example: From the equivalent circuit, it can be seen that the inclusion of a 20 kΩ resistor will reduce Vts to ± 0.25 V dc. This
corresponds to an imbalance of ± 0.75 V dc in the inputs.
There are three forms of analog output from the AD2S100.
Sin/Cos orthogonal output signals are derived from the Clark/
three-to-two-phase conversion before the Park angle rotation.
These signals are available on Pin 25 (Cos u) and Pin 26 (Sin
u), and occur before Park angle rotation.
Homopolar Filtering
The equation VSUM = Cosu + Cos (u + 120°) + Cos (u + 240°)
= 0 denotes an imbalance when VSUM ≠ 0. There are conditions,
however, when an actual imbalance will occur and the conditions as defined by VSUM will be valid. For example, if the first
phase was open circuit when u = 90° or 270°, the first phase is
valid at 0 V dc. VSUM is valid, therefore, when Cosu is close to 0.
In order to detect an imbalance u has to move away from 90° or
270°, i.e., when on a balanced line Cos u ≠ 0.
Three-Phase Output Signals
(Cos (θ + φ), Cos (φ + θ + 120°), Cos (φ + θ + 240°)), where
φ represents digital input angle. These signals are available on
Pin 7 (PH/OP1), Pin 9 (PH/OP2) and Pin 8 (PH/OP3),
respectively.
Two-Phase (Sin (θ + φ), Cos (θ + φ)) Signals
Line imbalance is detected as a function of HPREF, either set
by the user or internally set at ± 0.5 V dc. This corresponds to a
dead zone when f = 90° or 270° ± 30°, i.e., VSUM = 0, and,
therefore, no indicated imbalance. If an external 20 kΩ resistor
is added, this halves Vts and reduces the zone to ± 15°. Note this
example only applies if the first phase is detached.
These represent the output of the coordinate transformation.
These signals are available on Pin 6 (PH/OP4, Sin (θ + φ)) and
Pin 7 (PH/OP1, Cos (θ + φ)).
HOMOPOLAR OUTPUT
HOMOPOLAR Reference
In a three-phase ac system, the sum of the three inputs to the
converter can be used to indicate whether or not the phases are
balanced.
In order to prevent this false triggering an external capacitor
needs to be placed from HPFILT to ground, as shown in Figure
5. This averages out the perceived imbalance over a complete
cycle and will prevent the HPOP from alternatively indicating
balance and imbalance over u = 0° to 360°.
If VSUM = PH/IP1 + PH/IP2 + PH/IP3 (or PH/IPH1 +
PH/IPH2 + PH/IPH3) this can be rewritten as VSUM = [Cosu, +
Cos (u + 120°) + Cos (u + 240°)] = 0. Any imbalances in the
line will cause the sum VSUM ≠ 0. The AD2S100 homopolar
output (HPOP) goes high when VSUM > 3 × Vts. The voltage
level at which the HPOP indicates an imbalance is determined
by the HPREF threshold, Vts. This is set internally at ± 0.5 V dc
(± 0.1 V dc). The HPOP goes high when
For
dθ
dt
dθ
(Cosθ + Cos(θ + 120° ) + Cos(θ + 240° ))
V ts <
×V
3
dt
= 100 rpm C EXT = 2.2 µF
Note: The slower the input rotational speed, the larger the time
constant required over which to average the HPOP output. Use
of the homopolar output at slow rotational speeds becomes
impractical with respect to the increased value for CEXT.
where V is the nominal input voltage.
With no external components VSUM must exceed ± 1.5 V dc in
order for HPOP to indicate an imbalance. The sensitivity of the
threshold can be reduced by connecting an external resistor between HPOP and ground in Figure 5 where,
V ts =
= 1000 rpm C EXT = 200 nF
34
0.5 REXT
DGND
REXT + 20000
TOP VIEW
REXT = Ω
Vts = V dc.
1
23
CEXT
220nF
HPFILT
HPOP
HPOP
AGND
HPREF
25µA
HOMOPOLAR
REFERENCE
TO TRIGGER
12
REXT
GND
Figure 6. AD2S100 Homopolar Output Connections
20kΩ
EXTERNAL
RESISTOR
Figure 5. The Equivalent Homopolar Reference Input
Circuitry
REV. A
HPREF
–7–
TIMING DIAGRAMS
Busy Output
TYPICAL CIRCUIT CONFIGURATION
The state of converter is indicated by the state of the BUSY output (Pin 44). The BUSY output will go HI at the negative edge
of the STROBE input. This is used to synchronize digital input
data and load the digital angular rotation information into the
device counter. The BUSY output will remain HI for 2 µs, and
go LO until the next strobe negative edge occurs.
TWO/THREE PHASE
OUTPUT
Figure 8 shows a typical circuit configuration for the AD2S100
in a three phase, nominal level input mode (MODE2).
38
TOP VIEW
MSB
34
16
PH/IP1
23
SIN
COS
PH/IP3
PH/IP2
30
27
STROBE
+5V
DIGITAL ANGLE INPUT
BUSY
41
10µF
PH/IP4
12
HPFILT
t4
1
STROBE
PH/OP2
AGND
THREE PHASE INPUT
The width of the positive STROBE pulse should be at least
100 ns, in order to successfully start the conversion. The maximum frequency of STROBE input is 366 kHz, i.e., there should
be at least 2.73 µs from the negative edge of one STROBE pulse
to the next rising edge. This is illustrated by the following timing diagram and table.
PH/OP1
PH/OP3
HPREF
HPOP
Strobe Input
100nF
LSB
t1
–5V
t2
tf
tr
BUSY
100nF
GND
10µF
t3
Figure 8. Typical Circuit Configuration
APPLICATIONS
Forward and ReverseTransformation
Note: Digital data should be stable 25 ns before and after positive strobe edge.
The AD2S100 can perform both forward and reverse transformations. The section “Theory of Operation” explains how the
chip operates with the core operator e+jφ, which performs a forward transformation. The reverse transformation, e–jφ, is not
mentioned in the above sections of the data sheet simply to
avoid the confusion in the functionality and pinout. However,
the reverse transformation is very useful in many different applications, and the AD2S100 can be easily configured in a reverse
transformation configuration. Figure 9 shows four different
phase input/output connections for AD2S100 reverse transformation operation.
Parameter
Min
t1
t2
t3
t4
tr
100 ns
Typ
Max
30 ns
1.7 µs
2.5 µs
100 ns
20 ns
150 ns
tf
10 ns
120 ns
Condition
STROBE Pulse Width
STROBE ↓ to BUSY ↑
BUSY Pulse Width
BUSY ↓ to STROBE ↑
BUSY Pulse Rise Time
BUSY Pulse Rise Time
BUSY Pulse Fall Time
BUSY Pulse Fall Time
REVERSE
TRANSFORMATION
FORWARD
TRANSFORMATION
3 PHASE – 3 PHASE
Cosθ
Cos(θ + 120°)
Cos(θ + 240°)
e+jφ
Cos(θ + φ)
Cosθ
2 PHASE – 2 PHASE
Sinθ
e+jφ
Cosθ
2 PHASE – 3 PHASE
3 PHASE – 2 PHASE
Sinθ
Cosθ
Cos(θ + 120°)
Cos(θ + 240°)
Cos(θ +φ)
Cos(θ + φ + 120°)
Cos(θ + φ + 240°)
e+jφ
Sin(θ + φ)
Cos(θ + φ)
Cos(θ + φ + 120°)
Cos(θ + φ + 240°)
Cos(θ + φ)
e+jφ
Sin(θ + φ)
Cosθ
Cos(θ + 120°)
Cos(θ + 240°)
e–jφ
e–jφ
Cosθ
Sinθ
e–jφ
–1
Cosθ
Cos(θ + 120°)
Cos(θ + 240°)
Cos(θ – φ + 240°)
Cos(θ – φ)
Cosθ
Sinθ
Cos(θ – φ)
Cos(θ – φ + 120°)
Sin(θ – φ)
Cos(θ – φ)
Cos(θ – φ + 120°)
Cos(θ – φ + 240°)
Cos(θ – φ)
e–jφ
Sin(θ – φ)
–1
Figure 9. Reverse Transformation Connections
–8–
REV. A
calculating power required in the rotor reference frame is significantly reduced because the currents and flux are rotating at the
slip frequency. This permits calculations to be carried out in
time frames of, 100 µs, or under by a fixed-point DSP. Benchmark timing in this type of architecture can attain floating-point
speed processing with a fixed-point processor. Perhaps the largest advantage is in the ease with which the rotor flux position
can be obtained. A large amount of computation time is, therefore, removed by the AD2S100 vector processors due to the
split architecture shown in Figure 11. Motor control systems
employing one DSP to carry out the cartesian to polar transformations required for vector control are, therefore, tasked with
additional duties due to the fact that they normally operate in
the flux reference frame.
√In Figure 9, “–1” operator performs a 180° phase shift operation. It can be illustrated by a 2-phase-to-3-phase reverse transformation. An example is shown in Figure 10.
Cosθ
PH/OP1
Cos(θ + φ)
PH/IP1 (Cosθ)
R
Cos(θ – φ)
PH/OP3
Cos(θ + 240° + φ)
Cos(θ + 120° – φ)
PH/IP4 (Sinθ)
PH/OP2
Cos(θ + 120° + φ)
Cos(θ + 240° – φ)
R
Sinθ
R
2
φ
Figure 10. Two-Phase to Three-Phase Reverse
Transformation
The robustness of the control system can also be increased by
carrying out the control in the rotor reference frame. This is
achieved through the ability to increase and improve both the
algorithm quality in nonlinear calculations attributed to magnetizing inductance and rotor time constant for example. An
increase in sampling time can also be concluded with this architecture by avoiding the additional computing associated with
number truncation and rounding errors which reduce the signalto-noise rejection ratio.
Field Oriented Control of AC Induction Machine in a Rotor
Flux Frame
The architecture shown in Figure 11 identifies a simplified
scheme where the AD2S100 permits the DSP computing core
to execute the motor control in what is normally termed the
rotor reference frame. This reference frame actually operates in
synchronism with the rotor of a motor. This has significant
benefits regarding motor control efficiency and economics. The
POSITION
FEEDBACK
VELOCITY
FEEDBACK v
v
POSITION
v SET POINT
SPEED
CONTROL
+
VECTOR
is1
CO-PROCESSOR
v
ε'
LIMIT
+ ω'
–
–
ε
(a + jb)e–jρ
Cm
TORQUE
CONTROL
LIMIT
Vqs'
+ iqs'
md'
–
ω
+ imr'
+ ids'
–
–
imr
+
VECTOR
CO-PROCESSOR
iqs
FIELD
WEAKENING
ω+
is2
imrmax
Vds'
Vs1
(a + jb)e'–jρ'
ids
ω1
Vs2
ρ'
ω2
Tr
θ2
+
REVERSE
ROTATION
+
ε
FORWARD
ROTATION
iqs
is3
ids
ρ
Figure 11. Rotor Reference Frame Architecture
REV. A
Vs3
iqs
–9–
SIMPLE SLIP CONTROL
In an adjustable-frequency drive, the control strategy must ensure that motor operation is restricted to low slip frequencies,
resulting in stable operation with a high power factor and a high
torque per stator ampere. Figure 12 shows the block diagram of
simple slip control using the AD2S100. Here, the slip frequency
command ω2 and the current amplitude command are sent to
the microprocessor to generate two orthogonal signals, |I| Sin θ
and |I| Cos θ here (θ = ω2.) With the actual shaft position angle,
φ, (resolver-to-digital converter) and the orthogonal signals from
Ia
I Sinθ
(I) SET
SLIP
FREQ
Ib
Ic
dθ
ω2 = dt
PWM
+
INVERTER
AC
INDUCTION
MTR
RESOLVER
φ
Figure 12. Slip Control of AC Induction Motor with
the µP, the AD2S100 generates the inverter frequency and amplitude command into a three-phase format. The three-phase
sine wave reference currents are reproduced in the stator phases.
bibliography at the end of the data sheet.
Electronically commutated permanent magnet synchronous
motors (PMSM) are used in high performance drives for
machine tools and robotics. When a field orientated control
scheme is deployed, the resulting brushless drive has all the
properties required for servo applications in machine tool fed
drives, industrial robots, and spindle drives. These properties
include large torque/inertia ratio, a high peak torque capability
for fast acceleration and deceleration with high torsional stiffness at standstill.
Figure 13 shows the AD2S100 configured for both forward and
reverse transformations. This architecture concludes both flux
and torque current components independently. The additional
control of Vd (flux component) allows for the implementation
of field weakening schemes and maintenance of power factor.
ω ref
+
PI
Iqref
+
PI
–
–
Idref
+
Vq
e–jφ
Vd
2/3
INV +
PWM
PI
PMSM
φ
–
Id
Iq
e+jφ
3/2
Va
Vb
Vc
For more detailed information, please refer to the application
note “Vector Control Using a Single Vector Rotation Semiconductor for Induction and Permanent Magnet Motors.”
MOTION CONTROL DSP COPROCESSOR
AC induction motors are superior to dc motors with respect to
size/power ratio, weight, rotor inertia, maximum rotating velocity, efficiency and cost for motor ratings greater than 5 HP.
However, because of nonlinear and the highly interactive multivariable control structure, ac induction motors have been considered difficult to control in applications demanding variable
speed and torque.
Field orientated control theory and practice, under development
since 1975, has offered the same level of control enjoyed by traditional dc machines. Practical implementation of these algorithms involves the use of DSP and microprocessor based
architectures. The AD2S100 removes the needs for software
implementation of the rotor-to-stator and stator-to-rotor transformations in the DSP or µP. The reduction in throughput
times from typically 100 µs (µP) and 40 µs (DSP) to 2 µs increases system bandwidths while also allowing additional features to be added to the CPU. The combination of the fixed
control engine” shown in Figure 14, enables bandwidths previously attainable only through the use of floating point devices.
For more detailed information on the AD2S100 vector control
refer to application notes “Vector Control Using a Single Vector
Rotation Semiconductor for Induction and Permanent Magnet
Motors.”
MEASUREMENT OF HARMONICS
Three-phase ac power systems are widely used in power generation, transmission and electric drive. The quality of the electricity supply is affected by harmonics injected into the power main.
In inverter fed ac machines, fluxes and currents of various frequencies are produced. Predominantly in ac machines the 5th
and 7th harmonics are the most damaging; their reaction with
the fundamental flux component produces 6th harmonic torque
pulsations. The subsequent pulsating torque output may result
in uneven motion of the motor, especially at low speeds.
The AD2S100 can be used to monitor and detect the presence
and magnitude of a particular harmonic on a three-phase line.
Figure 15 shows the implementation of such a scheme using the
AD2S100. Note, the actual line voltages will have to be scaled
before applying to the three-phase input of the AD2S100.
Selecting a harmonic is achieved by synchronizing the rotational
frequency of the park digital input, φ, with the frequency of the
fundamental flux component and the integer harmonic selected.
The update rate, r, of the counters is determined by:
ω
r = 4096
Figure 13. PMSM Servo Control Using AD2S100
n×ω
2π
Here, r = input clock pulse rate (pulses/second);
n = the order of harmonics to be measured;
ω = fundamental angular frequency of the ac signal.
–10–
REV. A
HOST COMPUTER
VECTOR
COPROCESSOR
VECTOR
COPROCESSOR
DAC
DAC-8412
INV
+
PWM
INDUCTION
MOTOR
θ
R/D
CONVERTER
ia, ib, ic
Figure 14. Advanced Motion Control Engine
The magnitude of the n-th harmonic as well as the fundamental
component in the power line is represented by the output of the
low-pass filter, ak. In concert with magnitude of the harmonic
the AD2S100 homopolar output will indicate whether the
application, refer to the related application note listed in the
bibliography.
MSB
MSB-1
.
.
.
MSB – (n–1)
.
.
.
LSB + (n–1)
n = POLES
.
.
.
.
Va
Vb
Vc
Vd1
Vd
TWO-TO-THREE
CLARK
TRANSFORMATION Vq
e–jφ PARK
TRANSFORMATION
LOW PASS
FILTER
MSB
MSB-1
MSB-2
.
.
.
.
.
.
.
LSB
ak
Vq1
12,14 OR 16-BIT RESOLUTION MODE
HOMOPOLAR
OUTPUT
12-BIT UP/DOWN
COUNTER
Figure 16. A General Consideration in Connecting R/D
Converter and AD2S100 for Multiple Pole Motors
PULSE INPUTS
DIRECTION
Figure 17 shows the AD2S80A configured for use with a four
pole motor, where n = 2. Using the formula described the MSB
is shifted left once
Figure 15. Harmonics Measurement Using AD2S100
For multi-pole motor applications where a single speed resolver
is used, the AD2S100 input has to be configured to match the
electrical cycle of the resolver with the phasing of the motor
windings. The input to the AD2S100 is the output of a resolverto-digital converter, e.g., AD2S80A series. The parallel output
of the converter needs to be multiplied by 2n–1, where
n = the number of pole parts of the motor. In practice this is
implemented by shifting the parallel output of the converter left
relative to the number of pole pairs.
Figure 16 shows the generic configuration of the AD2S80A with
the AD2S100 for a motor with n pole pairs. The MSB of the
AD2S100 is connected to MSB-(n-1) bit of the AD2S80A digital output, MSB-1 bit to MSB-(n-2) bit, . . ., LSB bit to LSB
REV. A
MULTIPLE POLE MOTORS
–11–
(MSB)
(LSB)
BIT1
BIT2
.
.
.
.
.
.
BIT13
BIT14
.
.
.
.
.
.
MSB
MSB-1
.
.
.
.
.
.
.
LSB
14-BIT RESOLUTION MODE
Figure 17. Connecting of R/D Converter AD2S80A and
The AD2S100 can be configured for use as a 12-bit digital-toresolver (DRC) or synchro converter (DSC). DRCs and DSCs
are used to simulate the outputs of a resolver or a synchro. The
simulated outputs are represented by the transforms outlined
below.
Resolver Outputs
Asinωt.cosφ
Asinωt.sinφ
DRC—Must Select Mode 1
Inputs
PH/IP4
PH/IP1
Outputs PH/OP1
PH/OP4
Pin 11
Pin 1
Pin 7
Pin 6
AGND
Reference Asinωt
Asinωt Cosφ
Asinωt Sinφ
DSC—Must Select Mode 1
Inputs
PH/IP4
PH/IP1
Outputs PH/OP1
PH/OP2
PH/OP3
Synchro Outputs
Asinωt.sinφ
Asinωt.sin (φ + 120°)
Asinωt.sin (φ + 240°)
where:
Configuring the AD2S100 for DRC and DSC operation is done
by the following.
C1938–18–7/94
DIGITAL-TO-RESOLVER AND SYNCHRO CONVERSION
Pin 11
Pin 17
Pin 7
Pin 9
Pin 8
Reference Asinωt
AGND
–Asinωt Sinφ
–Asinωt Sin (φ + 120°)
–Asinωt Sin (φ + 240°)
NOTES
1. Valid information is only available after the strobe pulse and BUSY go low.
2. To correct for inverse phasing of the DSC outputs the reference should be
inverted, or the MSB can be inverted.
Asinωt = fixed ac reference
φ = digital input angle, i.e., shaft position
The waveforms are shown in Figures 18 and 19.
APPLICATION NOTES LIST
1. “Vector Control Using a Single Vector Rotation Semiconductor for Induction and Permanent Magnet Motors,” by F. P.
Flett, Analog Devices.
S2 TO S4
(COS)
2. “Gamana – DSP Vector Coprocessor for Brushless Motor
Control,” by Analog Devices and Infosys Manufacturing
System.
S3 TO S1
(SIN)
3. “Silicon Control Algorithms for Brushless Permanent Magnet
Synchronous Machines,” by F. P. Flett.
4. “Single Chip Vector Rotation Blocks and Induction Motor
Field Oriented Control,” by A. P. M. Van den Bossche and
P. J. M. Coussens.
R2 TO R4
(REF)
0°
90 °
180 °
270°
360°
θ
Figure 18. Electrical Representation and Typical Resolver
Signals
5. “Three Phase Measurements with Vector Rotation Blocks in
Mains and Motion Control,” P. J. M. Coussens, et al.
6. “Digital to Synchro and Resolver Conversion with the AC
Vector Processor AD2S100,” by Dennis Fu.
7. “Experiment with the AD2S100 Evaluation Board,” by
Dennis Fu.
S1 TO S2
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
S2 TO S3
0.056 (1.42)
0.042 (1.07)
6
0°
90°
180 °
270 °
0.025 (0.63)
0.015 (0.38)
40
PIN 1
IDENTIFIER
7
0.048 (1.21)
0.042 (1.07)
R1 TO R2
0.180 (4.57)
0.165 (4.19)
39
0.021 (0.53)
0.013 (0.33)
0.63 (16.00)
0.59 (14.99)
360 °
θ
0.032 (0.81)
0.026 (0.66)
TOP VIEW
Figure 19. Electrical Representation and Typical Synchro
Signals
0.050
(1.27)
BSC
29
17
18
0.020
(0.50)
R
28
0.695 (17.65)
SQ
0.685 (17.40)
–12–
0.040 (1.01)
0.025 (0.64)
0.656 (16.66)
SQ
0.650 (16.51)
0.110 (2.79)
0.085 (2.16)
REV. A
PRINTED IN U.S.A.
0.048 (1.21)
0.042 (1.07)
S3 TO S1