M 24AA64/24LC64 64K I2C™ Serial EEPROM Device Selection Table Description Part Number VCC Range Max Clock Frequency Temp Ranges 24AA64 1.8-5.5 400 kHz(1) I 24LC64 2.5-5.5 400 kHz I, E Note 1: 100 kHz for VCC <2.5V Features Package Types PDIP/SOIC/TSSOP/MSOP A0 1 A2 3 Vss 4 ROTATED TSSOP (24AA64X/24LC64X) 8 Vcc 7 WP 6 SCL 5 SDA WP Vcc A0 A1 1 2 3 4 24XX64X A1 2 24XX64 • Single supply with operation down to 1.8V • Low power CMOS technology - 1 mA active current typical - 1 µA standby current (max.) (I-temp) • Organized as 8 blocks of 8K bit (64K bit) • 2-wire serial interface bus, I2C™ compatible • Cascadable for up to eight devices • Schmitt trigger inputs for noise suppression • Output slope control to eliminate ground bounce • 100 kHz (24AA64) and 400 kHz (24LC64) compatibility • Self-timed write cycle (including auto-erase) • Page-write buffer for up to 32 bytes • 2 ms typical write cycle time for page-write • Hardware write protect for entire memory • Can be operated as a serial ROM • Factory programming (QTP) available • ESD protection > 4,000V • 1,000,000 erase/write cycles • Data retention > 200 years • 8-lead PDIP, SOIC, TSSOP, and MSOP package • Available temperature ranges: - Industrial (I): -40°C to +85°C - Automotive (E): -40°C to +125°C The Microchip Technology Inc. 24AA64/24LC64 (24XX64*) is a 64 Kbit Electrically Erasable PROM. The device is organized as eight blocks of 1K x 8-bit memory with a 2-wire serial interface. Low voltage design permits operation down to 1.8V with standby and active currents of only 1 µA and 1 mA respectively. It has been developed for advanced, low power applications such as personal communications or data acquisition. The 24XX64 also has a page-write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space. The 24XX64 is available in the standard 8-pin PDIP, surface mount SOIC, TSSOP and MSOP packages. 8 7 6 5 SCL SDA Vss A2 Block Diagram A0 A1 A2 WP I/O CONTROL LOGIC MEMORY CONTROL LOGIC HV GENERATOR XDEC EEPROM ARRAY PAGE LATCHES I/O SCL YDEC SDA VCC VSS SENSE AMP R/W CONTROL *24XX64 is used in this document as a generic part number for the 24AA64/24LC64 devices. 2002 Microchip Technology Inc. DS21189E-page 1 24AA64/24LC64 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temp. with power applied ..........................................................................................................-40°C to +125°C ESD protection on all pins ......................................................................................................................................................≥ 4 kV † NOTICE: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 1.1 DC Characteristics DC CHARACTERISTICS VCC = +1.8V to +5.5V Industrial (I): TAMB = -40°C to +85°C Automotive (E): TAMB = -40°C to +125°C Param. No. Sym Characteristic Min Typ Max Units D1 VIH WP, SCL and SDA pins — — — — — D2 — High level input voltage 0.7 VCC — — V — Low level input voltage D3 VIL D4 VHYS D5 VOL Conditions — — 0.3 VCC V — 0.05 VCC — — V (Note 1) Low level output voltage — — 0.40 V IOL = 3.0 mA, VCC = 2.5V Hysteresis of Schmitt trigger inputs D6 ILI Input leakage current — — ±10 µA VIN =.1V to VCC D7 ILO Output leakage current — — ±10 µA VOUT =.1V to VCC D8 CIN, COUT Pin capacitance (all inputs/outputs) — — 10 pF VCC = 5.0V (Note 1) TAMB = 25°C, FCLK = 1 MHz D9 ICC write Operating current — 0.1 3 mA VCC = 5.5V, SCL = 400 kHz D10 ICC read — 0.05 1 mA — D11 ICCS — — .01 — 1 5 µA µA Industrial Automotive SDA = SCL = VCC WP = VSS Standby current Note 1: This parameter is periodically sampled and not 100% tested. 2: Typical measurements taken at room temperature. DS21189E-page 2 2002 Microchip Technology Inc. 24AA64/24LC64 1.2 AC Characteristics VCC = +1.8V to +5.5V Industrial (I): TAMB = -40°C to +85°C Automotive (E): TAMB = -40°C to +125°C AC CHARACTERISTICS Param. No. Sym 1 FCLK 2 Characteristic Min Max Units Conditions Clock frequency — — 400 100 kHz 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC < 2.5V (24AA64) THIGH Clock high time 600 4000 — — ns 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC < 2.5V (24AA64) 3 TLOW Clock low time 1300 4700 — — ns 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC < 2.5V (24AA64) 4 TR SDA and SCL rise time (Note 1) — — 300 1000 ns 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC < 2.5V (24AA64) 5 TF SDA and SCL fall time — 300 ns (Note 1) 6 THD:STA START condition hold time 600 4000 — — ns 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC < 2.5V (24AA64) 7 TSU:STA 600 4700 — — ns 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC < 2.5V (24AA64) 8 THD:DAT Data input hold time 9 TSU:DAT 10 TSU:STO STOP condition setup time START condition setup time Data input setup time Output valid from clock (Note 2) 0 — ns (Note 2) 100 250 — — ns 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC < 2.5V (24AA64) 600 4000 — — ns 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC < 2.5V (24AA64) — — 900 3500 ns 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC < 2.5V (24AA64) 1300 4700 — — ns 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC < 2.5V (24AA64) 11 TAA 12 TBUF Bus free time: Time the bus must be free before a new transmission can start 13 TOF Output fall time from VIH min- 20+0.1CB imum to VIL maximum — 250 250 ns 2.5V ≤ VCC ≤ 5.5V 1.8V ≤ VCC ≤ 2.5V (24AA64) 14 TSP Input filter spike suppression (SDA and SCL pins) — 50 ns (Notes 1 and 3) 15 TWC Write cycle time (byte or page) — 5 ms — 16 — Endurance 1M — cycles 25°C, VCC = 5.0V, Block Mode (Note 4) Note 1: Not 100% tested. CB = total capacitance of one bus line in pF. 2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 3: The combined TSP and V HYS specifications are due to new Schmitt trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. 4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance Model which can be obtained on Microchip’s website: www.microchip.com. 2002 Microchip Technology Inc. DS21189E-page 3 24AA64/24LC64 FIGURE 1-1: BUS TIMING DATA 5 4 2 3 SCL 7 SDA IN 8 9 10 6 14 12 11 SDA OUT FIGURE 1-2: BUS TIMING START/STOP D4 SCL 6 7 10 SDA START DS21189E-page 4 STOP 2002 Microchip Technology Inc. 24AA64/24LC64 2.0 FUNCTIONAL DESCRIPTION The 24XX64 supports a bi-directional 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, and a device receiving data as receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access and generates the START and STOP conditions, while the 24XX64 works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. 3.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (Figure 3-1). 3.1 Start Data Transfer (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 3.3 Stop Data Transfer (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations must be ended with a STOP condition. FIGURE 3-1: (A) Data Valid (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of the data bytes transferred between the START and STOP conditions is determined by the master device and is theoretically unlimited, although only the last sixteen will be stored when doing a write operation. When an overwrite does occur it will replace data in a first-in first-out (FIFO) fashion. 3.5 Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. Note: Bus not Busy (A) Both data and clock lines remain HIGH. 3.2 3.4 The 24XX64 does not generate any acknowledge bits if an internal programming cycle is in progress. The device that acknowledges, has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24XX64) will leave the data line HIGH to enable the master to generate the STOP condition. DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) (D) (C) (A) SCL SDA START CONDITION 2002 Microchip Technology Inc. ADDRESS OR DATA ACKNOWLEDGE ALLOWED VALID TO CHANGE STOP CONDITION DS21189E-page 5 24AA64/24LC64 3.6 Device Addressing FIGURE 3-2: A control byte is the first byte received following the start condition from the master device (Figure 3-2). The control byte consists of a four bit control code; for the 24XX64 this is set as 1010 binary for read and write operations. The next three bits of the control byte are the chip select bits (A2, A1, A0). The chip select bits allow the use of up to eight 24XX64 devices on the same bus and are used to select which device is accessed. The chip select bits in the control byte must correspond to the logic levels on the corresponding A2, A1, and A0 pins for the device to respond. These bits are in effect the three most significant bits of the word address. The last bit of the control byte defines the operation to be performed. When set to a one a read operation is selected, and when set to a zero a write operation is selected. The next two bytes received define the address of the first data byte (Figure 3-3). Because only A12...A0 are used, the upper three address bits are don’t care bits. The upper address bits are transferred first, followed by the less significant bits. Following the start condition, the 24XX64 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a 1010 code and appropriate device select bits, the slave device outputs an acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX64 will select a read or write operation. FIGURE 3-3: 0 Read/Write Bit Chip Select Bits Control Code S 1 0 1 0 A2 A1 A0 R/W ACK Slave Address Start Bit 3.7 Acknowledge Bit Contiguous Addressing Across Multiple Devices The chip select bits A2, A1, A0 can be used to expand the contiguous address space for up to 512K bits by adding up to eight 24XX64's on the same bus. In this case, software can use A0 of the control byte as address bit A13, A1 as address bit A14, and A2 as address bit A15. It is not possible to sequentially read across device boundaries. ADDRESS SEQUENCE BIT ASSIGNMENTS CONTROL BYTE 1 CONTROL BYTE FORMAT 1 CONTROL CODE DS21189E-page 6 0 A 2 A 1 ADDRESS HIGH BYTE A 0 R/W CHIP SELECT BITS X X X A A A 12 11 10 A 9 ADDRESS LOW BYTE A 8 A 7 • • • • • • A 0 X = Don’t Care Bit 2002 Microchip Technology Inc. 24AA64/24LC64 4.0 WRITE OPERATIONS 4.1 Byte Write Following the start condition from the master, the control code (four bits), the chip select (three bits), and the R/W bit (which is a logic low) are clocked onto the bus by the master transmitter. This indicates to the addressed slave receiver that the address high byte will follow after it has generated an acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the high-order byte of the word address and will be written into the address pointer of the 24XX64. The next byte is the least significant address byte. After receiving another acknowledge signal from the 24XX64 the master device will transmit the data word to be written into the addressed memory location. The 24XX64 acknowledges again and the master generates a stop condition. This initiates the internal write cycle, and during this time the 24XX64 will not generate acknowledge signals (Figure 4-1). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command but no write cycle will occur, no data will be written and the device will immediately accept a new command. After a byte write command, the internal address counter will point to the address location following the one that was just written. 4.2 Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size - 1]. If a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. 4.3 Write Protection The WP pin allows the user to write protect the entire array (0000-1FFF) when the pin is tied to VCC. If tied to VSS or left floating, the write protection is disabled. The WP pin is sampled at the STOP bit for every write command (Figure 3-1) Toggling the WP pin after the STOP bit will have no effect on the execution of the write cycle. Page Write The write control byte, word address and the first data byte are transmitted to the 24XX64 in the same way as in a byte write. But instead of generating a stop condition, the master transmits up to 31 additional bytes which are temporarily stored in the on-chip page buffer and will be written into memory after the master has transmitted a stop condition. After receipt of each word, the five lower address pointer bits are internally incremented by one. If the master should transmit more than 32 bytes prior to generating the stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the stop condition is received, an internal write cycle will begin (Figure 4-2). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command but no write cycle will occur, no data will be written and the device will immediately accept a new command. 2002 Microchip Technology Inc. DS21189E-page 7 24AA64/24LC64 FIGURE 4-1: BYTE WRITE BUS ACTIVITY MASTER S T A R T CONTROL BYTE ADDRESS HIGH BYTE A A S 1 0 1 0 A 2 1 0 0 SDA LINE S T O P DATA X X X A C K BUS ACTIVITY ADDRESS LOW BYTE P A C K A C K A C K X = don’t care bit FIGURE 4-2: PAGE WRITE BUS ACTIVITY MASTER S T A R T SDA LINE A A A S 1 0 1 0 2 1 0 0 BUS ACTIVITY CONTROL BYTE ADDRESS HIGH BYTE ADDRESS LOW BYTE DATA BYTE 0 S T O P DATA BYTE 31 X X X A C K P A C K A C K A C K A C K X = don’t care bit DS21189E-page 8 2002 Microchip Technology Inc. 24AA64/24LC64 5.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the stop condition for a write command has been issued from the master, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the master sending a start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the start bit and control byte must be re-sent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next read or write command. See Figure 5-1 for flow diagram. FIGURE 5-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? NO YES Next Operation 2002 Microchip Technology Inc. DS21189E-page 9 24AA64/24LC64 6.0 READ OPERATION 6.3 Read operations are initiated in the same way as write operations with the exception that the R/W bit of the control byte is set to one. There are three basic types of read operations: current address read, random read, and sequential read. 6.1 Current Address Read The 24XX64 contains an address counter that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the control byte with R/W bit set to one, the 24XX64 issues an acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer but does generate a stop condition and the 24XX64 discontinues transmission (Figure 6-1). 6.2 Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24XX64 transmits the first data byte, the master issues an acknowledge as opposed to the stop condition used in a random read. This acknowledge directs the 24XX64 to transmit the next sequentially addressed 8-bit word (Figure 6-3). Following the final byte transmitted to the master, the master will NOT generate an acknowledge but will generate a stop condition. To provide sequential reads the 24XX64 contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. The internal address pointer will automatically roll over from address 1FFF to address 0000 if the master acknowledges the byte received from the array address 1FFF. Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24XX64 as part of a write operation (R/W bit set to 0). After the word address is sent, the master generates a start condition following the acknowledge. This terminates the write operation, but not before the internal address pointer is set. Then the master issues the control byte again but with the R/W bit set to a one. The 24XX64 will then issue an acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer but does generate a stop condition which causes the 24XX64 to discontinue transmission (Figure 6-2). After a random read command, the internal address counter will point to the address location following the one that was just read. FIGURE 6-1: CURRENT ADDRESS READ BUS ACTIVITY MASTER S T A R T SDA LINE S BUS ACTIVITY DS21189E-page 10 CONTROL BYTE S T O P DATA (n) P A C K N O A C K 2002 Microchip Technology Inc. 24AA64/24LC64 FIGURE 6-2: RANDOM READ S T A R T BUS ACTIVITY MASTER SDA LINE CONTROL BYTE ADDRESS HIGH BYTE S1 0 1 0 AAA0 2 1 0 ADDRESS LOW BYTE XXX A C K BUS ACTIVITY S T A R T CONTROL BYTE S 1 0 1 0 A A A1 2 1 0 A C K A C K DATA n + 1 DATA n + 2 S T O P DATA BYTE P N O A C K A C K X = Don’t Care Bit FIGURE 6-3: SEQUENTIAL READ BUS ACTIVITY MASTER CONTROL BYTE DATA n S T O P DATA n + X P SDA LINE BUS ACTIVITY 2002 Microchip Technology Inc. A C K A C K A C K A C K N O A C K DS21189E-page 11 24AA64/24LC64 7.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 7-1. TABLE 7-1: PIN FUNCTION TABLE Name PDIP SOIC TSSOP MSOP ROTATED TSSOP A0 1 1 1 1 3 Chip Address Input A1 2 2 2 2 4 Chip Address Input A2 3 3 3 3 5 Chip Address Input VSS 4 4 4 4 6 Ground SDA 5 5 5 5 7 Serial Address/Data I/O Description SCL 6 6 6 6 8 Serial Clock WP 7 7 7 7 1 Write Protect Input VCC 8 8 8 8 2 +1.8V to 5.5V Power Supply 7.1 A0, A1, A2 Chip Address Inputs 7.3 Serial Clock (SCL) The A0,A1,A2 inputs are used by the 24XX64 for multiple device operation. The levels on these inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. This input is used to synchronize the data transfer from and to the device. Up to eight devices may be connected to the same bus by using different chip select bit combinations. These inputs must be connected to either VCC or VSS. This pin can be connected to either VSS, VCC or left floating. An internal pull-down resistor on this pin will keep the device in the unprotected state if left floating. If tied to VSS or left floating, normal memory operation is enabled (read/write the entire memory 0000-1FFF). 7.2 Serial Data (SDA) This is a bi-directional pin used to transfer addresses and data into and data out of the device. It is an opendrain terminal, therefore, the SDA bus requires a pullup resistor to VCC (typical 10 kΩ for 100 kHz, 2 kΩ for 400 kHz) 7.4 Write Protect (WP) If tied to VCC, WRITE operations are inhibited. Read operations are not affected. For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions. DS21189E-page 12 2002 Microchip Technology Inc. 24AA64/24LC64 8.0 PACKAGING INFORMATION 8.1 Package Marking Information 8-Lead PDIP (300 mil) Example: XXXXXXXX XXXXXNNN YYWW 24LC64 I/PNNN YYWW 8-Lead SOIC (150 mil) Example: 24LC64 I/SNYYWW NNN XXXXXXXX XXXXYYWW NNN 8-Lead SOIC (208 mil) Example: XXXXXXXX XXXXXXXX YYWWNNN 24LC64 I/SM YYWWNNN Example: 8-Lead TSSOP XXXX XYWW NNN 8-Lead MSOP IYWW NNN Example: XXXXXX 4L64I YWWNNN YWWNNN Legend: Note: * 4L64 Rotated TSSOP marking will be “4LBX” XX...X YY WW NNN Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. Standard OTP marking consists of Microchip part number, year code, week code, and traceability code. 2002 Microchip Technology Inc. DS21189E-page 13 24AA64/24LC64 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L c A1 β B1 p eB B Units Dimension Limits n p Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L c § B1 B eB α β MIN .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 INCHES* NOM MAX 8 .100 .155 .130 .170 .145 .313 .250 .373 .130 .012 .058 .018 .370 10 10 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MIN MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 DS21189E-page 14 2002 Microchip Technology Inc. 24AA64/24LC64 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 h α 45× c A2 A f β L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D h L f c B α β MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 A1 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MIN MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 2002 Microchip Technology Inc. DS21189E-page 15 24AA64/24LC64 8-Lead Plastic Small Outline (SM) – Medium, 208 mil (SOIC) E E1 p D 2 n 1 B α c A2 A φ L β Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L φ c B α β MIN .070 .069 .002 .300 .201 .202 .020 0 .008 .014 0 0 INCHES* NOM 8 .050 .075 .074 .005 .313 .208 .205 .025 4 .009 .017 12 12 A1 MAX .080 .078 .010 .325 .212 .210 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.78 1.97 1.75 1.88 0.05 0.13 7.62 7.95 5.11 5.28 5.13 5.21 0.51 0.64 0 4 0.20 0.23 0.36 0.43 0 12 0 12 MIN MAX 2.03 1.98 0.25 8.26 5.38 5.33 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. Drawing No. C04-056 DS21189E-page 16 2002 Microchip Technology Inc. 24AA64/24LC64 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) E E1 p D 2 1 n B α A c A1 f β A2 L Units Dimension Limits n p Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Molded Package Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic A A2 A1 E E1 D L f c B α β MIN INCHES NOM MAX 8 .026 .033 .002 .246 .169 .114 .020 0 .004 .007 0 0 .035 .004 .251 .173 .118 .024 4 .006 .010 5 5 .043 .037 .006 .256 .177 .122 .028 8 .008 .012 10 10 MILLIMETERS* NOM MAX 8 0.65 1.10 0.85 0.90 0.95 0.05 0.10 0.15 6.25 6.38 6.50 4.30 4.40 4.50 2.90 3.00 3.10 0.50 0.60 0.70 0 4 8 0.09 0.15 0.20 0.19 0.25 0.30 0 5 10 0 5 10 MIN Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005” (0.127mm) per side. JEDEC Equivalent: MO-153 Drawing No. C04-086 2002 Microchip Technology Inc. DS21189E-page 17 24AA64/24LC64 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) E p E1 D 2 B n 1 α A2 A A1 c φ (F) L β Units Number of Pins Pitch Dimension Limits n p Overall Height NOM MAX 8 0.65 .026 A .044 .030 Standoff A1 .002 E .184 Molded Package Width MIN 8 A2 Overall Width MAX NOM Molded Package Thickness § MILLIMETERS* INCHES MIN 1.18 .038 0.76 .006 0.05 .193 .200 .034 0.86 0.97 4.67 4.90 .5.08 0.15 E1 .114 .118 .122 2.90 3.00 3.10 Overall Length D .114 .118 .122 2.90 3.00 3.10 Foot Length L .016 .022 .028 0.40 0.55 0.70 Footprint (Reference) .035 .037 .039 0.90 0.95 1.00 Foot Angle F φ 6 0 Lead Thickness c .004 .006 .008 0.10 0.15 0.20 Lead Width B α .010 .012 .016 0.25 0.30 0.40 Mold Draft Angle Top Mold Draft Angle Bottom β 0 6 7 7 7 7 *Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. Drawing No. C04-111 DS21189E-page 18 2002 Microchip Technology Inc. 24AA64/24LC64 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site. Connecting to the Microchip Internet Web Site Systems Information and Upgrade Hot Line The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-480-792-7302 for the rest of the world. 013001 The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP service to connect to: ftp://ftp.microchip.com The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A variety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: • Latest Microchip Press Releases • Technical Support Section with Frequently Asked Questions • Design Tips • Device Errata • Job Postings • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events 2002 Microchip Technology Inc. DS21189E-page 19 24AA64/24LC64 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager RE: Reader Response Total Pages Sent From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Device: 24AA64/24LC64 Y N Literature Number: DS21189E Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS21189E-page 20 2002 Microchip Technology Inc. 24AA64/24LC64 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X /XX Temperature Package Range Examples: a) b) Device: 1.8V, 64 Kbit I2C Serial EEPROM 1.8V, 64 Kbit I2C Serial EEPROM (Tape and Reel) 24AA64X 1.8V, 64 Kbit I2C Serial EEPROM in alternate pinout (ST only) 24AA64XT 1.8V, 64 Kbit I2C Serial EEPROM in alternate pinout (ST only) 24LC64: 2.5V, 64 Kbit I2C Serial EEPROM 24LC64T: 2.5V, 64 Kbit I2C Serial EEPROM (Tape and Reel) 24LC64X 2.5V, 64 Kbit I2C Serial EEPROM in alternate pinout (ST only) 24LC64XT 2.5V, 64 Kbit I2C Serial EEPROM in alternate pinout (ST only) 24AA64: 24AA64T: Temperature I Range: E = = -40°C to +85°C -40°C to +125°C Package: = = = = = Plastic DIP (300 mil body), 8-lead Plastic SOIC (150 mil body), 8-lead Plastic SOIC (208 mil body), 8-lead Plastic TSSOP (4.4 mm), 8-lead Plastic Micro Small Outline (MSOP), 8-lead P SN SM ST MS c) 24AA64-I/P: Industrial Temperature, PDIP package 24AA64-I/SN: Industrial Temperature, SOIC package 24AA64-I/SM: Industrial Temperature, SOIC (208 mil) package d) 24AA64X-I/ST: Industrial Temperature, Rotated TSSOP package a) 24LC64-I/P: Industrial Temperature, PDIP package 24LC64-E/SN: Extended Temperature, SOIC package 24LC64-E/SM: Extended Temperature, b) c) SOIC (208 mil) package d) 24LC64X-I/ST : Extended Temperature, Rotated TSSOP package Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. 2002 Microchip Technology Inc. DS21189E-page21 24AA64/24LC64 NOTES: DS21189E-page 22 2002 Microchip Technology Inc. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microID, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Term Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro ® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs and microperipheral products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified. 2002 Microchip Technology Inc. DS21189E - page 23 M WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC Corporate Office Australia 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: http://www.microchip.com Microchip Technology Australia Pty Ltd Suite 22, 41 Rawson Street Epping 2121, NSW Australia Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 Rocky Mountain China - Beijing 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7966 Fax: 480-792-7456 Microchip Technology Consulting (Shanghai) Co., Ltd., Beijing Liaison Office Unit 915 Bei Hai Wan Tai Bldg. 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Le Colleoni 1 20041 Agrate Brianza Milan, Italy Tel: 39-039-65791-1 Fax: 39-039-6899883 United Kingdom Arizona Microchip Technology Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 01/18/02 *DS21189E* DS21189E-page 24 2002 Microchip Technology Inc.