0 XC17V00 Series Configuration PROM R DS073 (v1.5) October 9, 2001 0 8 Features Advance Product Specification • Available in compact plastic packages: VQ44, PC44, PC20, VO8, and SO20 • One-time programmable (OTP) read-only memory designed to store configuration bitstreams of Xilinx FPGA devices • Programming support by leading programmer manufacturers. • Simple interface to the FPGA • • Cascadable for storing longer or multiple bitstreams Design support using the Xilinx Alliance and Foundation series software packages. • Programmable reset polarity (active High or active Low) for compatibility with different FPGA solutions • Dual configuration modes for the XC17V16 and XC17V08 devices • Low-power CMOS Floating Gate process • 3.3V supply voltage • - Serial slow/fast configuration (up to 33 Mb/s) - Parallel (up to 264 Mb/s at 33 MHz) Guaranteed 20 year life data retention Description Xilinx introduces the high-density XC17V00 family of configuration PROMs which provide an easy-to-use, cost-effective method for storing large Xilinx FPGA configuration bitstreams. Initial devices in the 3.3V family are available in 16 Mb, 8 Mb, 4 Mb, 2 Mb, and 1 Mb densities. See Figure 1 and Figure 2 for simplified block diagrams of the XC17V00 family. When the FPGA is in SelectMAP mode, an external oscillator will generate the configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data are available on the PROMs DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK. A free-running oscillator may be used to drive CCLK. See Figure 3. When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When the FPGA is in Slave Serial mode, the PROM and the FPGA must both be clocked by an incoming signal. Multiple devices can be concatenated by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. All devices are compatible and can be cascaded with other members of the family. For device programming, either the Xilinx Alliance or Foundation series development system compiles the FPGA design file into a standard Hex format, which is then transferred to most commercial PROM programmers. © 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS073 (v1.5) October 9, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 1 R XC17V00 Series Configuration PROM VCC RESET/ OE or OE/ RESET VPP GND CEO CE Address Counter CLK TC EPROM Cell Matrix OE Output DATA DS073_01_072600 Figure 1: Simplified Block Diagram for XC17V04, XC17V02, and XC17V01 (does not show programming circuit) VCC RESET/ OE or OE/ RESET VPP GND CEO CE CLK Address Counter TC BUSY EPROM Cell Matrix OE Output 8 D0 Data (Serial or Parallel Mode) 7 7 D[1:7] (SelectMAP Interface) DS073_02_072600 Figure 2: Simplified Block Diagram for XC17V16 and XC17V08 (does not show programming circuit) 2 www.xilinx.com 1-800-255-7778 DS073 (v1.5) October 9, 2001 Advance Product Specification R XC17V00 Series Configuration PROM Pin Description BUSY (XC17V16 and XC17V08 only) DATA[0:7] If BUSY pin is floating, the user must program the BUSY bit which will cause BUSY pin to be internally tied to a pull-down resistor. When asserted High, output data are held and when BUSY pin goes Low, data output will resume. Data output is in a high-impedance state when either CE or OE are inactive. During programming, the D0 pin is I/O. Note that OE can be programmed to be either active High or active Low. Note: XC17V04, XC17V02, and XC17V01 have serial output only. CLK Each rising edge on the CLK input increments the internal address counter, if both CE and OE are active. RESET/OE When High, this input holds the address counter reset and puts the DATA output in a high-impedance state. The polarity of this input pin is programmable as either RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as RESET/OE, although the opposite polarity is possible on all devices. When RESET is active, the address counter is held at “0”, and puts the DATA output in a high-impedance state. The polarity of this input is programmable. The default is active High RESET, but the preferred option is active Low RESET, because it can connected to the FPGAs INIT pin and a pullup resistor. VPP Programming voltage. No overshoot above the specified max voltage is permitted on this pin. For normal read operation, this pin must be connected to VCC. Failure to do so may lead to unpredictable, temperature-dependent operation and severe problems in circuit debugging. Do not leave VPP floating! VCC and GND Positive supply and ground pins. PROM Pinouts for XC17V16 and XC17V08 (Pins not listed are “no connect”) Pin Name 44-pin VQFP 44-pin PLCC BUSY 24 30 D0 40 2 D1 29 35 The polarity of this pin is controlled in the programmer interface. This input pin is easily inverted using the Xilinx HW-130 Programmer. Third-party programmers have different methods to invert this pin. D2 42 4 D3 27 33 D4 9 15 CE D5 25 31 When High, this pin disables the internal address counter, puts the DATA output in a high-impedance state, and forces the device into low-ICC standby mode. D6 14 20 D7 19 25 CLK 43 5 CEO RESET/OE (OE/RESET) 13 19 CE 15 21 GND 6, 18, 28, 37, 41 3, 12, 24, 34, 43 CEO 21 27 VPP 35 41 VCC 8, 16, 17, 26, 36, 38 14, 22, 23, 32, 42, 44 Chip Enable output, to be connected to the CE input of the next PROM in the daisy chain. This output is Low when the CE and OE inputs are both active AND the internal address counter has been incremented beyond its Terminal Count (TC) value. In other words: when the PROM has been read, CEO will follow CE as long as OE is active. When OE goes inactive, CEO stays High until the PROM is reset. Note that OE can be programmed to be either active High or active Low. Capacity DS073 (v1.5) October 9, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 Devices Configuration Bits XC17V16 16,777,216 XC17V08 8,388,608 3 R XC17V00 Series Configuration PROM PROM Pinouts for XC17V04, XC17V02, and XC17V01 (Pins not listed are “no connect”) 8-pi 20-pin VOIC SOIC Pin Name (1) (1) 20-pin PLCC 44-pin VQFP 44-pin PLCC (1,2) (2) (2) Xilinx FPGAs and Compatible PROMs Device Configuration Bits PROM XCV400 2,546,048 XC17V04 XCV600 3,607,968 XC17V04 XCV800 4,715,616 XC17V08 DATA 1 1 1 40 2 XCV1000 6,127,744 XC17V08 CLK 2 3 3 43 5 XCV50E 630,048 XC17V01 RESET/OE (OE/RESET) 3 8 8 13 19 XCV100E 863,840 XC17V01 XCV200E 1,442,106 XC17V01 CE 4 10 10 15 21 XCV300E 1,875,648 XC17V02 GND 5 11 11 18, 41 24, 3 XCV400E 2,693,440 XC17V04 XCV405E 3,430,400 XC17V04 CEO 6 13 13 21 27 XCV600E 3,961,632 XC17V04 VPP 7 18 18 35 41 XCV812E 6,519,648 XC17V08 VCC 8 20 20 38 44 XCV1000E 6,587,520 XC17V08 XCV1600E 8,308,992 XC17V08 XCV2000E 10,159,648 XC17V16 XCV2600E 12,922,336 XC17V16 XCV3200E 16,283,712 XC17V16 Notes: 1. XC17V01 available in these packages. 2. XC17V02 and XC17V04 available in these packages. Capacity Devices Configuration Bits XC17V04 4,194,304 XC17V02 2,097,152 XC17V01 1,679,360 Notes: 1. The suggested PROM is determined by compatibility with the higher configuration frequency of the Xilinx FPGA CCLK. Controlling PROMs Connecting the FPGA device with the PROM. • The DATA output(s) of the PROM(s) drives the DIN input of the lead FPGA device. • The Master FPGA CCLK output drives the CLK input(s) of the PROM(s). • The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). • The RESET/OE input of all PROMs is best driven by the INIT output of the lead FPGA device. This connection assures that the PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. • The PROM CE input is best connected to the FPGA DONE pin(s) and a pullup resistor. CE can also be permanently tied Low, but this keeps the DATA output active and causes an unnecessary supply current of 15 mA maximum. • SelectMAP mode is similar to Slave Serial mode. The DATA is clocked out of the PROM one byte per CCLK instead of one bit per CCLK cycle. See FPGA data sheets for special configuration requirements. Xilinx FPGAs and Compatible PROMs 4 Device Configuration Bits PROM XC2V40 360,160 XC17V01 XC2V80 635,360 XC17V01 XC2V250 1,697,248 XC17V02 XC2V500 2,761,952 XC17V04 XC2V1000 4,082,656 XC17V04 XC2V1500 5,659,360 XC17V08 XC2V2000 7,492,064 XC17V08 XC2V3000 10,494,432 XC17V16 XC2V4000 15,660,000 XC17V16 XC2V6000 21,849, 568 XC17V16 + XC17V08 XC2V8000 29,063,072 2 of XC17V16 XCV50 559,200 XC17V01 XCV100 781,216 XC17V01 XCV150 1,040,096 XC17V01 XCV200 1,335,840 XC17V01 XCV300 1,751,808 XC17V02 www.xilinx.com 1-800-255-7778 DS073 (v1.5) October 9, 2001 Advance Product Specification R XC17V00 Series Configuration PROM FPGA Master Serial Mode Summary The I/O and logic functions of the Configurable Logic Block (CLB) and their associated interconnections are established by a configuration program. The program is loaded either automatically upon power up, or on command, depending on the state of the three FPGA mode pins. In Master Serial mode, the FPGA automatically loads the configuration program from an external memory. The Xilinx PROMs have been designed for compatibility with the Master Serial mode. address and bit counters which are incremented on every valid rising edge of CCLK. If the user-programmable, dual-function DIN pin on the FPGA is used only for configuration, it must still be held at a defined level during normal operation. The Xilinx FPGA families take care of this automatically with an on-chip default pull-up/down resistor or keeper circuit. Cascading Configuration PROMs Upon power-up or reconfiguration, an FPGA enters the Master Serial mode whenever all three of the FPGA mode-select pins are Low (M0=0, M1=0, M2=0). Data is read from the PROM sequentially on a single data line. Synchronization is provided by the rising edge of the temporary signal CCLK, which is generated during configuration. For multiple FPGAs configured as a daisy-chain, or for future FPGAs requiring larger configuration memories, cascaded PROMs provide additional memory. After the last bit from the first PROM is read, the next clock signal to the PROM asserts its CEO output Low and disables its DATA line. The second PROM recognizes the Low level on its CE input and enables its DATA output. See Figure 3. Master Serial Mode provides a simple configuration interface. Only a serial data line, two control lines, and a clock line are required to configure an FPGA. Data from the PROM is read sequentially, accessed via the internal After configuration is complete, the address counters of all cascaded PROMs are reset if the FPGA PROGRAM pin goes Low, assuming the PROM reset polarity option has been inverted. DS073 (v1.5) October 9, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 5 R XC17V00 Series Configuration PROM OPTIONAL Daisy-chained FPGAs with different configurations DOUT VCC 4.7K FPGA OPTIONAL Slave FPGAs with identical configurations VCC 4.7K Modes(1) VCC VCC VCC (2) VCC DATA DIN CCLK CLK DONE CE Vpp VCC BUSY First PROM CEO OE/RESET INIT Vpp BUSY DATA CLK CE Cascaded PROM OE/RESET PROGRAM (Low Resets the Address Pointer) (1) For Mode pin connections, refer to the appropriate FPGA data sheet. (2) Virtex, Virtex-E is 300 ohms, all others are 4.7K. Master Serial Mode I/O(1) I/O(1) Modes(3) WRITE VIRTEX SelectMAP BUSY 1K 1K 3.3V VCC DONE INIT VCC Vpp 4.7K First CLK PROM (2) CCLK PROGRAM D[0:7] VCC VCC External Osc(4) CS 8 D[0:7] VCC BUSY CEO Vpp BUSY Second CLK PROM CEO D[0:7] CE CE OE/RESET OE/RESET (1) CS and WRITE must be pulled down to be used as I/O. One option is shown. (2) Virtex, Virtex-E is 300 ohms, all others are 4.7K. (3) For Mode pin connections, refer to the appropriate FPGA data sheet. (4) External oscillator required for Virtex/E SelectMAP or Virtex-II slave SelectMAP modes. Virtex SelectMAP Mode, XC17V16 and XC17V08 only. DS073_03_100901 Figure 3: (a) Master Serial Mode (b) Virtex SelectMAP Mode (dotted lines indicates optional connection) 6 www.xilinx.com 1-800-255-7778 DS073 (v1.5) October 9, 2001 Advance Product Specification R XC17V00 Series Configuration PROM Standby Mode Programming The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high impedance state regardless of the state of the OE input. The devices can be programmed on programmers supplied by Xilinx or qualified third-party vendors. The user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. The wrong choice can permanently damage the device. Table 1: Truth Table for XC17V00 Control Inputs Control Inputs Outputs RESET CE Internal Address DATA CEO ICC Inactive Low If address < TC(1): increment If address > TC(1): don’t change Active High-Z High Low Active Reduced Active Low Held reset High-Z High Active Inactive High Not changing High-Z High Standby Active High Held reset High-Z High Standby Notes: 1. The XC17V00 RESET input has programmable polarity 1. TC = Terminal Count = highest address value. TC + 1 = address 0. DS073 (v1.5) October 9, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 7 R XC17V00 Series Configuration PROM Absolute Maximum Ratings Symbol Description Conditions Units VCC Supply voltage relative to GND –0.5 to +7.0 V VPP Supply voltage relative to GND –0.5 to +12.5 V VIN Input voltage relative to GND –0.5 to VCC +0.5 V VTS Voltage applied to High-Z output –0.5 to VCC +0.5 V TSTG Storage temperature (ambient) –65 to +150 pC TSOL Maximum soldering temperature (10s @ 1/16 in.) +260 pC Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions (3V Supply) Symbol VCC(1) TVCC Description Min Max Units Supply voltage relative to GND (TA = 0pC to +70pC) Commercial 3.0 3.6 V Supply voltage relative to GND (TA = –40pC to +85pC) Industrial 3.0 3.6 V 1.0 50 ms VCC rise time from 0V to nominal voltage Notes: 1. During normal read operation VPP must be connected to VCC. 2. At power up, the device requires the VCC power supply to monotonically rise from 0V to nominal voltage within the specified VCC rise time. If the power supply cannot meet this requirement, then the device may not power-on-reset properly. DC Characteristics Over Operating Condition Symbol Min Max Units VIH High-level input voltage 2 VCC V VIL Low-level input voltage 0 0.8 V VOH High-level output voltage (IOH = –3 mA) 2.4 - V VOL Low-level output voltage (IOL = +3 mA) - 0.4 V ICCA Supply current, active mode (at maximum frequency) (XC17V16 and XC17V08 only) - 100 mA ICCA Supply current, active mode (at maximum frequency) (XC17V04, XC17V02, and XC17V01 only) - 15 mA ICCS Supply current, standby mode - 1 mA IL Input or output leakage current –10 10 NA Input capacitance (VIN = GND, f = 1.0 MHz) - 15 pF Output capacitance (VIN = GND, f = 1.0 MHz) - 15 pF CIN COUT 8 Description www.xilinx.com 1-800-255-7778 DS073 (v1.5) October 9, 2001 Advance Product Specification R XC17V00 Series Configuration PROM AC Characteristics Over Operating Condition for XC17V04, XC17V02, and XC17V01 CE TSCE TSCE THCE RESET/OE THOE THC TLC TCYC CLK TOE TCE TCAC TDF TOH DATA TOH DS073_04_072600 Symbol Description Min Max Units TOE OE to data delay - 30 ns TCE CE to data delay - 45 ns TCAC CLK to data delay - 45 ns TDF CE or OE to data float delay(2,3) - 50 ns TOH Data hold from CE, OE, or CLK(3) 0 - ns TCYC Clock periods 67 - ns TLC CLK Low time(3) 25 - ns THC CLK High time(3) 25 - ns TSCE CE setup time to CLK (to guarantee proper counting) 25 - ns THCE CE hold time to CLK (to guarantee proper counting) 0 - ns THOE OE hold time (guarantees counters are reset) 25 - ns Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. DS073 (v1.5) October 9, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 9 R XC17V00 Series Configuration PROM AC Characteristics Over Operating Condition for XC17V16 and XC17V08 CE TSCE TSCE THCE RESET/OE THOE THC TLC TCYC CLK TOE TCE TDF TOH TCAC DATA TSBUSY TOH THBUSY BUSY DS073_05_072600 Symbol Description Min Max Units TOE OE to data delay - 15 ns TCE CE to data delay - 20 ns TCAC CLK to data delay(2) - 20 ns TDF CE or OE to data float delay(3,4) - 35 ns TOH Data hold from CE, OE, or CLK(4) 0 - ns TCYC Clock periods 50 - ns TLC CLK Low time(4) 25 - ns THC CLK High time(4) 25 - ns TSCE CE setup time to CLK (to guarantee proper counting) 25 - ns THCE CE hold time to CLK (to guarantee proper counting) 0 - ns THOE OE hold time (guarantees counters are reset) 25 - ns TSBUSY BUSY setup time 5 - ns THBUSY BUSY hold time 5 - ns Notes: 1. AC test load = 50 pF. 2. When BUSY = 0. 3. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels. 4. Guaranteed by design, not tested. 5. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 10 www.xilinx.com 1-800-255-7778 DS073 (v1.5) October 9, 2001 Advance Product Specification R XC17V00 Series Configuration PROM AC Characteristics Over Operating Condition When Cascading OE/RESET CE CLK TCDF TOCE Last Bit DATA First Bit TOCK TOOE CEO DS026_07_020300 Symbol Description Min Max Units TCDF CLK to data float delay(2,3) - 50 ns TOCK CLK to CEO delay(3) - 30 ns TOCE CE to CEO delay(3) - 35 ns TOOE RESET/OE to CEO delay(3) - 30 ns Notes: 1. AC test load = 50 pF 2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. DS073 (v1.5) October 9, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 11 R XC17V00 Series Configuration PROM Ordering Information XC17V16 PC44 C Device Number XC17V16 XC17V08 XC17V04 XC17V02 XC17V01 Operating Range/Processing Package Type VQ44 PC44 V08 PC20 SO20 = = = = = 44-pin Plastic Quad Flat Package 44-pin Plastic Chip Carrier 8-pin Plastic Small Outline Thin Package 20-pin Plastic Leaded Chip Carrier 20-pin Plastic Small Outline Package C = Commercial (TA = 0p to +70pC) I = Industrial (TA = –40p to +85pC) Valid Ordering Combinations XC17V16VQ44C XC17V08VQ44C XC17V04PC20C XC17V02PC20C XC17V01PC20C XC17V16PC44C XC17V08PC44C XC17V04PC44C XC17V02PC44C XC17V01VO8C XC17V16VQ44I XC17V08VQ44I XC17V04VQ44C XC17V02VQ44C XC17V01SO20C XC17V16PC44I XC17V08PC44I XC17V04PC20I XC17V02PC20I XC17V01PC20I XC17V04PC44I XC17V02PC44I XC17V01VO8I XC17V04VQ44I XC17V02VQ44I XC17V01SO20I Marking Information Due to the small size of the commercial serial PROM packages, the complete ordering part number cannot be marked on the package. The XC prefix is deleted and the package code is simplified. Device marking is as follows: XC17V16 PC44 C Device Number XC17V16 XC17V08 XC17V04 XC17V02 XC17V01 12 Operating Range/Processing Package Type VQ44 PC44 V08 PC20 SO20 = = = = = 44-pin Plastic Quad Flat Package 44-pin Plastic Chip Carrier 8-pin Plastic Small Outline Thin Package 20-pin Plastic Leaded Chip Carrier 20-pin Plastic Small Outline Package www.xilinx.com 1-800-255-7778 C = Commercial (TA = 0p to +70pC) I = Industrial (TA = –40p to +85pC) DS073 (v1.5) October 9, 2001 Advance Product Specification R XC17V00 Series Configuration PROM Revision History The following table shows the revision history for this document. Date Version Revision 07/26/00 1.0 Initial Xilinx release. 10/09/00 1.1 Updated 20-pin PLCC Pinouts. 11/16/00 1.2 Updated pinouts for XC17V16 and XC17V08, ICCA DC Characteristic from standby to active mode; CIN and COUT from 10 pF to 15 pF, added ICCS for XC17V16 and XC17V08 at 500 NA. 02/20/01 1.3 Added note to pinouts for “no connect,” updated Figure 3. 04/04/01 1.4 Added XC2V products to Compatible PROM table, updated Figure 3, updated text for Virtex-II FPGAs. 10/09/01 1.5 Corrected bitstream length for SCV405E, added power-on supply requirements and note for power-on reset, updated configuration bits for Virtex-II devices, removed CF from Figure 3, and updated FPGA list. DS073 (v1.5) October 9, 2001 Advance Product Specification www.xilinx.com 1-800-255-7778 13