0 QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM R DS125 (v1.0) December 16, 2003 0 5 Advance Product Specification Features Description • Operating Temperature Range: –55° C to +125° C • Low-power advanced CMOS FLASH process memory cells immune to static single event upset • In-system programmable 3.3V PROMs for configuration of Xilinx FPGAs Xilinx introduces the QPro™ XQ18V04 Military Grade 4Mbit in-system programmable configuration Flash PROM (see Figure 1). The XQ18V04 is a 3.3V rewritable PROM that provides a reliable non-volatile method for storing large Xilinx FPGA configuration bitstreams used in systems that require operation over the full military temperature range. - Endurance of 20,000 program/erase cycles • IEEE Std 1149.1 boundary-scan (JTAG) support • Cascadable for storing longer or multiple bitstreams • Dual configuration modes - Serial Slow/Fast configuration (up to 20 MHz) - Parallel (up to 160 Mbps at 20 MHz) • 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals • 3.3V or 2.5V output capability • Available in plastic VQ44 packaging only • Design support using the Xilinx Alliance Series™ and Xilinx Foundation Series™ software packages • JTAG command initiation of standard FPGA configuration When the FPGA is in Master Serial mode, it generates a configuration clock that drives the PROM. A short access time after the rising CCLK, data is available on the PROM DATA (D0) pin that is connected to the FPGA DIN pin. The FPGA generates the appropriate number of clock pulses to complete the configuration. When the FPGA is in Slave Serial mode, the PROM and the FPGA are clocked by an external clock. When the FPGA is in SelectMAP mode (Slave), an external oscillator will generate the configuration clock that drives the PROM and the FPGA. After the rising CCLK edge, data is available on the PROMs DATA (D0-D7) pins. The data will be clocked into the FPGA on the following rising edge of the CCLK. See Figure 3. Multiple devices can be cascaded by using the CEO output to drive the CE input of the following device. The clock inputs and the DATA outputs of all PROMs in this chain are interconnected. The XQ18V04 is compatible and can be cascaded with other configuration PROMs such as the XQR1701L and XQR17V16 one-time programmable configuration PROMs. OE/Reset CLK CE TCK TMS TDI Control and JTAG Interface TDO Data Memory Address Data CEO Serial or Parallel Interface 7 D0 DATA (Serial or Parallel [Express/SelectMAP] Mode) D[1:7] Express Mode and SelectMAP Interface CF DS026_01_021000 Figure 1: XQ18V04 Series Block Diagram © 2001 – 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm. All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS125 (v1.0) December 16, 2003 Advance Product Specification www.xilinx.com 1-800-255-7778 1 R QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM Xilinx FPGAs and Compatible PROMs Table 1: FPGA Configuration Storage Requirements Device Configuration Bits XQ18V04 PROMs XQV300 1,751,808 1 XQV600 3,607,968 1 XQV1000 6,127,744 2 XQ2V1000 3,752,736 1 XQ2V3000 9,594,656 3 XQ2V6000 19,759,904 5 Express/SelectMap mode is similar to slave serial mode. The DATA is clocked out of the PROM one byte per CCLK instead of one bit per CCLK cycle. See FPGA data sheets for special configuration requirements. The XQ18V04 device incorporates a pin named CF that is controllable through the JTAG CONFIG instruction. Executing the CONFIG instruction through JTAG pulses CF Low for 300 to 500 ns, which resets the FPGA and initiates configuration. The CF pin must be connected to the PROGRAM pin on the FPGA(s) to use this feature. The Xilinx iMPACT™ software can also issue a JTAG CONFIG command to initiate FPGA configuration through the "Load FPGA" setting. Table 2: PROM Storage Capacity Device Configuration Bits XQ18V04 4,194,304 Selecting Configuration Modes Connecting Configuration PROMs When connecting the FPGA device with the configuration PROM (see Figure 3): • The DATA output(s) of the PROM(s) drives the DIN input of the lead FPGA device. • The Master FPGA CCLK output drives the CLK input(s) of the PROM(s) in Master Serial and Master SelectMAP modes. • The CEO output of a PROM drives the CE input of the next PROM in a daisy chain (if any). • The OE/RESET input of all PROMs is best driven by the INIT output of the lead FPGA device. This connection ensures that the PROM address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a VCC glitch. • The PROM CE input can be driven from the DONE pin. The CE input of the first (or only) PROM can be driven by the DONE output of the first FPGA device, provided that DONE is not permanently grounded. CE also can be tied permanently Low, but this keeps the DATA output active and causes an unnecessary supply current of 20 mA maximum. 2 • Initiating FPGA Configuration Capacity • left unconnected when the PROM operates in serial mode. The XQ18V04 accommodates serial and parallel methods of configuration. The configuration modes are selectable through a user control register in the XQ18V04 device. This control register is accessible through JTAG, and is set using the "Parallel mode" setting on the Xilinx iMPACT software. Serial output is the default programming mode. Cascading Configuration PROMs For multiple FPGAs configured as a serial daisy-chain, or a single FPGA requiring larger configuration memories in a serial or SelectMAP configuration mode, cascaded PROMs provide additional memory (see Figure 2). Multiple XQ18V04 devices can be cascaded by using the CEO output to drive the CE input of the downstream device. The clock inputs and the data outputs of all the XQ18V04 devices in the chain are interconnected. After the last bit from the first PROM is read, the next clock signal to the PROM asserts its CEO output Low and drives its DATA line to a high-impedance state. The second PROM recognizes the Low level on its CE input and enables its DATA output. See Figure 3. After configuration is complete, the address counters of all cascaded PROMs are reset if the PROM OE/RESET pin goes Low. D1-D7 remain in a high-impedance state and can be www.xilinx.com 1-800-255-7778 DS125 (v1.0) December 16, 2003 Advance Product Specification R QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM Vcc Vcco Vcc Vcco Vcc 4.7K Vcc MODE PINS* Vcc DOUT DIN DIN Vcc D0 Vcco J1 TDI TMS TCK TDO 1 2 3 4 D0 Vcc Vcco XQ18V04 XQ18V04 Cascaded PROM First PROM Vcc MODE PINS* Xilinx FPGA Xilinx FPGA Master Serial Slave Serial ** CLK CCLK CCLK TMS CE TMS CE DONE DONE TCK CEO TCK CEO TDI GND CLK TDI OE/RESET OE/RESET CF CF TDO GND TDO INIT INIT PROGRAM PROGRAM TDI TDI TMS TMS TCK TDO * For Mode pin connections, refer to the appropriate FPGA data sheet. ** Resistor value is 300 ohms for Virtex and Virtex-E devices, and 4.7K ohms for all others. TCK TDO DS026_08_120103 Figure 2: JTAG Chain for Configuring Devices in Master Serial Mode DS125 (v1.0) December 16, 2003 Advance Product Specification www.xilinx.com 1-800-255-7778 3 R QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM OPTIONAL Daisy-chained FPGAs with different configurations DOUT FPGA OPTIONAL Slave FPGAs with identical configurations Vcco Vcc VCC 4.7K Modes* VCC ** VCC VCCO DATA First CLK PROM CEO CE DIN CCLK DONE INIT DATA Cascaded PROM CLK CE OE/RESET OE/RESET CF CF PROGRAM (Low Resets the Address Pointer) *For Mode pin connections, refer to the appropriate FPGA data sheet. **Resistor value is 300 ohms for Virtex and Virtex-E devices, and 4.7K ohms for all others. Master Serial Mode I/O* I/O* Modes*** WRITE 1K Virtex Select MAP NC VCC VCCO VCC VCCO CS External Osc 1K 3.3V VCC BUSY 4.7K XQ18V04 ** CCLK CLK 8 PROGRAM D[0:7] D[0:7] CE DONE OE/RESET INIT CEO CF *CS and WRITE must be pulled down to be used as I/O. One option is shown. **Resistor value is 300 ohms for Virtex and Virtex-E devices, and 4.7K ohms for all others. ***For Mode pin connections, refer to the appropriate FPGA data sheet. Virtex Select MAP Mode VCC VCC VCC VCCO VCC 4.7K VCC 4.7K VCCO D[0:7] 8 M0 CS1 M1 DOUT XQ4000XL M1 CS1 DOUT Optional Daisy-chained XQ4000XL D[0:7] D[0:7] CEO XQ18V04 CE M0 To Additional Optional Daisy-chained Devices CF OE/RESET CLK PROGRAM DONE INIT PROGRAM DONE INIT CCLK CCLK To Additional Optional Daisy-chained Devices External Osc XQ4000XL Express Mode DS082_05_120103 Figure 3: (a) Master Serial Mode (b) Virtex SelectMAP Mode (c) XQ4000XL Express Mode (dotted lines indicate optional connection) 4 www.xilinx.com 1-800-255-7778 DS125 (v1.0) December 16, 2003 Advance Product Specification R QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM 5V Tolerant I/Os The I/Os on each re-programmable PROM are fully 5V tolerant even through the core power supply is 3.3V. This allows 5V CMOS signals to connect directly to the PROM inputs without damage. In addition, the 3.3V VCC power supply can be applied before or after 5V signals are applied to the I/Os. In mixed 5V/3.3V/2.5V systems, the user pins, the core power supply (VCC), and the output power supply (VCCO) may have power applied in any order. This makes the PROM devices immune to power supply sequencing issues. state regardless of the state of the OE input. JTAG pins TMS, TDI, and TDO can be in a high-impedance state or High. See Table 3. Customer Control Bits The XQ18V04 PROMs have various control bits accessible by the customer. These can be set after the array has been programmed using “Skip User Array” in Xilinx iMPACT software. The iMPACT software can set these bits to enable the optional JTAG read security, parallel configuration mode, or CF-->D4 pin function. Reset Activation 3.6V Recommended Operating Range 3.0V Recommended Volts On power up, OE/RESET is held Low until the XQ18V04 is active (1 ms) and is able to supply data after receiving a CCLK pulse from the FPGA. OE/RESET is connected to an external resistor to pull OE/RESET High releasing the FPGA INIT and allowing configuration to begin. OE/RESET is held Low until the XQ18V04 voltage reaches the operating voltage range. If the power drops below 2.0V, the PROM will reset. OE/RESET polarity is NOT programmable. See Figure 4 for power-on requirements. Standby Mode VCCINT Rise Time 0V 0ms 1ms 50ms Time (ms) The PROM enters a low-power standby mode whenever CE is asserted High. The output remains in a high-impedance ds026_10_102303 Figure 4: VCCINT Power-On Requirements Table 3: Truth Table for PROM Control Inputs Control Inputs Outputs OE/RESET CE Internal Address DATA CEO ICC High Low If address < TC(1): increment If address > TC(1): don’t change Active High-Z High Low Active Reduced Low Low Held reset High-Z High Active High High Held reset High-Z High Standby Low High Held reset High-Z High Standby Notes: 1. TC = Terminal Count = highest address value. TC + 1 = address 0. DS125 (v1.0) December 16, 2003 Advance Product Specification www.xilinx.com 1-800-255-7778 5 R QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM In-System Programming In-System Programmable PROMs can be programmed individually, or two or more can be chained together and programmed in-system via the standard 4-pin JTAG protocol as shown in Figure 5. In-system programming offers quick and efficient design iterations and eliminates unnecessary package handling or socketing of devices. The Xilinx development system provides the programming data sequence using either Xilinx iMPACT software and a download cable, a third-party JTAG development system, a JTAG-compatible board tester, or a simple microprocessor interface that emulates the JTAG instruction sequence. The iMPACT software also outputs serial vector format (SVF) files for use with any tools that accept SVF format and with automatic test equipment. All outputs are held in a high-impedance state or held at clamp levels during in-system programming. OE/RESET The ISP programming algorithm requires issuance of a reset that will cause OE to go Low. boundary-scan manufacturing tools, with an in-system programmable option for future enhancements and design changes. Reliability and Endurance Xilinx in-system programmable products provide a guaranteed endurance level of 2,000 in-system program/erase cycles and a minimum data retention of ten years. Each device meets all functional, performance, and data retention specifications within this endurance limit. Design Security The Xilinx in-system programmable PROM devices incorporate advanced data security features to fully protect the programming data against unauthorized reading. Table 4 shows the security setting available. The read security bit can be set by the user to prevent the internal programming pattern from being read or copied via JTAG. When set, it allows device erase. Erasing the entire device is the only way to reset the read security bit. Table 4: Data Security Options External Programming Xilinx reprogrammable PROMs can also be programmed by the Xilinx HW-130, the Xilinx MultiPRO, or a third party device programmer. This provides the added flexibility of using pre-programmed devices in board design and Default = Reset Set Read Allowed Program/Erase Allowed Verify Allowed Read Inhibited via JTAG Program/Erase Allowed Verify Inhibited V CC GND (a) (b) DS026_02_011100 Figure 5: In-System Programming Operation (a) Solder Device to PCB and (b) Program Using Download Cable 6 www.xilinx.com 1-800-255-7778 DS125 (v1.0) December 16, 2003 Advance Product Specification R QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM IEEE 1149.1 Boundary Scan (JTAG) The XQ18V04 is fully compliant with the IEEE Std. 1149.1 Boundary Scan, also known as JTAG. A Test Access Port (TAP) and registers are provided to support all required boundary-scan instructions, as well as many of the optional instructions specified by IEEE Std. 1149.1. In addition, the JTAG interface is used to implement in-system programming (ISP) to facilitate configuration, erasure, and verification operations on the XQ18V04 device. Table 5 lists the required and optional boundary-scan instructions supported in the XQ18V04. Refer to the IEEE Std. 1149.1 specification for a complete description of boundary-scan architecture and the required and optional instructions. Binary Code [7:0] Description BYPASS 11111111 Enables BYPASS SAMPLE/ PRELOAD 00000001 Enables boundary-scan SAMPLE/PRELOAD operation EXTEST 00000000 Enables boundary-scan EXTEST operation Optional Instructions CLAMP 11111010 Enables boundary-scan CLAMP operation HIGHZ 11111100 All outputs in high-impedance state simultaneously IDCODE 11111110 Enables shifting out 32-bit IDCODE USERCODE 11111101 Enables shifting out 32-bit USERCODE XQ18V04 Specific Instructions 11101110 IR[4] IR[3] IR[2] IR[1:0] 000 ISP Status Security 0 01 ->TDO Notes: 1. IR[1:0] = 01 is specified by IEEE Std. 1149.1. The boundary-scan register is used to control and observe the state of the device pins during the EXTEST, SAMPLE/PRELOAD, and CLAMP instructions. Each output pin on the XQ18V04 has two register stages that contribute to the boundary-scan register, while each input pin only has one register stage. For each output pin, the register stage nearest to TDI controls and observes the output state, and the second stage closest to TDO controls and observes the High-Z enable state of the pin. For each input pin, the register stage controls and observes the input state of the pin. Identification Registers The IDCODE is a fixed, vendor-assigned value that is used to electrically identify the manufacturer and type of the device being addressed. The IDCODE register is 32 bits wide. The IDCODE register can be shifted out for examination by using the IDCODE instruction. The IDCODE is available to any other system component via JTAG. The IDCODE register has the following binary format: vvvv:ffff:ffff:aaaa:aaaa:cccc:cccc:ccc1 Initiates FPGA configuration by pulsing CF pin Low where v = the die version number f = the family code (50h for the XQ18V04) Instruction Register The Instruction Register (IR) for the XQ18V04 is eight bits wide and is connected between TDI and TDO during an instruction scan sequence. In preparation for an instruction scan sequence, the instruction register is parallel loaded with a fixed instruction capture pattern. This pattern is shifted out onto TDO (LSB first), while an instruction is DS125 (v1.0) December 16, 2003 Advance Product Specification TDI-> IR[7:5] Boundary-Scan Register Required Instructions CONFIG The ISP Status field, IR[4], contains logic "1" if the device is currently in ISP mode; otherwise, it will contain logic "0". The Security field, IR[3], will contain logic "1" if the device has been programmed with the security option turned on; otherwise, it will contain logic "0". Figure 6: Instruction Register Values Loaded into IR as Part of an Instruction Scan Sequence Table 5: Boundary Scan Instructions Boundary-Scan Command shifted into the instruction register from TDI. The detailed composition of the instruction capture pattern is illustrated in Figure 6. a = the ISP PROM product ID (26h for the XQ18V04) c = the company code (49h for Xilinx) Note: The LSB of the IDCODE register is always read as logic "1" as defined by IEEE Std. 1149.1. www.xilinx.com 1-800-255-7778 7 R QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM Table 6 lists the IDCODE register values for the XQ18V00 devices. The USERCODE instruction gives access to a 32-bit user programmable scratch pad typically used to supply information about the device’s programmed contents. By using the USERCODE instruction, a user-programmable identification code can be shifted out for examination. This code is loaded into the USERCODE register during programming of the XQ18V04 device. If the device is blank or was not loaded during programming, the USERCODE register will contain FFFFFFFFh. Table 6: IDCODEs Assigned to XQ18V04 Devices ISP PROM IDCODE XQ18V04 05036093h XQ18V04 TAP Characteristics TAP Timing The XQ18V04 device performs both in-system programming and IEEE 1149.1 boundary-scan (JTAG) testing via a single 4-wire Test Access Port (TAP). This simplifies system designs and allows standard Automatic Test Equipment to perform both functions. The AC characteristics of the XQ18V04 TAP are described as follows. Figure 7 shows the timing relationships of the TAP signals. These TAP timing characteristics are identical for both boundary-scan and ISP operations. TCKMIN TCK TMSS TMSH TMS TDIS TDIH TDI TDOV TDO DS026_04_020300 Figure 7: Test Access Port Timing TAP AC Parameters Table 7 shows the timing parameters for the TAP waveforms shown in Figure 7. Table 7: Test Access Port Timing Parameters 8 Symbol Parameter Min Max Units TCKMIN TCK minimum clock period 200 - ns TMSS TMS setup time 10 - ns TMSH TMS hold time 25 - ns TDIS TDI setup time 10 - ns TDIH TDI hold time 25 - ns TDOV TDO valid delay - 25 ns www.xilinx.com 1-800-255-7778 DS125 (v1.0) December 16, 2003 Advance Product Specification R QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM Absolute Maximum Ratings(1,2) Table 8: Absolute Maximum Ratings Symbol Description Value Units Supply voltage relative to GND –0.5 to +4.0 V VIN Input voltage with respect to GND –0.5 to +5.5 V VTS Voltage applied to High-Z output –0.5 to +5.5 V TSTG Storage temperature (ambient) –65 to +150 °C Ceramic +150 °C Plastic +125 °C +220 °C VCCINT/VCCO TJ TSOL Junction temperature Maximum soldering temperature Notes: 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the device pins may undershoot to –2.0V or overshoot to +7.0V, provided this overshoot or undershoot lasts less then 10 ns and with the forcing current being limited to 200 mA. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operating Conditions Table 9: Recommended Operating Conditions Symbol VCCINT VCCO Parameter Min Max Units Internal voltage supply (TC = –55° C to +125° C) Ceramic 3.0 3.6 V Internal voltage supply (TJ = –55° C to +125° C) Plastic 3.0 3.6 V Supply voltage for output drivers for 3.3V operation 3.0 3.6 V Supply voltage for output drivers for 2.5V operation 2.3 2.7 V VIL Low-level input voltage 0 0.8 V VIH High-level input voltage 2.0 5.5 V VO Output voltage 0 VCCO V VCCINT rise time from 0V to nominal voltage1 1 50 ms TVCC Notes: 1. At power up, the device requires the VCCINT power supply to monotonically rise from 0V to nominal voltage within the specified VCCINT rise time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. Quality and Reliability Characteristics Table 10: Reliability Characteristics Symbol Description Min Max Units 10 - Years TDR Data retention NPE Program/erase cycles (Endurance) 20,000 - Cycles VESD Electrostatic discharge (ESD) 2,000 - Volts DS125 (v1.0) December 16, 2003 Advance Product Specification www.xilinx.com 1-800-255-7778 9 R QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM DC Characteristics Over Operating Conditions Table 11: DC Characteristics Symbol VOH Test Conditions Min Max Units 2.4 - V 90% VCCO - V High-level output voltage for 3.3V outputs IOH = –4 mA High-level output voltage for 2.5V outputs IOH = –500 µA Low-level output voltage for 3.3V outputs IOL = 8 mA - 0.4 V Low-level output voltage for 2.5V outputs IOL = 500 µA - 0.4 V ICC Supply current, active mode 25 MHz - 50 mA ICCS Supply current, standby mode - 20 mA IILJ JTAG pins TMS, TDI, and TDO VCC = MAX VIN = GND –100 - µA IIL Input leakage current VCC = Max VIN = GND or VCC –10 10 µA IIH Input and output High-Z leakage current VCC = Max VIN = GND or VCC –10 10 µA Input and output capacitance VIN = GND f = 1.0 MHz - 10 pF VOL CIN and COUT 10 Parameter www.xilinx.com 1-800-255-7778 DS125 (v1.0) December 16, 2003 Advance Product Specification R QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM AC Characteristics Over Operating Conditions for XQ18V04 . CE TSCE THCE OE/RESET THC TLC THOE TCYC CLK TOE TCE TCAC TDF TOH DATA TOH DS026_06_012000 Figure 8: Pin-to-Pin Timing Diagram Table 12: AC Timing Characteristics for Single Device Symbol Description Min Max Units TOE OE/RESET to data delay - 10 ns TCE CE to data delay - 20 ns TCAC CLK to data delay - 20 ns TOH Data hold from CE, OE/RESET, or CLK 0 - ns TDF CE or OE/RESET to data float delay(2) - 25 ns Clock periods 50 - ns TLC CLK Low time(3) 10 - ns THC CLK High time(3) 10 - ns TSCE CE setup time to CLK (to guarantee proper counting)(3) 25 - ms THCE CE High time (to guarantee proper counting) 2 - µs THOE OE/RESET hold time (guarantees counters are reset) 25 - ns TCYC Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 5. If THCE High < 2 µs, TCE = 2 µs. DS125 (v1.0) December 16, 2003 Advance Product Specification www.xilinx.com 1-800-255-7778 11 R QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM AC Characteristics Over Operating Conditions When Cascading for XQ18V04 OE/RESET CE CLK TCDF TOCE Last Bit DATA First Bit TOCK TOOE CEO DS026_07_020300 Figure 9: Pin-to-Pin Timing Diagram for Cascaded Devices Table 13: AC Timing Characteristics for Cascaded Devices Symbol Description Min Max Units TCDF CLK to data float delay(2,3) - 25 ns TOCK CLK to CEO delay(3) - 20 ns TOCE CE to CEO delay(3) - 20 ns TOOE OE/RESET to CEO delay(3) - 20 ns Notes: 1. AC test load = 50 pF. 2. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels. 3. Guaranteed by design, not tested. 4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V. 12 www.xilinx.com 1-800-255-7778 DS125 (v1.0) December 16, 2003 Advance Product Specification R QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM Pinout and Pin Description Table 14: Pin Names and Descriptions (pins not listed are “no connect”) Pin Number Pin Name Boundary Scan Order Function Pin Description VQFP D0 4 DATA OUT 40 3 OUTPUT ENABLE D0 is the DATA output pin to provide data for configuring an FPGA in serial mode. 6 DATA OUT 29 5 OUTPUT ENABLE D0-D7 are the output pins to provide parallel data for configuring a Xilinx FPGA in Express/SelectMap mode. D1-D7 remain in HIGHZ state and can be left unconnected when the PROM operates in serial mode. 2 DATA OUT 1 OUTPUT ENABLE 8 DATA OUT 7 OUTPUT ENABLE 24 DATA OUT 23 OUTPUT ENABLE 10 DATA OUT 9 OUTPUT ENABLE 17 DATA OUT 16 OUTPUT ENABLE 14 DATA OUT 13 OUTPUT ENABLE CLK 0 DATA IN Each rising edge on the CLK input increments the internal address counter if both CE is Low and OE/RESET is High. 43 OE/ RESET 20 DATA IN 13 19 DATA OUT 18 OUTPUT ENABLE When Low, this input holds the address counter reset and the DATA output is in a high-impedance state. This is a bidirectional open-drain pin that is held Low while the PROM is reset. Polarity is NOT programmable. 15 DATA IN When CE is High, this pin puts the device into standby mode and resets the address counter. The DATA output pin is in a high-impedance state, and the device is in low-power standby mode. 15 D1 D2 D3 D4 D5 D6 D7 CE 44-pin DS125 (v1.0) December 16, 2003 Advance Product Specification 42 27 9 25 14 19 www.xilinx.com 1-800-255-7778 13 R QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM Table 14: Pin Names and Descriptions (pins not listed are “no connect”) (Continued) Pin Number Pin Name Boundary Scan Order Function Pin Description VQFP CF 22 DATA OUT 10 21 OUTPUT ENABLE Allows JTAG CONFIG instruction to initiate FPGA configuration without powering down FPGA. This is an open-drain output that is pulsed Low by the JTAG CONFIG command. 13 DATA OUT 21 14 OUTPUT ENABLE Chip Enable Output (CEO) is connected to the CE input of the next PROM in the chain. This output is Low when CE is Low and OE/RESET input is High, AND the internal address counter has been incremented beyond its Terminal Count (TC) value. CEO returns to High when CEO 44-pin OE/RESET goes Low or CE goes High. GND GND is the ground connection. 6, 18, 28, 41 TMS TEST MODE SELECT The state of TMS on the rising edge of TCK determines the state transitions at the Test Access Port (TAP) controller. TMS has an internal 50 Kohm resistive pull-up on it to provide a logic "1" to the device if the pin is not driven. 5 TCK TEST CLOCK This pin is the JTAG test clock. It sequences the TAP controller and all the JTAG test and programming electronics. 7 TDI TEST DATA IN This pin is the serial input to all JTAG instruction and data registers. TDI has an internal 50 Kohm resistive pull-up on it to provide a logic "1" to the system if the pin is not driven. 3 TDO TEST DATA OUT This pin is the serial output for all JTAG instruction and data registers. TDO has an internal 50 Kohm resistive pull-up on it to provide a logic "1" to the system if the pin is not driven. 31 VCCINT Positive 3.3V supply voltage for internal logic and input buffers. 17, 35, 38 VCCO Positive 3.3V or 2.5V supply voltage connected to the output voltage drivers. 8, 16, 26, 36 14 www.xilinx.com 1-800-255-7778 DS125 (v1.0) December 16, 2003 Advance Product Specification R QPro XQ18V04 Military 4Mbit ISP Configuration Flash PROM Package Pin Diagrams PROM Package Pinout Compatibility VQ44 XQ18V04 XQ17V16 5 TMS N/C 7 TCK N/C 3 TDI N/C 31 TDO N/C 10 CF N/C 24 N/C BUSY 37 N/C GND 35 VCCINT VPP 8, 16, 26, 36 VCCO1 VCC 44 43 42 41 40 39 38 37 36 35 34 NC CLK D2 GND D0 NC VCCINT* NC VCCO VCCINT* NC Table 15: PROM-to-PROM Pinout Compatibility for the VQFP44 Package 1 2 3 4 5 6 7 8 9 10 11 NC NC TDO NC D1 GND D3 VCCO D5 NC NC 33 32 31 30 29 28 27 26 25 24 23 VQ44 Top View 12 13 14 15 16 17 18 19 20 21 22 NC NC TDI NC TMS GND TCK VCCO D4 CF NC NC OE/RESET D6 CE VCCO VCCINT* GND D7 NC CEO NC 1. The XQ18V04 supports 2.5-3.3V VCCO operation. The XQ17V16 only supports 3.3V. *See pin descriptions. DS082_13_102303 Figure 10: Package Pinout for the XQ18V04VQ44 Ordering Information XQ18V04 VQ44 N Device Number Manufacturing Grade Package Type Device Ordering Options Device Type XQ18V04 Package VQ44 Grade 44-pin Plastic Thin Quad Flat Package N Military Plastic TJ = –55° C to +125° C Revision History The following table shows the revision history for this document. Date Version 12/16/03 1.0 DS125 (v1.0) December 16, 2003 Advance Product Specification Revision First publication of this early access specification. www.xilinx.com 1-800-255-7778 15