ETC CANTUS

Preliminary Datasheet
CANTUS
Ver 2.04
Aug 18, 2009
Advanced Digital Chips, Inc.
CANTUS
Ver 2.04
History
Ver 1.1
April 17, 2009
Ver 1.7
June 30, 2009
1st version released
Add Electrical Characteristics
Fixed Name rule (signal name, register name, bit name)
Ver 1.8
July 1, 2009
Add Coprocessor
Ver 1.81
July 3, 2009
Change Clocks and Power Management
Ver 1.82
July 6, 2009
Modified typographic error
Ver 1.83
July 7, 2009
Modified TWI
Ver 1.84
July 8, 2009
Modified typographic error
Ver 1.85
July 14, 2009
Ver 1.86
July 15, 2009
Ver 1.87
July 15, 2009
Ver 1.88
July 15, 2009
Ver 1.89
July 16, 2009
Change GPIO
Added explanation of interrupt nesting
Modified Peri title name
Modified Voice Codec Block Diagram
Added Picture of External SRAM Memory
Modified DMA
Modified External SRAM
Modified font
Modified NOR Flash
Ver 1.90
July 17, 2009
Modified Figure of
Ver 1.91
July 17, 2009
Added KeyScan Data 2 Register
Ver 1.92
July 20, 2009
Modified CANTUS Block Diagram
Ver 1.93
July 20, 2009
Added Voice Codec ADC/DAC Signal Level
Ver 1.94
July 21, 2009
Modified IINTMOD Register of Interrupt Controller
1-2
“PCLK Clock Gating”
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Ver 2.04
CANTUS
Ver 1.95
July 22, 2009
Modified KSD1 Register of Keyscan
Ver 1.96
July 23, 2009
Modified typographic error
Ver 1.97
July 24, 2009
Modified I2S Clock Tree
Ver 1.98
July 24, 2009
Modified RTC Control Register
Ver 1.99
Aug 7, 2009
Modified ISP
Ver 2.00
Aug 10, 2009
Modified RTC
Ver 2.01
Aug 12, 2009
Modified Status Command and AAI Programming Command of ISP
Ver 2.02
Aug 14, 2009
Modified Picture of External SRAM Memory
Ver 2.03
Aug 18, 2009
Register
Modified Receive FIFO Trigger Level bit in UART Channel FIFO Control
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1-3
CANTUS
Ver 2.04
CONTENTS
1 Descriptions and Features .................................................................................................... 10
1.1 General Description ..................................................................................................... 10
1.2 Features ...................................................................................................................... 10
2 Block Diagram & Pin Descriptions ....................................................................................... 12
2.1 Block Diagram ............................................................................................................. 12
2.2 Pin Configurations ....................................................................................................... 13
Pinout ........................................................................................................................... 13
Pin Definitions ............................................................................................................. 14
Pin Descriptions .......................................................................................................... 19
3 Memory Architecture and Boot mode .................................................................................. 21
3.1 Memory Map ............................................................................................................... 21
3.2 Embedded Memories .................................................................................................. 21
Internal NOR Flash...................................................................................................... 21
Internal SRAM ............................................................................................................. 21
3.3 Memory Mapped I/O .................................................................................................... 22
3.4 Boot Configuration ....................................................................................................... 23
NAND Flash Type ....................................................................................................... 23
External SRAM Data Bus Type .................................................................................. 23
ISP (In System Programming) mode and Debugger mode ....................................... 23
4 Clocks and Power Management ............................................................................................ 24
4.1 Power.......................................................................................................................... 24
Power Pins .................................................................................................................. 25
Power Consumption .................................................................................................... 26
Voltage Regulators ..................................................................................................... 26
4.2 Reset .......................................................................................................................... 27
Power On Reset .......................................................................................................... 27
Power On Start Time .................................................................................................. 28
Software Reset ............................................................................................................ 29
System Reset .............................................................................................................. 29
4.3 Clocks ......................................................................................................................... 30
MOSC Clock and ROSC Clock .................................................................................... 31
PLL Clock .................................................................................................................... 32
MAIN Clock and HCLK Clock .................................................................................... 33
HCLK Clock and PCLK Clock Gating......................................................................... 34
USB Device Clock ....................................................................................................... 36
4.4 Power Management Controller .................................................................................... 37
Normal Run Mode ....................................................................................................... 38
Idle Mode ..................................................................................................................... 39
Deep Idle Mode ........................................................................................................... 39
Sleep Mode .................................................................................................................. 40
4.5 Power Management Control Registers ........................................................................ 41
5 Internal NOR Flash and External SRAM Controller ............................................................. 46
5.1 Internal NOR Flash Memory ........................................................................................ 46
5.2 External SRAM Memory .............................................................................................. 49
5.3 Internal NOR Flash and External SRAM Control Registers .......................................... 51
6 Coprocessor ........................................................................................................................... 54
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CANTUS
6.1 Coprocessor Description ............................................................................................. 55
6.2 Coprocessor Control Registers .................................................................................... 56
7 Watchdog Timer .................................................................................................................... 61
7.1 Watchdog Timer Control Registers .............................................................................. 62
8 GPIO (General Purpose I/O) .................................................................................................. 63
8.1 Port Alternate Functions .............................................................................................. 63
8.2 Port Control ................................................................................................................. 65
8.3 Port Edge Detect ......................................................................................................... 66
8.4 GPIO Registers ........................................................................................................... 66
9 Interrupts ............................................................................................................................... 79
9.1 Interrupt Vector and Priority ......................................................................................... 80
9.2 External Interrupt (EIRQ0/EIRQ1) ................................................................................ 81
9.3 Internal Interrupt Mode ................................................................................................ 82
9.4 Interrupt Pending and Interrupt Pending Clear ............................................................. 82
9.5 Interrupt Enable ........................................................................................................... 82
9.6 Interrupt Mask Set/Clear Register ................................................................................ 82
9.7 Interrupt Control Registers ........................................................................................... 83
10 Timers ................................................................................................................................. 92
10.1 15-bit Pre-scaler with clock source selection ................................................................ 93
10.2 Timer/Counter ............................................................................................................. 94
10.3 Pulse Width Modulation (PWM) ................................................................................... 95
10.4 Capture ....................................................................................................................... 97
10.5 Output Compare Mode ................................................................................................ 99
10.6 Timer Control Registers ............................................................................................. 100
11 SPI (Serial Peripheral Interface) ..................................................................................... 103
11.1 SPI Registers Summery ............................................................................................ 104
11.2 SPI Pins .................................................................................................................... 105
11.3 SPI Operating Modes ................................................................................................ 105
11.4 SCK Phase and Polarity Control ................................................................................ 107
11.5 Data Transfer Timing ................................................................................................. 107
11.6 SPI Serial Clock Baud Rate ....................................................................................... 109
11.7 Open-Drain Output for Wired-OR............................................................................... 109
11.8 Transfer Size and Direction ....................................................................................... 109
11.9 Write Collision ........................................................................................................... 109
11.10
MODE Fault ........................................................................................................ 109
11.11
Interrupt .............................................................................................................. 110
11.12
SPI Control Registers ......................................................................................... 111
12 TWI (Two Wired Interface) ............................................................................................. 114
12.1 DATA TRANSFER FORMAT ...................................................................................... 115
12.2 START AND STOP CONDITIONS ............................................................................. 115
12.3 ACK SIGNAL TRANSMISSION ................................................................................. 116
12.4 READ-WRITE OPERATION ...................................................................................... 116
12.5 BUS ARBITRATION PROCEDURES ......................................................................... 117
12.6 ABORT CONDITIONS ............................................................................................... 118
12.7 Operational Flow Diagrams ....................................................................................... 118
12.8 TWI Control Registers ............................................................................................... 123
13 UART................................................................................................................................. 127
13.1 UART Registers Summary......................................................................................... 128
13.2 Serial Data Format .................................................................................................... 129
13.3 UART Baud Rate ....................................................................................................... 131
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CANTUS
Ver 2.04
13.4 UART Control Registers ............................................................................................ 132
14 DMA (Direct Memory Access) ......................................................................................... 137
14.1 DMA Operation .......................................................................................................... 138
14.2 DMA Descriptor Table ................................................................................................ 139
14.3 Control Flag of Descriptor .......................................................................................... 142
14.4 DMA Control Registers .............................................................................................. 143
15 NAND Flash Controller .................................................................................................... 148
15.1 NAND Flash Operation .............................................................................................. 149
15.2 ECC .......................................................................................................................... 151
15.3 NAND Flash Control Registers .................................................................................. 152
16 I2S ..................................................................................................................................... 159
16.1 Frequency Control ..................................................................................................... 160
16.2 Interface Format ........................................................................................................ 161
16.3 Data Format .............................................................................................................. 161
16.4 Transmit and Receive FIFO ....................................................................................... 162
16.5 Wave File Format ...................................................................................................... 163
16.6 I2S Control Registers ................................................................................................ 164
17 USB Device ....................................................................................................................... 168
17.1 USB Registers Summary ........................................................................................... 169
17.2 USB Control Registers .............................................................................................. 171
18 Keyscan............................................................................................................................. 180
18.1 Key Scan Matrix Circuit ............................................................................................. 181
18.2 Key Scan Mode and Interrupt .................................................................................... 181
18.3 Key Scan Control Registers ....................................................................................... 182
19 Real Timer Clock .............................................................................................................. 184
19.1 RTC Control Registers .............................................................................................. 185
20 14-bit Voice Codec .......................................................................................................... 188
20.1 Voice Codec Control Registers .................................................................................. 190
21 ISP (In System Programmer) ........................................................................................... 192
21.1 ISP Command Set ..................................................................................................... 193
21.2 Read Command ........................................................................................................ 194
21.3 Write Command ........................................................................................................ 195
21.4 Device ID Command ................................................................................................. 195
21.5 Status/Control Command........................................................................................... 196
21.6 AAI Programming Command ..................................................................................... 197
22 Electrical Characteristics ................................................................................................. 198
22.1 DC Electrical Characteristics ..................................................................................... 198
22.2 LDO100 Voltage Regulator Electrical Characteristics ................................................. 199
22.3 LDO50 Voltage Regulator Electrical Characteristics ................................................... 199
22.4 POR Electrical Characteristics ................................................................................... 199
22.5 MOSC Electrical Characteristics ................................................................................ 200
22.6 ROSC Electrical Characteristics ................................................................................ 200
22.7 PLL Electrical Characteristics .................................................................................... 201
22.8 Voice Codec Electrical Characteristics ....................................................................... 202
22.9 Internal Register Electrical Characteristics ................................................................. 203
23 Package Dimension .......................................................................................................... 204
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Ver 2.04
CANTUS
FIGURES
FIGURE 2-1 CANTUS BLOCK DIAGRAM ........................................................................................................ 12
FIGURE 2-2 CANTUS PINOUT DIAGRAM ....................................................................................................... 13
FIGURE 3-1 MEMORY MAP ............................................................................................................................. 21
FIGURE 4-1 POWER SCHEME ......................................................................................................................... 24
FIGURE 4-2 POWER SUPPLY SCHEME ............................................................................................................ 26
FIGURE 4-3 RESET SOURCE........................................................................................................................... 27
FIGURE 4-4 POR RESET CONTROL ............................................................................................................... 28
FIGURE 4-5 POWER-UP RESET ...................................................................................................................... 28
FIGURE 4-6 CANTUS CLOCK TREE .............................................................................................................. 30
FIGURE 4-7 MOSC BLOCK DIAGRAM ............................................................................................................ 31
FIGURE 4-8 TYPICAL CRYSTAL CONNECTION FOR MOSC ............................................................................ 31
FIGURE 4-9 PLL BLOCK DIAGRAM ................................................................................................................. 32
FIGURE 4-10 MAIN CLOCK AND HCLK CLOCK ............................................................................................. 33
FIGURE 4-11 HCLK CLOCK GATING .............................................................................................................. 34
FIGURE 4-12 PCLK CLOCK GATING .............................................................................................................. 35
FIGURE 4-13 USB DEVICE CLOCKS............................................................................................................... 36
FIGURE 4-14 POWER MODE STATE DIAGRAM ............................................................................................... 37
FIGURE 4-15 SLEEP MODE STATE ................................................................................................................. 40
FIGURE 5-1 NOR FLASH TIMING DIAGRAM.................................................................................................... 47
FIGURE 5-2 EXTERNAL 8-BIT SRAM MEMORY TIMING DIAGRAM ................................................................. 49
FIGURE 5-3 CONNECTION 8-BIT SRAM MEMORY ......................................................................................... 49
FIGURE 5-4 EXTERNAL 16-BIT SRAM MEMORY TIMING DIAGRAM ............................................................... 50
FIGURE 5-5 CONNECTION 16-BIT SRAM MEMORY ....................................................................................... 50
FIGURE 8-1 GPIO BLOCK DIAGRAM .............................................................................................................. 63
FIGURE 9-1 EXTERNAL INTERRUPT MODE ..................................................................................................... 81
FIGURE 10-1 PRE-SCALER BLOCK DIAGRAM ................................................................................................. 93
FIGURE 10-2 TIMER OPERATION .................................................................................................................... 94
FIGURE 10-3 PWM OPERATION ..................................................................................................................... 96
FIGURE 10-4 CAPTURE MODE OPERATION.................................................................................................... 97
FIGURE 10-5 TIMING DIAGRAM OF OUTPUT COMPARE OPERATION ............................................................. 99
FIGURE 11-1 SPI BLOCK DIAGRAM .............................................................................................................. 104
FIGURE 11-2 SCK PHASE AND POLARITY.................................................................................................... 107
FIGURE 11-3 TRANSFER TIMING WHEN CPHA = „0‟ .................................................................................... 108
FIGURE 11-4 TRANSFER TIMING WHEN CPHA = „1‟ .................................................................................... 108
FIGURE 11-5 1-BYTE TRANSFER VS. STATUS AND INTERRUPT ................................................................... 110
FIGURE 11-6 N-BYTES TRANSFER VS. STATUS AND INTERRUPT................................................................. 110
FIGURE 12-1 TWI BLOCK DIAGRAM ............................................................................................................. 114
FIGURE 12-2 TWI-BUS INTERFACE DATA FORMAT ..................................................................................... 115
FIGURE 12-3 DATA TRANSFER ON THE TWI-BUS........................................................................................ 115
FIGURE 12-4 ACKNOWLEDGEMENT OF TWI................................................................................................. 116
FIGURE 12-5 BUS ARBITRATION 1 OF TWI ................................................................................................... 117
FIGURE 12-6 BUS ARBITRATION 2 ................................................................................................................ 117
FIGURE 12-7 TWI INITIALIZATION FLOW CHAR ............................................................................................ 118
FIGURE 12-8 MASTER TRANSMIT FLOW CHAR ............................................................................................ 119
FIGURE 12-9 MASTER RECEIVE FLOW CHAR .............................................................................................. 120
FIGURE 12-10 SLAVE MODE FLOW CHART (POLLING) ................................................................................ 121
FIGURE 12-11 SLAVE MODE FLOW CHART (INTERRUPT) ............................................................................ 122
FIGURE 13-1 UART BLOCK DIAGRAM ......................................................................................................... 127
FIGURE 13-2 UART LCR REGISTER SETTING AND SERIAL DATA FORMAT ............................................... 130
FIGURE 14-1 STRUCTURE OF DMA CONTROLLER ...................................................................................... 137
FIGURE 14-2 STRUCTURE OF DMA DESCRIPTOR ....................................................................................... 139
FIGURE 14-3 EXAMPLE OF DMA DESCRIPTOR FLOW .................................................................................. 140
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CANTUS
Ver 2.04
FIGURE 14-4 DMA DATA SWAP MODE......................................................................................................... 144
FIGURE 15-1 NAND FLASH CONTROLLER BLOCK DIAGRAM ...................................................................... 148
FIGURE 15-2 READ/WRITE TIMING DIAGRAM OF NAND FLASH MEMORY ................................................. 149
FIGURE 15-3 TRANSMISSION THROUGH BUFFER OF NAND FLASH CONTROLLER ..................................... 150
FIGURE 16-1 I2S BLOCK DIAGRAM .............................................................................................................. 159
FIGURE 16-2 I2S PRE-SCALER .................................................................................................................... 160
FIGURE 16-3 I2S INTERFACE FORMAT ......................................................................................................... 161
FIGURE 16-4 I2S DATA SWAP MODE............................................................................................................ 161
FIGURE 18-1 KEY SCAN BLOCK DIAGRAM ................................................................................................... 180
FIGURE 18-2 4 X 4 KEY MATRIX ................................................................................................................... 181
FIGURE 18-3 KEY SCAN TIME DIAGRAM ...................................................................................................... 181
FIGURE 20-1 VOICE CODEC BLOCK DIAGRAM ............................................................................................. 188
FIGURE 20-2 ADC/DAC SIGNAL LEVEL ...................................................................................................... 189
FIGURE 21-1 SPI MODES SUPPORTED ........................................................................................................ 192
FIGURE 21-2 READ COMMAND FLOW CHART............................................................................................... 194
FIGURE 21-3 WRITE COMMAND FLOW CHART ............................................................................................. 195
FIGURE 21-4 DEVICE ID COMMAND FLOW CHART ....................................................................................... 195
FIGURE 21-5 STATUS/CONTROL COMMAND FLOW CHART .......................................................................... 196
FIGURE 21-6 AAI PROGRAMMING COMMAND FLOW CHART........................................................................ 197
FIGURE 23-1 PACKAGE DIMENSION ............................................................................................................. 204
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CANTUS
TABLES
TABLE 2-1 CANTUS PIN DEFINITIONS .......................................................................................................... 14
TABLE 3-1 CANTUS PERIPHERAL MEMORY MAP ......................................................................................... 22
TABLE 4-1 POWER MODE ............................................................................................................................... 38
TABLE 5-1 NOR FLASH MEMORY (CANTUS128) ........................................................................................ 46
TABLE 5-2 NOR FLASH MEMORY (CANTUS512) ........................................................................................ 46
TABLE 5-3 NOR FLASH COMMAND DEFINITIONS........................................................................................... 48
TABLE 6-1 REAL MEMORY MAP IN NOR FLASH BOOT MODE......................................................................... 54
TABLE 6-2 COPROCESSOR REGISTER DESCRIPTION .................................................................................... 55
TABLE 8-1 PORT ALTERNATE FUNCTIONS ..................................................................................................... 63
TABLE 8-2 INTERNAL PULL-UP RESISTANCE CHARACTERISTICS .................................................................. 65
TABLE 9-1 INTERRUPT VECTOR & PRIORITY .................................................................................................. 80
TABLE 11-1 SPI PIN FUNCTIONS.................................................................................................................. 105
TABLE 13-1 UART REGISTER SUMMARY .................................................................................................... 128
TABLE 13-2 UART BAUD RATE.................................................................................................................... 131
TABLE 13-3 UART INTERRUPT CONTROL FUNCTION .................................................................................. 133
TABLE 14-1 DMA DESCRIPTOR SUMMARY .................................................................................................. 139
TABLE 16-1 I2S SAMPLING FREQUENCY(LRCK) AND MCLK CLOCK ........................................................ 160
TABLE 16-2 I2S SAMPLING FREQUENCY AND SERIAL BIT CLOCK ................................................................. 160
TABLE 16-3 WAVE FILE FORMAT HEADER .................................................................................................... 163
TABLE 17-1. ENDPOINT LIST ........................................................................................................................ 168
TABLE 17-2. USB CORE REGISTER LIST ..................................................................................................... 169
TABLE 21-1 ISP COMMAND SET .................................................................................................................. 193
TABLE 21-2 ISP STATUS/CONTROL REGISTER ........................................................................................... 196
TABLE 22-1 DC ELECTRICAL CHARACTERISTICS ........................................................................................ 198
TABLE 22-2 LDO100 ELECTRICAL CHARACTERISTICS ............................................................................... 199
TABLE 22-3 LDO50 ELECTRICAL CHARACTERISTICS ................................................................................. 199
TABLE 22-4 POR ELECTRICAL CHARACTERISTICS ..................................................................................... 199
TABLE 22-5 MOSC ELECTRICAL CHARACTERISTICS .................................................................................. 200
TABLE 22-6 ROSC ELECTRICAL CHARACTERISTICS................................................................................... 200
TABLE 22-7 PLL ELECTRICAL CHARACTERISTICS ....................................................................................... 201
TABLE 22-8 VOICE CODEC ELECTRICAL CHARACTERISTICS ....................................................................... 202
TABLE 22-9 INTERNAL RESISTANCE ELECTRICAL CHARACTERISTICS ........................................................ 203
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CANTUS
Ver 2.04
1 DESCRIPTIONS AND FEATURES
1.1 General Description
CANTUS is a high-performance 32-bit microcontroller that can operate at up to 92MHz, with
built-in NOR Flash Memory. The built-in NOR Flash Memory is 512KB (or 128KB) size, including
80KB SRAM.
CPU has an independent bus to access program memory and data memory (Harvard structure)
and a 5-stage pipeline EISC structure for very fast command processing.
Built-in NOR Flash Memory is available for both program code and data usage, to which easy-todownload JTAG Programming and ISP (In-System Programming) modes are applied.
In addition, CANTUS provides Idle mode, Deep Idle mode and Sleep mode for low power
application.
1.2 Features
▫ High-performance, Low-power 32-bit EISC Microprocessor
▫ 32-bit EISC Architecture
- AE32000C
- Up to 96MIPS Throughput at 96MHz
- 2 Way Set Associative cache with I-Cache(8KB) and D-Cache(4KB)
▫ Program and Data Memories
- 128KBytes , 512KBytes of Re-programmable NOR Flash
Endurance: 100,000 Erase Cycles
JTAG Programming
ISP (In System Programming)
- 80KBytes Internal SRAM
- External Static Memory Interface with ALE
▫ Peripherals
- 32-bit Watchdog Timer
- 2 External Interrupts
- 8 Channel 32-bit Timer/Counter with 15-bit Pre-scaler, Capture mode, PWM mode, and
Output Compare Mode
- 8 Channel UART with 16Bytes FIFO, Functionally compatible with the 16550
- Master/Slave SPI with 8Bytes FIFO
- Two Wire Interface
- Direct Memory Access Controller(DMAC)
- NAND Flash Controller with 4bit ECC
- I2S with ADPCM
- USB 1.1 Full Speed Device
- 53 Port In/Out
- 32.768KHz crystal oscillator for RTC
- 2MHz ~ 15MHz crystal oscillator
- Power Controller
- JTAG Debugger
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CANTUS
▫ Special Features
- Embedded two 1.8v Voltage Regulators (LDOs)
- Power On Reset
- On-chip PLL
 The PLL generates the clock to operate the overall device (including USB device).
- 14-bit Voice Codec with 4Ch Input
- Power Mode: Normal, Idle, Deep Idle and Sleep mode
- Woken by PWK pin or RTC interrupt from Deep Idle and Sleep mode
▫ Operating Voltage Range
- Core: 1.8V
- I/O: 3.3V
▫ Operating Frequency
- Up to 96MHz
▫ Package
- 100-pin TQFP Package
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CANTUS
Ver 2.04
2 BLOCK DIAGRAM & PIN DESCRIPTIONS
2.1 Block Diagram
Processor
Debugger
AE32000C
(I- 2way 8KB
D- 2way 4KB)
I-Port
D-Port
128KB,
512KB
NOR
FLASH
JTAG
SRAM Ctrl
Bus
Debugger
(ALE)
ISP
NAND Ctrl
AHB
1:1
1:2
Ch.1
ISRAM Ctrl
Ch. 0
1.8V
LDO
3.3V
100mA
Interrupt
Ctrl
Timer 8ch.
Watchdog
Timer
SPI
TWI
PLL
MOSC
(40M~96MHz)
APB
2MHz~15MHz
PMU
1.8V
LDO
3.3V
(50mA)
32.768KHz
GPIO 53
80KB SRAM
DMA Ctrl
UART 8ch.
Key Scan
4x4
RTC
ROSC
ADPCM
Low Power Domain
I2S
USB PHY
Voice
Codec
Analog
Mux
1.1
Codec Ctrl
USB Dev
4
Figure 2-1 CANTUS Block Diagram
12
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33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
RX3/SDA/P4.7
EXTCLK/TM0/CAP0/SD1/P5.0
TM1/CAP1/SD0/P5.1
TM2/CAP2/LRCK/P5.2
GND
TM3/CAP3/SCLK/P5.3
TM4/CAP4/MCLK/P5.4
TM5/CAP5/A16/P5.5
TM6/CAP6/A17/P5.6
TM7/CAP7/A18/P5.7
VDD33
GND
PVDD18
PWK
PDN
PVDD33
GND
PVDD18
30
ISP_CLK/TX2/SCK/SDCLK/P4.4
32
29
ISP_OUT/RX1/MISO/SD2/P4.3
TX3/SCL/P4.6
28
ISP_IN/TX1/MOSI/SD3/P4.2
31
27
RX0/SDI/P4.1
RX2/SDCMD/P4.5
26
TX0/SDO/P4.0
nTEST
1
75
GND
TX4/KO0/AD8/P1.0
2
74
nRESET
RX4/KI0/AD9/P1.1
3
73
P3.7/NDFL_nBUSY/nNMI
TX5/KO1/AD10/P1.2
4
72
P3.6/NDFL_nRE
RX5/KI1/AD11/P1.3
5
71
P3.5/NDFL_nCS
TX6/KO2/AD12/P1.4
6
70
P3.4/NDFL_CLE
RX6/KI2/AD13/P1.5
7
69
P3.3/NDFL_ALE
TX7/KO3/AD14/P1.6
8
68
P3.2/NDFL_nWE
RX7/KI3/AD15/P1.7
9
67
P3.1/nBE1/EIRQ1
VDD33
10
66
P3.0/nWAIT/EIRQ0
GND
11
65
VDDIN100
DP
12
64
VDDOUT100
DM
13
63
GND
AVDD33
14
62
AVDD18
AVSS33
15
61
AVSS18
VGA(AIN0)
16
60
VDD33
VOA
17
59
VDD18
AOUT
18
58
XOUT
VREF
19
57
XIN
AIN1
20
56
GND
AIN2
21
55
GND
AIN3
22
54
VDDOUT50
POREN/P6.4
23
53
VDDIN50
GND
24
52
RTC_XOUT
VDD18
25
51
RTC_XIN
P6.3/TDI
P6.2/TMS
P6.1/TCK
P6.0/nTRST
P2.7/SPI_nSS/SRAM_nCS3
P2.6/SRAM_nCS2/ISP_nCS
P2.5/SRAM_nCS1
P2.4/SRAM_nCS0
VDD33
GND
P2.3/SRAM_nWE
P2.2/SRAM_nRE
P2.1/SRAM_ALE1
P2.0/SRAM_ALE0
P0.7/AD7/nJTAGSEL
P0.6/AD6/nOSISEL
P0.5/AD5/MEMSIZ
P0.4/AD4/nISPSEL
VDD18
GND
P0.3/AD3/NFSIZ1
P0.2/AD2/NFSIZ0
P0.1/AD1/BOOTSEL1
P0.0/AD0/BOOTSEL0
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
TDO
99
100
Ver 2.04
CANTUS
2.2 Pin Configurations
Pinout
Figure 2-2 CANTUS Pinout Diagram
CONFIDENTIAL
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CANTUS
Ver 2.04
Pin Definitions
Table 2-1 CANTUS Pin Definitions
No.
Pin Name
1
2
nTEST
P1.0
3
P1.1
4
P1.2
5
P1.3
6
P1.4
7
P1.5
8
P1.6
9
P1.7
10
11
12
13
14
15
16
17
18
19
VDD33
GND
DP
DM
AVDD33
AVSS33
VGA
(AIN0)
VOA
AOUT
VREF
20
21
22
AIN1
AIN2
AIN3
14
Description.
Test mode select
P1.0 – General purpose I/O port
TX4 – UART TX[4]
KO0 – Key Scan output[0]
AD[8] – Address[8], Data[8]
P1.1 – General purpose I/O port
RX4 – UART RX[4]
KI0 – Key Scan input[0]
AD[9] – Address[9], Data[9]
P1.2 – General purpose I/O port
TX5 – UART TX[5]
KO1 – Key Scan output[1]
AD[10] – Address[10], Data[10]
P1.3 – General purpose I/O port
RX5 – UART RX[5]
KI1 – Key Scan input[1]
AD[11]/ – Address[11], Data[11]
P1.4 – General purpose I/O port
TX6 – UART TX[6]
KO2 – Key Scan output[2]
AD[12] – Address[12], Data[12]
P1.5 – General purpose I/O port
RX6 – UART RX[6]
KI2 – Key Scan input[2]
AD[13] – Address[13], Data[13]
P1.6 – General purpose I/O port
TX7 – UART TX[7]
KO3 – Key Scan output[3]
AD[14] – Address[14], Data[14]
P1.7 – General purpose I/O port
RX7 – UART RX[7]
KI3 – Key Scan input[3]
AD[15] – Address[15], Data[15]
3.3V (Main Power Domain)
Ground
USB D+
USB D3.3V (Voice Codec)
Ground (Voice Codec)
Voice Codec analog input0
Voice Codec gain control output
Voice Codec analog output
1.24V
This is the analog reference pin for the
Voice Codec.
Voice Codec analog input1
Voice Codec analog input2
Voice Codec analog input3
CONFIDENTIAL
Type
Output
Drive
Current
Pull-Up /
Pull-Down
I
B
4mA
Up / Schmitt
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
PWR
GND
B
B
PWR
GND
I
Analog
Analog
Analog
-
O
O
O
Analog
Analog
Analog
-
I
I
I
Analog
Analog
Analog
-
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
23
P6.4
24
25
26
GND
VDD18
P4.0
27
P4.1
28
P4.2
29
P4.3
30
P4.4
31
P4.5
32
P4.6
33
P4.7
34
P5.0
35
P5.1
36
P5.2
37
38
GND
P5.3
39
P5.4
P6.4 – General purpose I/O
POREN – POR enable signal
Ground
1.8V (Main Power Domain)
P4.0 – General purpose I/O
TX0 – UART TX[0]
SDO – I2S SDO
P4.1 – General purpose I/O
RX0 – UART RX[0]
SDI – I2S SDI
P4.2 – General purpose I/O
ISP_IN – ISP input data
TX1 – UART TX[1]
MOSI – SPI MOSI
SD3 – SDCD data[3]
P4.3 – General purpose I/O
ISP_OUT – ISP output data
RX1 – UART RX[1] data
MISO – SPI MISO
SD2 – SDCD data[2]
P4.4 – General purpose I/O
ISP_CLK – ISP clock
TX2 – UART TX[2]
SCK – SPI SCK
SDCLK – SDCD Clock
P4.5 – General purpose I/O
RX2 – UART RX[2]
SDCMD – SDCD Command
P4.6 – General purpose I/O
TX3 – UART TX[3]
SCL – TWI SCL
P4.7 – General purpose I/O
RX3 – UART RX[3]
SDA – TWI SDA
P5.0 – General purpose I/O
EXTCLK – External clock source for I2S
and Voice Codec
TM0 – PWM output[0]
CAP0 – Capture input[0]
SD1 – SDCD data[1]
P5.1 – General purpose I/O
TM1 – PWM output[1]
CAP1 – Capture input[1]
SD0 – SDCD data[0]
P5.2 – General purpose I/O
TM2 – PWM output[2]
CAP2 – Capture input[2]
LRCK – I2S LRCK
Ground
P5.3 – General purpose I/O
TM3 – PWM output[3]
CAP3 – Capture input[3]
SCLK – I2S SCLK
P5.4 – General purpose I/O
TM4 – PWM output[4]
CAP4 – Capture input[4]
Advanced Digital Chips, Inc.
CONFIDENTIAL
B
4mA
Up Controlled
GND
PWR
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
GND
B
4mA
Up Controlled
B
4mA
Up Controlled
15
CANTUS
16
Ver 2.04
40
P5.5
41
P5.6
42
P5.7
43
44
45
46
47
VDD33
GND
PVDD18
PWK
PDN
48
49
50
51
PVDD33
GND
PVDD18
RTC_XIN
52
53
54
55
56
57
RTC_XOU
T
VDD33
LOUT50
GND
GND
XIN
58
59
60
61
62
63
64
65
66
XOUT
VDD18
VDD33
AVSS18
AVDD18
GND
LOUT100
VDD33
P3.0
67
P3.1
68
P3.2
69
P3.3
70
P3.4
MCLK – I2S MCLK
P5.5 – General purpose I/O
TM5 – PWM output[5]
CAP5 – Capture output[5]
A16 – Address[16]
P5.6 – General purpose I/O
TM6 – PWM output[6]
CAP6 – Capture output[6]
A17 – Address[17]
P5.7 – General purpose I/O
TM7 – PWM output[7]
CAP7 – Capture input[7]
A18 – Address[18]
3.3V (Main Power Domain)
Ground
1.8V (Low Power Domain)
Wake up input signal
Power down signal.
3.3V of Main Power Domain control
signal
3.3V (Low Power Domain)
Ground
1.8V (Low Power Domain)
32.768KHz crystal input for Low Power
Domain.
32.768KHz crystal output for Low Power
Domain. If it isn‟t used, it has to be float.
3.3V (Low Power Domain)
LDO50 1.8V output
Ground
Ground
MOSC Xin is used for PLL clock source
and system clock source.
MOSC Xout
1.8V (Main Power Domain)
3.3V (Main Power Domain)
Ground (PLL)
1.8V (PLL)
Ground
LDO100 1.8V output
3.3V (Main Power Domain)
P3.0 – General purpose I/O
nWAIT – External wait input signal
EIRQ0 – External IRQ 0
P3.1 – General purpose I/O
nBE1 – SRAM byte enable 1
EIRQ1 – External IRQ1
P3.2 – General purpose I/O
NDFL_nWE – NAND Flash Write enable
signal
P3.3 – General purpose I/O
NDFL_ALE – NAND Flash address
latch enable signal
P3.4 – General purpose I/O
NDFL_CLE – NAND Flash command
latch enable signal
CONFIDENTIAL
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
PWR
GND
PWR
I
O
4mA
Down/Schmitt
-
PWR
GND
PWR
I
Analog
-
O
Analog
-
PWR
O
GND
GND
I
Analog
Analog
-
O
PWR
PWR
GND
PWR
GND
O
PWR
B
Analog
Analog
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
-
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
71
P3.5
72
P3.6
73
P3.7
74
75
76
nRESET
GND
P0.0
77
P0.1
78
P0.2
79
P0.3
80
81
82
GND
VDD18
P0.4
83
P0.5
84
P0.6
85
P0.7
86
P2.0
87
P2.1
88
P2.2
89
P2.3
90
91
92
GND
VDD33
P2.4
93
P2.5
94
P2.6
P3.5 – General purpose I/O
NDFL_nCS – NAND Flash chip select
signal
P3.6 – General purpose I/O
NDFL_nRE – NAND Flash read enable
signal
P3.7 – General purpose I/O
NDFL_nBUSY – NAND Flash busy
input signal
External reset signal. Active low reset
Ground
P0.0 – General purpose I/O port
AD0 – Address[0]/[8], Data[0]
BOOTSEL0 – Boot mode select[0]
P0.1 – General purpose I/O port
AD1 – Address[1]/[9], Data[1]
BOOTSEL1 – Boot mode select[1]
P0.2 – General purpose I/O port
AD2 – Address[2]/[10], Data[2]
NFSIZ0 – NAND Flash size[0]
P0.3 – General purpose I/O port
AD3 – Address[3]/[11], Data[3]
NFSIZ1 – NAND Flash size[1]
Ground
1.8V (Main Power Domain)
P0.4 – General purpose I/O port
AD4 – Address[4]/[12], Data[4]
nISPSEL – ISP mode select
P0.5 – General purpose I/O port
AD5 – Address[5]/[13], Data[5]
MEMSIZ – SRAM_nCS0 Memory Size
P0.6 – General purpose I/O port
AD6 – Address[6]/[14], Data[6]
nOSISEL – OSI debugger select
P0.7 – General purpose I/O port
AD7 – Address[7]/[15], Data[7]
nJTAGSEL – JTAG debugger select
P2.0 – General purpose I/O port
SRAM_ALE0 – SRAM address latch
enable [0]
P2.1 – General purpose I/O port
SRAM_ALE1 – SRAM address latch
enable [1]
P2.2 – General purpose I/O port
SRAM_nRE – SRAM read enable signal
P2.3 – General purpose I/O port
SRAM_nWE – SRAM write enable
signal
Ground
3.3V (Main Power Domain)
P2.4 – General purpose I/O port
SRAM_nCS0 – SRAM chip select[0]
P2.5 – General purpose I/O port
SRAM_nCS1 – SRAM chip select[1]
P2.6 – General purpose I/O port
SRAM_nCS2 – SRAM chip select[2]
Advanced Digital Chips, Inc.
CONFIDENTIAL
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
I
GND
B
4mA
Schmitt
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
GND
PWR
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
GND
PWR
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
17
CANTUS
Ver 2.04
95
P2.7
96
P6.0
97
P6.1
98
P6.2
99
P6.3
100
TDO
18
ISP_nCS –ISP chip select
P2.7 – General purpose I/O port
SPI_nSS – SPI chip enable
SRAM_nCS3 – SRAM chip select[3]
P6.0 – General purpose I/O port
nTRST – JTAG nTRST
P6.1 – General purpose I/O port
TCK – JTAG TCK
P6.2 – General purpose I/O port
TMS – JTAG TMS
P6.3 – General purpose I/O port
TDI – JTAG TDI
TDO – JTAG TDO
CONFIDENTIAL
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
B
4mA
Up Controlled
O
4mA
-
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
Pin Descriptions
VDD33
VDD18
PVDD33
PVDD18
GND
: 3.3V Supply voltage for Main Power Domain
: 1.8V Supply voltage for Main Power Domain
: 3.3V Supply voltage for Low Power Domain
: 1.8V Supply voltage for Low Power Domain
: Ground.
AVDD33
AVSS33
: 3.3V Supply voltage for Voice Codec
: Ground
AVDD18
AVSS18
: 1.8V Supply voltage for PLL
: Ground
nTEST: Chip test pin
Pin to decide device operation mode. For normal operation, this pin should be set to high level and
nothing should be connected to this pin. Low level is used for chip test.
nISPSEL: ISP mode select pin
Pin to select ISP (In System Programming) mode
nOSISEL: test pin
Pin to select OSI debug mode
nJTAGSEL: test pin
Pin to select JTAG debugmode
BOOTSEL[1:0]: test pin
Pin to select normal boot mode.
BOOTSEL1
1
1
0
0
BOOTSEL0
1
0
1
0
Boot Mode
NOR Flash booting
SRAM_nCS0 area booting
NAND Flash booting
Reserved
NFSIZ [1:0]: test pin
Pin to select NAND Flash type for NAND Flash booting, in NAND boot mode.
NFSIZ1
1
1
0
0
Advanced Digital Chips, Inc.
NFSIZ0
1
0
1
0
NAND Flash Type
5 Cycles Large NAND Flash Type
4 Cycles Large NAND Flash Type
4 Cycles Small NAND Flash Type
3 cycles Small NAND Flash Type
CONFIDENTIAL
19
CANTUS
Ver 2.04
MEMSIZ: test pin
Pin to select data bus size for memory during booting to the local memory SRAM_nCS0, in normal
boot mode
MEMSIZ
1
0
20
External Memory Bus Size
8bit Data bus
16bit Data bus
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
3 MEMORY ARCHITECTURE AND BOOT MODE
3.1 Memory Map
CANTUS has three types of memory maps as shown in Figure 3-1, as there are three types of boot
modes. Default boot mode is booting by internal NOR Flash. The other boot modes include booting
by external NAND Flash and booting by external memory.
6017_FFFFh
6010_0000h
6008_0000h
6000_0000h
SRAM_nCS3
Max 512KB
SRAM_nCS2
Max 512KB
SRAM_nCS1
Max 512KB
6017_FFFFh
6010_0000h
6008_0000h
6000_0000h
Reserved
4007_FFFFh
SRAM_nCS2
Max 512KB
SRAM_nCS1
Max 512KB
4000_0000h
0007_FFFFh
6010_0000h
6008_0000h
6000_0000h
0000_0000h
4000_0000h
Reserved
Internal SRAM
(80KB)
Reserved
SRAM_nCS0
Max 512KB
0000_0000h
NOR Flash Booting
SRAM_nCS1
Max 512KB
SRAM_nCS0
Max 512KB
Reserved
2007_FFFFh
NOR Flash
512KB
(128KB)
0007_FFFFh
NOR Flash
512KB
(128KB)
SRAM_nCS2
Max 512KB
Reserved
NOR Flash
512KB
(128KB)
2001_3FFFh
2000_0000h
SRAM_nCS3
Max 512KB
4007_FFFFh
4000_0000h
Reserved
Internal SRAM
(80KB)
Reserved
6017_FFFFh
Reserved
4007_FFFFh
SRAM_nCS0
Max 512KB
2001_3FFFh
2000_0000h
SRAM_nCS3
Max 512KB
External Memory Booting
2000_0000h
0001_3FFFh
0000_0000h
Reserved
Internal SRAM
(80KB)
NAND Flash Booting
Figure 3-1 Memory Map
3.2 Embedded Memories


512KB(or 128KB) NOR Flash
80KB SRAM
 Single Cycle Access at full speed.
Internal NOR Flash
CANTUS has built-in 512KB or 128KB NOR Flash Memory. During Flash boot mode, this memory
is accessible at 0x0000_0000. It is available for commands or data.
Internal SRAM
CANTUS has 80KB internal memory, which is available for commands or data. During NAND boot
mode, this memory is allocated to the address „0x0000_0000‟ but during other boot modes, it is
allocated to the address „0x2000_0000.‟
Advanced Digital Chips, Inc.
CONFIDENTIAL
21
CANTUS
Ver 2.04
3.3 Memory Mapped I/O
Addresses of the peripheral blocks of CANTUS are shown in the following table:
Base Address
AHB
0x8000_0000
APB
0x8002_0000
22
Table 3-1 CANTUS Peripheral Memory Map
Offset Address
Block
0x0000
Reserved
0x0400
Internal NOR Flash /
External SRAM Controller (with ALE)
0x0800
DMA
0x0C00
NAND Flash Controller
0x1000
Reserved
0x0000
GPIO (Port Alternate Functions)
0x0400
Power Management Unit
0x0800
Interrupt Controller
0x0C00
Watchdog Timer
0x1000
Timer
0x1400
UART Ch0~Ch3
0x1800
UART Ch4~Ch7
0x1C00
SPI
0x2000
TWI
0x2400
Voice Codec
0x2800
I2S (with ADPCM)
0x2C00
USB Device
0x3000
Key Scan
0x3400
GPIO (Port Control, Port Edge Detect)
0x3800
Real Timer Counter
0x3C00 ~
Reserved
0xFFFF
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
3.4 Boot Configuration
Booting always starts at 0x0000_0000. At the time of booting, the boot mode is decided by
BOOTSEL1 and BOOTSEL0 pins and at the same time the memory map is adjusted. Booting
always uses XIN, and memory is accessed with the default memory control.



Internal NOR Flash boot mode
 NOR Flash is allocated to the address „0x0000_0000.‟
External NAND Flash boot mode
 Internal SRAM is allocated to the address „0x0000_0000.‟
External SRAM boot mode
 Memory selected as external SRAM_CS0 is allocated to the address „0x0000_0000.‟
Boot mode is decided by the status values of BOOTSEL1 and BOOTSEL0 pins when the external
reset is released.
BOOTSEL1
1
1
0
0
BOOTSEL0
1
0
1
0
Boot Mode
NOR Flash boot mode
SRAM_nCS0 Area boot mode
NAND Flash boot mode
Reserved
NAND Flash Type
During NAND Flash boot mode, the size and type of NAND Flash can be decided. Boot mode by
NAND Flash type is decided by the level values of NFSIZ1 and NFSIZ0 pins.
NFSIZ1
1
1
0
0
NFSIZ0
1
0
1
0
NAND Flash Type
5 Cycles Large NAND Flash Type
4 Cycles Large NAND Flash Type
4 Cycles Small NAND Flash Type
3 Cycles Small NAND Flash Type
External SRAM Data Bus Type
During booting by the external memory of SRAM_nCS0 area, whether the data bus is 8-bit or 16bit is decided by MEMSIZ pin.
MEMSIZ
1
0
External Memory Bus Size
8bit Data Bus
16bit Data Bus
ISP (In System Programming) mode and Debugger mode
The following pins decide ISP, OSI Debugger or JTAG Debugger mode.
- nISPSEL : Booted to ISP mode, for low level.
- nOSISEL : Booted to OSI Debugger mode, for low level.
- nJTAGSEL: Booted to JTAG Debugger mode, for low level.
Advanced Digital Chips, Inc.
CONFIDENTIAL
23
CANTUS
Ver 2.04
4 CLOCKS AND POWER MANAGEMENT
4.1 Power
CANTUS has two separate power domains, each of which is divided into main power and low
power area. Figure 4-1 shows the separate power domains.
Main Power Domain should supply the voltage of 1.8V to internal devices and SRAM to operate
and 3.3V to internal Flash and I/O.
Low Power Domain should supply 1.8V to internal devices and 3.3V to I/O.
CANTUS
Low Power
3.3V
LDO
PMU
1.8V
1.8V
RTC
Wakeup Logic
Low Power Domain
Main Power
3.3V
1.8V
LDO
SRAM
Voice Codec
NOR Flash
PLL
USB PHY
1.8V
Main Power Domain
Figure 4-1 Power Scheme
In each domain, there is LDO to generate the 1.8V supply voltage and thus there is no need to
supply 1.8V from the outside.
24
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
Power Pins
In CANTUS, there is a variety of power pins and are two built-in voltage regulators (LDOs). The
internal voltage regulator allows configuring the system with 3.3V single supply.
Power pins are classified into the following types:

VDDIN100 pin: It powers the internal voltage regulator in Main Power Domain; voltage ragnes
from 3.0V to 3.6V, 3.3V nominal..

VDDOUT100 pin: It is the output of the internal 1.8V voltage regulator in Main Power Domain.

VDD33 pins: It powers the I/O lines of Main Power Domain; Ranges from 3.0V to 3.6V, 3.3V
nominal.

VDD18 pins: They power the logic of the device in Main Power Domain; voltage ranges from
1.65V to 1.95V, 1.8V typical. It can be connected to the VDDOUT100 pin with decoupling
capacitor. When these pins are connected to VDDOUT100 output, the system can be
configured with a single power source of 3.3V.

AVDD18 pin: It powers the PLL. When this pin is connected to VDDOUT100 output, the
system can be configured with a single power source of 3.3V.

AVDD33 pin: It powers the Voice Codec.

VDDIN50 pin: It powers the voltage regulator in Low Power Domain; voltage ranges from 3.0V
to 3.6V, 3.3V nominal.

VDDOUT50 pin: It is the output of the 1.8V voltage regulator in Low Power Domain.

PVDD33 pins: It power th I/O lines of Low Power Domain; Ranges from 3.0V to 3.6V, 3.3V
nominal.

PVDD18 pins: They power the logic in Low Power Domain; voltage ranges from 1.65V to
1.95V, 1.8V typical. It can be connected to the VDDOUT50 pin with decoupling capacitor.
When these pins are connected to VDDOUT50 output, the system can be configured with a
single power source of 3.3V.
Advanced Digital Chips, Inc.
CONFIDENTIAL
25
CANTUS
Ver 2.04
Main Power
3.3V
VDD33
AVDD33
VDDIN100
1.8V
VDDOUT100
1.8V
Main Power
Volatage
Regulator
OFF
VDD18
AVDD18
Low Power
3.3V
PVDD33
VDDIN50
Low Power
Voltage
Regulator
VDDOUT50
1.8V
1.8V
PVDD18
This Block is kept powered on in SLEEP MODE
NOTE: The External 3.3V power supplies must always be kept on
Figure 4-2 Power Supply scheme
Figure 4-2 illustrates a power supply scheme of a typical CANTUS. In this illustration, 3.3V power
is applied to Main Power Domain and also to Low Power Domain, in order to configure the system
with the single power source of 3.3V.
When the voltage regulator is not used, VDDIN100 and VDDIN50 should be connected to GND.
At this time, VDDOUT100 and VDDOUT50 pins should be open.
Power Consumption
CANTUS has a static power consumption of less than 500uA at 25℃ (typical).
The dynamic power consumption on VDD18 is less than 100mA at full speed.
Voltage Regulators
CANTUS has two internal voltage regulators (LDO).

26
Main Power Voltage Regulator
 It consumes 30uA static current in normal mode and supplies maximum 100mA current.
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
In SLEEP mode, it powers down and consumes only 1uA of static current.

Low Power Voltage Regulator
 It consumes 30uA static current and supplies 50mA current.
4.2 Reset
Reset controller consists of Power-On Reset, External Reset, Watchdog Timer Reset, PMU Reset
and Software Reset. When reset occurs, it is possible to identify the source of the reset through
RSTSTAT register.
NORFlash reset
ISP system reset
nRESET
External reset
POREN
/P6.4
1.8V
POR
POR reset
System reset
Startup
Counter
Boot reset
ISP processor reset
Processor reset
WDT_reset
PMU_reset
(HALT 0)
Software reset
Figure 4-3 Reset Source
Power On Reset
CATUS embeds a Power-On Reset circuit, which is supplied with 1.8V power and monitors 1.8V
power supply. During power-up process, the power-on reset circuit resets the entire system to
ensure safe booting.
The reset control has a startup counter in it, which operates as MOSC clock and generates the
following reset signals.



Processor reset: For CPU reset
System reset: Affects all peripheral controllers.
Flash reset: For NOR Flash reset
These reset signals are generated either by external input or software setting.
Advanced Digital Chips, Inc.
CONFIDENTIAL
27
CANTUS
Ver 2.04
P6PUS[4]
VDD33
POREN/
P6.4
VDD18
POR Reset
1.8V
POR
Figure 4-4 POR Reset Control
POREN/P6.4 pin makes it possible to determine the operation of internal POR. When POREN
pin is set to high level, the internal POR is available. POREN/P6.4 pin has pull-up resistance
connected inside. So, if there is no external connection, POR reset is activated.
Power On Start Time
When VDD18 is powered on, the POR circuit output is filtered with a start-up conter that operates
at main oscillator clock(MOSC). The purpose of this counter is to ensure that the main
oscillator(MSOC) is stable before start up the device.
POR Reset
MOSC
External nRESET
NOR Flash nReset
System nReset
Reset Filter time
16 cycles of Xin
flash reset 500ns
Flash Initial Time
20us
Startup counter
1024 cycles of Xin
Figure 4-5 Power-up Reset
When power supply is stabilized, POR is released. Then, after 17 cycles of MOSC clock, internal
NOR Flash reset is released and then again after 20us, system reset is released. Then, CPU starts
28
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
to read commands from the address „0x0000_0000.‟
Software Reset
By setting the register, you can generate reset signals. First set RSTWEN bit in PMCTRLEN
register to “1” and set RSTCTRL register, and then Software Reset signal is generated.
System Reset
System Reset is triggered in the following events:
1. Power On Reset
2. External Reset
3. Watchdog Timer Reset
4. Software Reset
In Deep Idle and Sleep mode, System Reset is triggered by the above events after Wake-up.
Advanced Digital Chips, Inc.
CONFIDENTIAL
29
CANTUS
Ver 2.04
4.3 Clocks
CANTUS has two external clock sources and one internal PLL. MOSC is supplied to Main Power
domain to be an input clock to PLL. ROSC is supplied to Low Power domain to be supplied to
PMU/RTC block. Figure 4-6 shows the internal clock structure.
The clock applied to XIN is supplied to PPL via MOSC, and operates within the range of 2MHz ~
15MHz.
RTC_XIN, supplied via ROSC to PMU and RTC blocks, operates at the frequency of 32.768KHz.
PLL is set to 48MHz or 96MHz when USB device is available, to supply 48MHz and 12MHz
clocks to the USB device. When USB device is not available, PLL may use any clock lower than
96MHz.
HCLK Clock
(Max.96MHz)
1/N
PLL
(40MHz~96MHz)
MAIN Clock
PLL Clock
XIN
2MHz~15MHz
MOSC
MOSC Clock
1/2
1/2
PCLK Clock
(Max.48MHz)
USB48 Clock
(48MHz)
1/4
IMCLK
EXTCLK(#34)
USB12 Clock
(12MHz)
Internal MCLK for I2S, Voice Codec
• 11.2896MHz → 44.1KHz for I2S
• 2.048MHz → 8KHz for Voice Codec
RTC_XIN
32.768KHz
ROSC
ROSC Clock
Figure 4-6 CANTUS Clock Tree
30
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
MOSC Clock and ROSC Clock
MOSC clock supplied to XIN is generated by 2MHz ~ 15MHz crystal oscillation.
MOSC clock is set to be controlled by CLKWEN bit in PMCTRLEN register, and its ON/OFF is
controlled by “Halt1.” In Deep Idle or Sleep mode in which MOSC clock is disabled, the clock can
be re-oscillated for wake-up by PWKpin or RTC interrupt.
When MOSC oscillation is disabled by “Halt 1,” CPU can get out of “Halt1” state only if PWK and
RTC interrupt has been set.
“HALT 1"
XIN
MOSC
MOSC Clock
XOUT
Figure 4-7 MOSC Block Diagram
GND
XIN
XOUT
VDD18
VDD33
1.8V
3.3V
Rfb
Rs
CL
CL
Figure 4-8 Typical Crystal Connection for MOSC
Figure 4-8 shows a typical external crystal circuit connection for MOSC. Rs resistance allows
reducing power consumption by crystal.
The external crystal circuit connection for ROSC is the same as shown in Figure 4-8.
Advanced Digital Chips, Inc.
CONFIDENTIAL
31
CANTUS
Ver 2.04
PLL Clock
Internal PLL has a built-in divider at the input and the output ends, so it has a high degree of
precision.
M
N
6
MOSC Clock
P
2
8
Divider
VCO
PLL
Divider
PLL Clock
(5MHz ~ 96MHz)
Figure 4-9 PLL Block Diagram
f PLL 
( N  2)  f OSC
( M  2)  2 p
Where: fOSC = 2 ~ 15MHz
M = Input Frequency Divider
N = VCO Frequency Divider
P = Output Frequency Divider
In order to use PLL, PLLCTRL register should be first set to be controllable through PLLWEN bit
in PMCTRLEN register. Then, a proper clock should be set by controlling PLLCTRL register, to
generate PLL clock. However, until MAIN clock is controlled through CLKCTRL register, MAIN
clock input becomes MOSC clock.
In a system that can operate at a speed of 15MHz or less, MOSC clock which is an external
crystal oscillation is used as MAIN clock without operating PLL, in order to reduce power
consumption.
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CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
MAIN Clock and HCLK Clock
HCLK clock is generated by dividing MAIN clock that has been selected as MOSC clock and PLL
clock. MAIN and HCLK clocks are decided in consideration of the system performance and power
consumption. Transfer from one clock to another does not cause glitch to occur nor affect the
system operation.
CLKCTRL
PRESEL
CLKCTRL
MAINSEL
CPU
Clock
Gating
CPUCLK
To CPU
HCLKl
Clock
Gating
HCLK
To AHB Bus
MOSC Clock
MAIN Clock
Main Clock
Prescaler
(/1,2,4,8,16,1024)
HCLK Clock
PLL Clock
CLKCTRL
PCLKSEL
1/2
PCLK Clock
PCLK
Clock
Gating
PCLK
To APB Bus
Figure 4-10 MAIN Clock and HCLK Clock
MAIN clock source selection is determined with MAINSEL bit in CLKCTRL register. Pre-scaler
N
divides MAIN clock to 2 . PRESEL bit in CLKCTRL register selects one of clocks divided by Prescaler.
When Pre-scaler changes setting to another clock, the clock change circuit operates to prevent a
glitch from occurring, so that it may take 1024 cycles of MAIN clock.
Advanced Digital Chips, Inc.
CONFIDENTIAL
33
CANTUS
Ver 2.04
HCLK Clock and PCLK Clock Gating
HCLK clock is the clock supplied to peripherals of AHB bus and CPU. It can be selected among /1,
/2, /4, /8, /16, /1024 cycles of MAIN clock.
PCLK clock is the clock supplied to peripherals of APB bus. It is either the same as HCLK clock or
selected as 1/2 cycle of MAIN clock. When PPL clock has been set so that HCLK clock is 48MHz
or lower, PCLK can be selected the same as HCLK clock.
HALTCTRL
HALT2
HCLK Clock
CPU clock
HCLKGATE
SDCLKEN
SDHC clock
HCLKGATE
NDFLCKEN
NAND CTRL clock
HCLKGATE
DMACKEN
DMA CTRL clock
HCLKGATE
ISRAMCKEN
Internal SRAM clock
HCLKGATE
SRAMCKEN
Internal NOR Flash /
External SRAM CTRL clock
HCLKGATE
ISPCKEN
ISP CTRL clock
HCLKGATE
AHBBUSCKEN
AHB Bus clock
Figure 4-11 HCLK Clock Gating
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CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
CLKCTRL
PCLKSEL
PCLKGATE
GPIOCKEN
HCLK Clock
1/2
PCLK Clock
GPIO clock
(Port Alternate Function)
PCLKGATE
PCLKGATE
RTCCKEN
SPICKEN
RTC clock
SPI clock
PCLKGATE
PCLKGATE
KEYCKEN
UARTCKEN
KeyScan clock
UART clock
PCLKGATE
PCLKGATE
USBCKEN
TIMECKEN
USB Device clock
TIMER clock
PCLKGATE
PCLKGATE
I2SCKEN
WDCKEN
I2S clock
Watchdog Timer clock
PCLKGATE
PCLKGATE
VOICECKEN
INTCKEN
Voice clock
Interrupt CTRL clock
PCLKGATE
GPIOCKEN
GPIO clock
(Port Control, Port Edge Detect)
PCLKGATE
TWICKEN
TWI CTRL clock
Figure 4-12 PCLK Clock Gating
HCLKGATE register and PCLKGATE register can control the clocks of peripheral controllers
individually.
After reset, clock is supplied to all peripheral controllers. For the clocks of the controllers not to
bused, the corresponding bits in HCLKGATE register and PCLKGATE register should be set to “0.”
As the peripheral controller clock is disabled the moment its bit is set to “0,” the bit should not be
set until the peripheral controller completes its last operation.
Advanced Digital Chips, Inc.
CONFIDENTIAL
35
CANTUS
Ver 2.04
USB Device Clock
USB device clock is supplied from MAIN clock. When MAIN clock is 96MHz, UCLKSEL bit of
CLKCTRL register should be set to “1” and when the clock is 48MHz, the bit should be set to “0.”
USB device requires three types of clocks. USB48M and USB12M can be controlled by
USB48EN and USB12EN bits of SCLKGATE register. To reduce power consumption when USB
device is not in use, USB Suspend Enable bit can be set. So, when it is confirmed that USB PHY
has entered Suspend mode, USB48, USB12, and USB device clock can be suspended.
CLKCTRL
MAINSEL
MOSC Clock
MAIN Clock
CLKCTRL
UCLKSEL
PLL Clock
SCLKGATE
USB48EN
1/2
USB48M Clock
SCLKGATE
USB12EN
1/4
USB12M Clock
Figure 4-13 USB Device Clocks
36
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
4.4 Power Management Controller
Power management controller dynamically controls power consumption in accordance with the
system requirements. Power management is achieved through controlling CPU, SRAM and each
peripheral controller clock.
CANTUS supports the following four power management modes:
- Normal Run Mode
- Idle Mode
- Deep Idle Mode
- Sleep Mode
Figure 4-14 illustrates the transition among power modes.
Power On Reset
Normal
Run
* CPU Clock ON (MAIN Clock = MOSC Clock)
* Peripherals Clock OFF
* PLL Power down
* Audio Codec Power down
* USB PHY Suspend mode
“Halt 0” Instruction
PWK Event
RTC Interrupt
Interrupt
Sleep
Halt 2 instruction
“Halt 1” Instruction
PWK Event
RTC Interrupt
Idle
* MOSC OFF
* LDO Power OFF
* Main Power OFF
Deep Idle
* CPU Clock OFF
* MOSC OFF
Figure 4-14 Power Mode State Diagram
Advanced Digital Chips, Inc.
CONFIDENTIAL
37
CANTUS
Power States
Normal Run
Mode
Idle Mode
(Halt 2)
Ver 2.04
Table 4-1 Power Mode
Clocks
Wake-Up event
Description
CPU Active
Peripherals inactive if disabled by the
peripherals clock gating register
CPU Clock ON
USB PHY, PLL, Flash Memory and
Voice Codec in power down mode if
disabled by the power down register
Slower clock selected
External Reset
CPU Clock
Watchdog Reset
“Halt 2” Instruction
OFF
Interrupt
Deep Idle Mode
(Halt 1)
MOSC OFF
Sleep Mode
(Halt 0)
Main LDO and
Main Power
OFF
RTC Interrupt
PWK Wake-up
RTC Interrupt
PWK Wake-up
“Halt 1” Instruction
MOSC OFF
All Clocks OFF except RTC Clock
“Halt 0” Instruction
MOSC OFF
All Clocks OFF except RTC Clock
Main Domain Power Down
Normal Run Mode
This is the state in which CPU is processing an instruction. Either all or some peripheral
controllers are working. Clocks for inactive peripherals have been disabled by HCLKGATE,
PCLKGATE and SCLKGATE register setting. In this mode, it is possible to reduce power
consumption by choosing slower frequency. It is possible to set CANTUS to operate by an external
clock without using PLL. In addition, when it is deemed that USB PHY, PLL and Voice Codec are
inactive, it is possible to power them down.
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CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
Idle Mode
Idle mode is enabled by “Halt 2” command. In this mode, CPU clock is disabled and thus CPU is
inactive. However, other peripheral controllers might be actively working. CANTUS can return to
Normal Run mode only when the interrupt controller is activated.
In order for CANTUS to exit from Idle mode, an interrupt should be generated by an active
peripheral controller or by an external interrupt.
CANTUS can exit from Idle mode upon one of the following events:




Power on reset
External reset
External interrupt or Internal peripheral interrupt
RTC interrupt
Deep Idle Mode
Deep Idle mode is enabled by “Halt 1” command. In this mode, MOSC is disabled and only ROSC
is enabled. In order for CANTUS to return to Normal Run mode from Deep Idle mode, MOSC clock
should be selected as MAIN clock and interrupt controller should be enabled.
In order to enhance power efficiency in Deep Idle mode, PLL, Voice Codec and USB PHY should
be set to power-down state.
CANTUS can exit from Deep Idle mode by the following condition. At this time, it activates PWK
and RTC Interrupt Service Routine and processes “Halt 1” command.
The PMU module can generate interrupts when the following conditions occur:


RTC match interrupt
Assertion of PWK pin (PWK event)
When the interrupt controller is re-activated, CANTUS wakes up processors upon receiving the
above interrupt. The processors are reactivated before CANTUS enters into Deep Idle mode.
In order for CANTUS to exit from Deep Idle mode, PWK or RTC interrupt should be pre-set by
program before it enters into Deep Idle mode.
Advanced Digital Chips, Inc.
CONFIDENTIAL
39
CANTUS
Ver 2.04
Sleep Mode
Sleep mode is enabled with “HALT 0” command. In this mode, Main Power Voltage Regulator
(LDO100) is set to shut off 1.8V supply from the main power domain. MOSC clock is also disabled.
In addition, PDN pin should be connected to 3.3V control end in the main power domain, to shut off
3.3V power input to the main power domain. If the system environment does not allow shutting off
3.3V power to the main power domain, leakage current is generated, resulting in more power
consumption than in Deep Idle mode.
VDDIN
3.3V
Always alive
LDO50
Low Power
Voltage
Regulator
RTC
VDDOUT
1.8V
PMU
PWK
PDN
LDO power off
VDDIN
3.3V
Always alive
LDO100
Main Power
Voltage
Regulator
1.8V OFF
VDDOUT
1.8V
CPU, Peripherals, PLL,
SRAM80KB, POR, Voice
Codec, NOR Flash, USB
PHY
Figure 4-15 Sleep Mode State
CANTUS can exit from Sleep mode by the following event. At this time, as these events are the
same as Power-On Reset state, it enters into Reset state.


40
RTC match interrupt
Assertion of PWK pin (PWK event)
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
4.5 Power Management Control Registers
PLL Control Register (PLLCTRL)
Address: 0x8002_0400
Bit
R/W
Description
Default Value
31 : 17
R
Reserved
16
R/W
PLL Power Control
1
0 : PLL ON 1 : PLL OFF
15 : 8
R/W
N : VCO frequency divider value 8bit
0Fh
7:6
R/W
P : Output frequency scalar value 2bit
0
5:0
R/W
M : Reference frequency input divider 6bit
0
*** This register is accessed by setting the PLLWEN bit in the PMCTRLEN register to 1.
f PLL 
( N  2)  f OSC
( M  2)  2 p
Clock Control Register (CLKCTRL)
Address: 0x8002_0404
Bit
R/W
Description
Default Value
31 : 7
R
Reserved
6:4
R/W
PRESEL : MAIN Clock Pre-scaler for HCLK Clock
0
000 : MAIN Clock
001 : MAIN Clock / 2
010 : MAIN Clock / 4
011 : MAIN Clock / 8
100 : MAIN Clock / 16
101 : MAIN Clock / 1024
11x : MAIN Clock
3
R/W
IMCLKSEL : Clock Source Selection bit for I2S and
0
Voice Codec
0 : MOSC Clock
1 : EXTCLK(#34)
2
R/W
UCLKSEL : USB Clock Source Selection bit
0
0 : MAIN Clock / 2 (if MAIN Clock is 96MHz)
1 : MAIN Clock
(if MAIN Clock is 48MHz)
1
R/W
PCLKSEL : PCLK Clock Source Selection bit
0
0 : HCLK Clock / 2
1 : HCLK Clock
0
R/W
MAINSEL : MAIN Clock Source Selection bit
0
0 : MOSC Clock
1 : PLL Clock
*** This register is accessed by setting the CLKWEN bit in the PMCTRLEN register to 1.
Advanced Digital Chips, Inc.
CONFIDENTIAL
41
CANTUS
Ver 2.04
Wake Up Control Register (WUKCTRL)
Address: 0x8002_040C
Bit
R/W
Description
Default Value
31 : 4
R
Reserved
Wake-up selection register update status bit
3
R
0
0 : Update complete
1 : Not update
2
R/W
PWK Wake-up Mode
1
0 : Rising edge
1 : Falling edge
1
R/W
PWK Wake-up Enable bit
1
0 : Disable
1 : Enable
0
R/W
RTC Interrupt Enable bit
1
0 : Disable
1 : Enable
*** This register is accessed by setting the WUKWEN bit in the PMCTRLEN register to 1.
HCLK Gating Control Register (HCLKGATE)
Address: 0x8002_0410
Bit
R/W
Description
Default Value
31 : 7
R
Reserved
6
R/W
SDHC Controller Clock Enable bit
1
0 : Disable
1 : Enable
5
R/W
NAND Flash Controller Clock Enable bit
1
0 : Disable
1 : Enable
4
R/W
DMA Controller Clock Enable bit
1
0 : Disable
1 : Enable
3
R/W
Internal SRAM Controller Clock Enable bit
1
0 : Disable
1 : Enable
2
R/W
Internal NOR Flash /
1
External SRAM Controller Clock Enable bit
0 : Disable
1 : Enable
1
R/W
ISP Controller Clock Enable bit
1
0 : Disable
1 : Enable
0
R/W
AHB Bus Clock Enable bit
1
0 : Disable
1 : Enable
*** This register is accessed by setting the HGWEN bit in the PMCTRLEN register to 1.
42
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
PCLK Gating Control Register (PCLKGATE)
Address: 0x8002_0414
Bit
R/W
Description
Default Value
31 : 14
R
Reserved
13
R/W
GPIO (Port Alternate Function) Clock Enable bit
1
0 : Disable
1 : Enable
12
R/W
RTC Clock Enable bit
1
0 : Disable
1 : Enable
11
R/W
KeyScan Clock Enable bit
1
0 : Disable
1 : Enable
10
R/W
USB Device Clock Enable bit
1
0 : Disable
1 : Enable
9
R/W
I2S Clock Enable bit
1
0 : Disable
1 : Enable
8
R/W
Voice Clock Enable bit
1
0 : Disable
1 : Enable
7
R/W
GPIO (Port Control, Port Edge Detect) Clock Enable
1
bit
0 : Disable
1 : Enable
6
R/W
TWI Clock Enable bit
1
0 : Disable
1 : Enable
5
R/W
SPI Clock Enable bit
1
0 : Disable
1 : Enable
4
R/W
UART Clock Enable bit
1
0 : Disable
1 : Enable
3
R/W
Timer Clock Enable bit
1
0 : Disable
1 : Enable
2
R/W
Watchdog Timer Clock Enable bit
1
0 : Disable
1 : Enable
1
R/W
Interrupt Controller Clock Enable bit
1
0 : Disable
1 : Enable
0
R/W
APB Bus Clock Enable bit
1
0 : Disable
1 : Enable
*** This register is accessed by setting the PGWEN bit in the PMCTRLEN register to 1.
Special Clock Gating Control Register (SCLKGATE)
Address: 0x8002_0418
Bit
R/W
Description
Default Value
31 : 3
R
Reserved
2
R/W
IMCLKEN : I2S and Voice Codec Clock Enable bit
0
0 : Disable
1 : Enable
1
R/W
USB12EN : USB12M Clock Enable bit
0
0 : Disable
1 : Enable
0
R/W
USB48EN : USB48M Clock Enable bit
0
0 : Disable
1 : Enable
*** This register is accessed by setting the SGWEN bit in the PMCTRLEN register to 1.
Advanced Digital Chips, Inc.
CONFIDENTIAL
43
CANTUS
Ver 2.04
Software Reset Control Register (RSTCTRL)
Address: 0x8002_041C
Bit
R/W
Description
Default Value
31 : 1
R
Reserved
0
W
Software Reset
0: No effect
1 : Set to system reset
*** This register is accessed by setting the RSTWEN bit in the PMCTRLEN register to 1.
Reset Status Register (RSTSTAT)
Address: 0x8002_041C
Bit
R/W
Description
Default Value
31 : 4
R
Reserved
3
R
POR reset occurred
0
2
R
Sleep mode reset occurred
0
1
R
Software reset occurred
0
0
R
Watchdog reset occurred
0
*** Reports the cause of the last reset. Reading this RSTSTAT does clear this field.
*** All zero means that the External reset is occurred.
44
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
Power Management Control Enable Register (PMCTRLEN)
Address: 0x8002_0424
Bit
R/W
Description
Default Value
31 : 9
R
Reserved
HALTEN : HALT Process Enable bit
8
R/W
0
0 : Disable
1: Enable
RSTWEN : RSTCTRL Register Write Enable bit
7
R/W
0
0 : Disable
1: Enable
SGWEN : SCLKGATE Register Write Enable bit
6
R/W
0
0 : Disable
1: Enable
PGWEN : PCLKGATE Register Write Enable bit
5
R/W
0
0 : Disable
1: Enable
HGWEN : HCLKGATE Register Write Enable bit
4
R/W
0
0 : Disable
1: Enable
WUKWEN : WUKCTRL Register Write Enable bit
3
R/W
0
0 : Disable
1: Enable
2
R/W
Reserved
0
CLKWEN : CLKCTRL Register Write Enable bit
1
R/W
0
0 : Disable
1: Enable
PLLWEN : PLLCTRL Register Write Enable bit
0
R/W
0
0 : Disable
1: Enable
*** For write access to all other registers, the appropriate bits of this register must be set to 1.
Advanced Digital Chips, Inc.
CONFIDENTIAL
45
CANTUS
5
Ver 2.04
INTERNAL NOR FLASH AND EXTERNAL SRAM CONTROLLER
5.1 Internal NOR Flash Memory
CANTUS128 has a built-in 128Kbyte Flash Memory. It consists of eight 16Kbyte sectors.
Table 5-1 NOR Flash Memory (CANTUS128)
Address Range (512KBytes)
Sector Number
0x0000_0000∼0x0000_3FFF
Sector 0 (16KBytes)
0x0000_4000∼0x0000_7FFF
Sector 1 (16KBytes)
0x0000_8000∼0x0000_BFFF
Sector 2 (16KBytes)
0x0000_C000∼0x0000_FFFF
Sector 3 (16KBytes)
0x0001_0000∼0x0001_3FFF
Sector 4 (16KBytes)
0x0001_4000∼0x0001_7FFF
Sector 5 (16KBytes)
0x0001_8000∼0x0001_BFFF
Sector 6 (16KBytes)
0x0001_C000∼0x0001_FFFF
Sector 7 (16KBytes)
CANTUS512 has a built-in 512Kbyte Flash Memory. It consists of eight 64Kbyte sectors.
Table 5-2 NOR Flash Memory (CANTUS512)
Address Range (512KBytes)
Sector Number
0x0000_0000∼0x0000_FFFF
Sector 0 (64KBytes)
0x0001_0000∼0x0001_FFFF
Sector 1 (64KBytes)
0x0002_0000∼0x0002_FFFF
Sector 2 (64KBytes)
0x0003_0000∼0x0003_FFFF
Sector 3 (64KBytes)
0x0004_0000∼0x0004_FFFF
Sector 4 (64KBytes)
0x0005_0000∼0x0005_FFFF
Sector 5 (64KBytes)
0x0006_0000∼0x0006_FFFF
Sector 6 (64KBytes)
0x0007_0000∼0x0007_FFFF
Sector 7 (64KBytes)
46
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
As internal NOR Flash Memory has the access rate of maximum 80nsec, the access cycle
should be changed depending on HCLK rateIf tACC bit is set to “00” when HCLK reads NOR Flash
Memory at the rate of 12MHz or lower, it access NOR Flash Memory at 1-cycle. When the rate is
faster than 12MHz, tACC should be set by the unit of HCLK/12MHz.
CANTUS has a built-in I-Cache so that CPU can process commands every clock independently
of NOR Flash timing even when HCLK is faster than 12MHz.
HCLK
ADDR
nCS
nRE \
nWE
tCSS
tOES
tACC
tOEH
tCSH
Figure 5-1 NOR Flash Timing Diagram
Advanced Digital Chips, Inc.
CONFIDENTIAL
47
CANTUS
Ver 2.04
In the event of programming internal NOR Flash Memory, it is possible to upload the desired
program to internal SRAM and than proceed with NOR Flash erase and programming using
JEDEC standard command.
As Erase and Program commands have Erase time and Program time, the command execution
should be confirmed when they are completed. Erase time reads the value of the erased address
and the value of „0xFF‟ indicates that the command execution has been completed. On the other
hand, Program time reads the programmed address and the value of „0xFF‟ indicates that the
command execution has been completed.
It is possible to identify the type of internal NOR Flash Memory, by reading NOR Flash ID with
Autoselect command. Once Autoselect command is executed, Read, Program, or Erase command
is not accepted. Therefore, after Autoselect command is executed, Reset command must be
executed. NOR Flash ID of CANTUS128 is „0x1C6E‟ and that of CANTUS512 is „0x1C4F.‟
Table 5-3 NOR Flash Command Definitions
NOR Flash ID (MSB)
6E/
4F
NOR Flash ID (LSB)
48
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
5.2 External SRAM Memory
CANTUS supports external 8/16-bit NOR Flash, PROM and SRAM. It can use up to four 512KB
memories.
For interface with external static memory, it supports SRAM_ALE1,
SRAM_nCS[3:0], SRAM_nRE, SRAM_nWE, AD[15:0], A[18:16], and nBE1.
SRAM_ALE0,
For interface with external 8-bit SRAM, AD[7:0] generates Address[15:0] and Data[7:0] signals.
When SRAM_ALE1 latches AD[7:0], it becomes Address[15:8] but when SRAM_ALE0 latches
AD[7:0], it becomes Address[7:0]. Then, AD[7:0] can read or write Data[7:0] in the sections of
SRAM_nCS, SRAM_nRE, and SRAM_nWE.
HCLK
A[18:16]
AD[7:0]
Address[18:16]
Address[15:8]
Address[7:0]
Data[7:0]
SRAM_ALE1
SRAM_ALE0
SRAM_nCS
SRAM_nRE /
SRAM_nWE
tCSS
tOES
tACC
tOEH
tCSH
Figure 5-2 External 8-bit SRAM Memory Timing Diagram
8-bit interface : 8-BIT SRAM 사용 시
8-BIT SRAM
CSx
nCS
WEx
nWE
OEx
nRE
CANTUS
SRAM_ALE1
AD[7:0]
SRAM_ALE0
AD[7:0]
High
Address
Latch
Addr[15:8]
ADR[15:0]
Low
Address
Latch
Addr[15:0]
Addr[7:0]
A[18:16]
AD[7:0]
ADR[18:16]
DATA[7:0]
Figure 5-3 Connection 8-bit SRAM Memory
Advanced Digital Chips, Inc.
CONFIDENTIAL
49
CANTUS
Ver 2.04
For interface with external 16-bit SRAM, AD[15:0] generates Address[15:0] and Data[15:0]
signals. When SRAM_ALE0 latches AD[15:0], it becomes Address[15:0]. Then, AD[15:0] can read
or write Data[15:0] in the sections of SRAM_nCS, SRAM_nRE, and SRAM_nWE.
HCLK
A[18:16]
Address[18:16]
AD[15:0]
Address[15:0]
Data[15:0]
SRAM_ALE0
SRAM_nCS
SRAM_nRE /
SRAM_nWE
tCSS
tOES
tACC
tOEH
tCSH
Figure 5-4 External 16-bit SRAM Memory Timing Diagram
16-bitinterface:
interface when
: 16-BIT
SRAM
사용is시
16-bit
16-bit
SRAM
used
16-BIT SRAM
CSx
nCS
WEx
nWE
OEx
nRE
UBEx
nBE1
CANTUS
SRAM_ALE0
AD[15:8]
SRAM_ALE0
AD[7:0]
High
Address
Latch
Low
Address
Latch
LBEx
Addr[0]
Addr[15:8]
ADR[14:0]
Addr[15:1]
Addr[7:0]
ADR[17:15]
A[18:16]
DATA[15:0]
AD[15:0]
Figure 5-5 Connection 16-bit SRAM Memory
50
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
5.3 Internal NOR Flash and External SRAM Control Registers
Internal NOR Flash Memory Control Register (FLASHCTRL)
Address: 0x8000_0410
Bit
R/W
Description
31 : 16
R
Reserved
15 : 14
R/W
tCSS : Address Set-up before nCS
00 : 0 Clock
01 : 1 Clock
10 : 2 Clock
11 : 4 Clock
13 : 12
R/W
tOES : Chip Selection Set-up nRE / nWE
00 : 0 Clock
01 : 1 Clock
10 : 2 Clock
11 : 4 Clock
11 : 8
R/W
tACC : Access Cycle
0000 : 1 Clock
0001 : 2 Clock
0010 : 3 Clock
0011 : 4 Clock
0100 : 6 Clock
0101 : 8 Clock
0110 : 10 Clock
0111 : 12 Clock
1000 : 14 Clock
1001 : 16 Clock
1010 : 18 Clock
1011 : 20 Clock
1100 : 22 Clock
1101 : 24 Clock
1110 : 26 Clock
1111 : 30 Clock
7:6
R/W
tOEH : Chip Selection Hold on nRE / nWE
00 : 0 Clock
01 : 1 Clock
10 : 2 Clock
11 : 4 Clock
5:4
R/W
tCSH : Address Holding Time after nCS
00 : 0 Clock
01 : 1 Clock
10 : 2 Clock
11 : 4 Clock
3:1
R
Reserved
0
R/W
Error Response Enable bit in NOR Flash
0 : Error Response Disable
1 : Error Response Enable
Advanced Digital Chips, Inc.
CONFIDENTIAL
Default Value
00
00
0001
11
11
1
51
CANTUS
Ver 2.04
External SRAM_nCS0 Area Control Register (CS0CTRL)
Address: 0x8000_0400
Bit
R/W
Description
31 : 16
R
Reserved
15 : 14
R/W
tCSS : Address Set-up before SRAM_nCS0
00 : 0 Clock
01 : 1 Clock
10 : 2 Clock
11 : 4 Clock
13 : 12
R/W
tOES : Chip Selection Set-up nRE / nWE
00 : 0 Clock
01 : 1 Clock
10 : 2 Clock
11 : 4 Clock
11 : 8
R/W
tACC : Access Cycle
0000 : 1 Clock
0001 : 2 Clock
0010 : 3 Clock
0011 : 4 Clock
0100 : 6 Clock
0101 : 8 Clock
0110 : 10 Clock
0111 : 12 Clock
1000 : 14 Clock
1001 : 16 Clock
1010 : 18 Clock
1011 : 20 Clock
1100 : 22 Clock
1101 : 24 Clock
1110 : 26 Clock
1111 : 30 Clock
7:6
R/W
tOEH : Chip Selection Hold on nRE / nWE
00 : 0 Clock
01 : 1 Clock
10 : 2 Clock
11 : 4 Clock
5:4
R/W
tCSH : Address Holding Time after SRAM_nCS0
00 : 0 Clock
01 : 1 Clock
10 : 2 Clock
11 : 4 Clock
3
R/W
This bit determines whether using nBE1 pin for 16bit
Data bus
0 : Not using nBE1
1 : Using nBE1
2
R/W
This bit determines WAIT status
0 : nWAIT Disable
1 : nWAIT Enable
1
R
Reserved
0
R/W
Error Response Enable bit in Read only Memory
0 : Error Response Disable
1 : Error Response Enable
52
CONFIDENTIAL
Default Value
11
11
1111
11
11
0
0
0
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
External SRAM_nCS[3:1] Area Control Register (CSxCTRL)
Address: 0x8000_0404 / 0x8000_0408 / 0x8000_040C
Bit
R/W
Description
31 : 16
R
Reserved
15 : 14
R/W
tCSS : Address Set-up before SRAM_nCSx
00 : 0 Clock
01 : 1 Clock
10 : 2 Clock
11 : 4 Clock
13 : 12
R/W
tOES : Chip Selection Set-up nRE / nWE
00 : 0 Clock
01 : 1 Clock
10 : 2 Clock
11 : 4 Clock
11 : 8
R/W
tACC : Access Cycle
0000 : 1 Clock
0001 : 2 Clock
0010 : 3 Clock
0011 : 4 Clock
0100 : 6 Clock
0101 : 8 Clock
0110 : 10 Clock
0111 : 12 Clock
1000 : 14 Clock
1001 : 16 Clock
1010 : 18 Clock
1011 : 20 Clock
1100 : 22 Clock
1101 : 24 Clock
1110 : 26 Clock
1111 : 30 Clock
7:6
R/W
tOEH : Chip Selection Hold on nRE / nWE
00 : 0 Clock
01 : 1 Clock
10 : 2 Clock
11 : 4 Clock
5:4
R/W
tCSH : Address Holding Time after SRAM_nCSx
00 : 0 Clock
01 : 1 Clock
10 : 2 Clock
11 : 4 Clock
3
R/W
This bit determines whether using nBE1 pin for 16bit
Data bus
0 : Not using nBE1
1 : Using nBE1
2
R/W
This bit determines WAIT status
0 : nWAIT Disable
1 : nWAIT Enable
1:0
R/W
This bit determines data bus width
00 : 8 bit
01 : 16 bit
1x : Reserved
Advanced Digital Chips, Inc.
CONFIDENTIAL
Default Value
11
11
1111
11
11
0
0
0
53
CANTUS
Ver 2.04
6 COPROCESSOR
Coprocessor of CANTUS includes Memory Management Unit (MMU) for memory management,
and I-Cache and D-Cache function blocks, and takes charge of controlling these function blocks
and other additional function blocks.
Key Features
- Memory Management Unit
- Real Memory mode
- 2 Way Set Associative Harvard Cache
- 8KBytes I-Cache
- 4Kbytes D-Cache
- Write Back / Write Through
- 16 Bytes / Line
- LRU Replacement
- Cache Invalidation by Software
- 4 Words Deep Write Buffer (FIFO)
Real Memory mode allows CPU to access only the memory area reserved for 4GB-zise linear
memory area, and the CPU address agrees with the actual memory address.
Table 6-1 Real Memory map in NOR Flash boot mode
Address Range (512KBytes)
Sector Number
0x0000_0000∼0x0007_FFFF
NOR Flash
(Memory Bank0)
0x2000_0000∼0x3FFF_FFFF
Internal SRAM
(Memory Bank1)
0x4000_0000∼0x5FFF_FFFF
External SRAM_nCS0
(Memory Bank2)
0x6000_0000∼0x7FFF_FFFF
External SRAM_nCS[3:1]
(Memory Bank3)
0x8000_0000∼0xFFFF_FFFF
Reserved
54
CONFIDENTIAL
Size
512KBytes
80KBytes
512KBytes
1536KBytes
-
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
6.1 Coprocessor Description
Register
SCPR15
SCPR14
SCPR13
SCPR12
SCPR11
SCPR10
SCPR9
SCPR8
SCPR7
SCPR6
SCPR5
SCPR4
SCPR3
SCPR2
SCPR1
SCPR0
R/W
R
W
R/W
R/W
R/W
W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Table 6-2 Coprocessor Register Description
Description
System Coprocessor Status Register
Master Command Register
Supervisor Stack Point Register
User Stack Pointer
Vector Base Register
Invalidate Cache Line and Lock Register
Reserved
Memory Bank Configuration Register
Sub-Bank Configuration Register
Reserved
Reserved
Sub-Bank Address Register
General Access Point Data Register
General Access Point Index Register
Reserved
Reserved
Reserved
Advanced Digital Chips, Inc.
CONFIDENTIAL
55
CANTUS
Ver 2.04
6.2 Coprocessor Control Registers
System Coprocessor Status Register (SCPR15)
Bit
R/W
Description
31
R
Reflects the status of System Co-Processor access
right (Privileged).
0 : Supervisor/User Accessible
1 : Supervisor Access only
30 : 28
R
Coprocessor Type
27 : 25
R
Coprocessor Subtype
24 : 19
R
Reserved
18
R
L1 Cache Presented
0 : Presented
1 : Not Presented
17
R
L1 Cache Snooping Capability
0 : Support Snooping
1 : Not support Snooping
16
R
L1 Cache Replacement Policy
0 : Support Write-through only
1 : Support Write-through and Write-back
15 : 7
R
Reserved
6
R
Misalign Correction Support for Data Access
0 : Not support Misalign Correction
1 : Support Misalign Correction
5:2
R
SCP Rending Exception Number
0000 : Inst. Fetch - Access Violation
0010 : Privilege Violation Exception
0011 : Data Access - Address Misalignment
0100 : Data Access – Access Violation
1000 : Inst. Fetch - Address Misalignment
1111 : N/A
1
R
SCP Pending Exception status
0 : No Pending Exception
1 : Pending Exception Exist
0
R
Reserved
Master Command Register (SCPR15)
Bit
R/W
Description
31 : 6
W
Reserved
5:2
W
End of Exception
0000 : Inst. Fetch - Access Violation
0010 : Privilege Violation Exception
0011 : Data Access - Address Misalignment
0100 : Data Access – Access Violation
1000 : Inst. Fetch - Address Misalignment
1111 : Privilege Violation Exception
1:0
W
Reserved
Supervisor Stack Point Register (SCPR14)
Bit
R/W
Description
31 : 2
R/W
Supervisor Stack Pointer
1:0
R/W
Always 0
56
CONFIDENTIAL
Default Value
1
001
000
0
1
1
0
1111
0
-
Default Value
1111
-
Default Value
0x0000_0000
00
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
User Stack Point Register (SCPR13)
Bit
R/W
Description
31 : 2
R/W
User Stack Pointer
1:0
R/W
Always 0
Default Value
0x0000_0000
00
Vector Base Register (SCPR12)
Bit
R/W
Description
31 : 2
R/W
Vector Base for Exception
1:0
R/W
Always 0
Default Value
0x0000_0000
00
Invalidate Cache Line and Lock Register (SCPR11)
Bit
R/W
Description
31 : 7
W
Invalidation Target Address/Way
6:4
W
Invalidation Target Address/Way
3
W
Invalidation Mode
0 : Address Based Invalidation
1 : Way Based Invalidation
2
W
Copy-back Selection in Invalidation
0 : Invalidation without Copy-back
1 : Invalidation with Copy-back if need
1
W
Cache Line Locking in Invalidation
0 : Invalidation without Locking
1 : Invalidation with Locking
0
W
Cache Type in Invalidation
0 : I-Cache
1 : D-Cache
Advanced Digital Chips, Inc.
CONFIDENTIAL
Default Value
-
-
-
-
57
CANTUS
Ver 2.04
Memory Bank Configuration Register (SCPR9)
Bit
R/W
Description
31 : 16
R
Reserved
15
R/W
Always 0
14
R/W
Memory Bank 3 Access Right
0 : Supervisor only Accessible
1 : Supervisor/User Accessible
13 : 12
R/W
Memory Bank 3 Cache Configuration
00 : Disable Cache
01 : Reserved
10 : Enable Cache with Write-through
11 : Enable Cache with Write-back
11
R/W
Always 0
10
R/W
Memory Bank 2 Access Right
0 : Supervisor only Accessible
1 : Supervisor/User Accessible
9:8
R/W
Memory Bank 2 Cache Configuration
00 : Disable Cache
01 : Reserved
10 : Enable Cache with Write-through
11 : Enable Cache with Write-back
7
R/W
Always 0
6
R/W
Memory Bank 1 Access Right
0 : Supervisor only Accessible
1 : Supervisor/User Accessible
5:4
R/W
Memory Bank 1 Cache Configuration
00 : Disable Cache
01 : Reserved
10 : Enable Cache with Write-through
11 : Enable Cache with Write-back
3
R/W
Always 0
2
R/W
Memory Bank 0 Access Right
0 : Supervisor only Accessible
1 : Supervisor/User Accessible
1:0
R/W
Memory Bank 0 Cache Configuration
00 : Disable Cache
01 : Reserved
10 : Enable Cache with Write-through
11 : Enable Cache with Write-back
58
CONFIDENTIAL
Default Value
0
0
0
00
0
0
00
0
0
00
0
0
00
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
Sub-Bank Configuration Register (SCPR8)
Bit
R/W
Description
Default Value
31 : 7
R
Reserved
6:4
R/W
Sub-Bank Index
000
3
R/W
Sub-Bank Valid Control bit
0
0 : Invalid
1 : Valid
2
R/W
Sub-Bank Access Right
0
0 : Supervisor only Accessible
1 : Supervisor/User Accessible
1:0
R/W
Sub-Bank Cache Property Control bit
00
00 : Disable Cache, Disable Write buffer
01 : Disable Cache, Enable Write buffer
10 : Enable Cache with Write-through
11 : Enable Cache with Write-back
*** Set together with SCPR5, to designate Sub-Bank.
*** In an area where Sub-Bank is set, the Sub-Bank setting has priority over the memory bank
setting by SCPR9.
Sub-Bank Address Register (SCPR5)
Bit
R/W
Description
31 : 12
R/W
Sub-Bank Base Address[31:12]
11 : 0
R/W
Sub-Bank Size Enable
0x000 : 4KBytes
0x001 : 8KBytes
0x003 : 16KBytes
0x007 : 32KBytes
0x00F : 64KBytes
0x01F : 128KBytes
0x03F : 256KBytes
0x07F : 512KBytes
0x0FF : 1MBytes
*** When setting Sub-Bank, set it to be Nature Aligned.
Advanced Digital Chips, Inc.
CONFIDENTIAL
Default Value
0x00000
0x000
59
CANTUS
Ver 2.04
General Access Point Data Register (SCPR4)
Bit
R/W
Description
31 : 0
R
General Access Point Data
Register Value set by SCPR3
Default Value
0x0000_0000
General Access Point Index Register (SCPR3)
Bit
R/W
Description
31 : 0
W
General Access Point Index
Default Value
-
- Core Debugging Information
0x0000_0000 : Backup IR
0x0000_0001 : Backup ER
0x0000_0002 : Backup PC
0x0000_0010 : Backup EAD
- System Coprocessor Debugging Information
0x0000_0303 : Inst. Bus Error Address
0x0000_0304 : Data Bus Error Address
- Cache Lock Information
0x0000_0500 : Inst. Lock Condition
0x0000_0501 : Data Lock Condition
- Memory Bank Management Information
0x0000_0600 : Inst. MBMB Violation Address
0x0000_0601 : Data MBMB Violation Address
60
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
7 WATCHDOG TIMER
Watchdog timer serves returning CPU to normal operating state when CPU cannot perform its
normal operation due to a system error, a device that does not respond normally, or any noise.
When Watchdog Reset has been enabled, the value set to WDTCNT reduces down by „1‟ and
when it reaches „0,‟ Watchdog Reset occurs.
When Watchdog Reset occurs, the state in which Watchdog Reset occurs is stored in RSTSTAT
register.
Once watchdog timer is set, WDTCNT should be reset periodically so that 32-bit watchdog counter
value does not reach „0‟ to trigger watchdog reset.
Advanced Digital Chips, Inc.
CONFIDENTIAL
61
CANTUS
Ver 2.04
7.1 Watchdog Timer Control Registers
Watchdog Timer Control Register (WDTCTRL)
Address: 0x8002_0C00
Bit
R/W
Description
31 : 1
R
Reserved.
0
RW
WDTEN : Watchdog Timer Reset Enable bit
0 : Disable Watchdog Timer Reset
1 : Enable Watchdog Timer Reset
Default Value
0
Watchdog Timer Counter Value Register (WDTCNT)
Address: 0x8002_0C04
Bit
R/W
Description
31 : 0
RW
Watchdog Timer Counter 32-bit Value. Down-counter
62
CONFIDENTIAL
Default Value
0xFFFF_FFFF
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
8 GPIO (GENERAL PURPOSE I/O)
PxPUS
PAFx
Alternate Function
(Direction)
PxODIR/PxIDIR
VDD33
Alternate Function
(Output)
PxOHIGH/PxOLOW
Alternate Function
(Input)
PxILEV
PxEDS
1
1
Edge
Detect
PxRED
RxFED
Figure 8-1 GPIO Block Diagram
8.1 Port Alternate Functions
The initial value of GPIO ports is „Input‟ state and as it is pulled up, it can be prevented that
“unknown” is received as input.
In addition, port alternate functions allow GPIO ports to be shared by peripheral functions with
external references.
Port Alternate Function registers determine whether a pin is used as normal GPIO or whether it is
taken by the alternate function.
Group Index
0
PAF0
1
2
Pin
76
77
78
Advanced Digital Chips, Inc.
Table 8-1 Port Alternate Functions
st
nd
rd
1
2
3
AD[0]
AD[1]
AD[2]
CONFIDENTIAL
th
4 (default)
P0.0
P0.1
P0.2
63
CANTUS
PAF1
PAF2
PAF3
PAF4
PAF5
PAF6
64
Ver 2.04
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
79
82
83
84
85
2
3
4
5
6
7
8
9
86
87
88
89
92
93
94
95
66
67
68
69
70
71
72
73
26
27
28
29
30
31
32
33
34
35
36
38
39
40
41
42
96
97
98
99
23
TX[4]
RX[4]
TX[5]
RX[5]
TX[6]
RX[6]
TX[7]
RX[7]
KEY_O[0]
KEY_I[0]
KEY_O[1]
KEY_I[1]
KEY_O[2]
KEY_I[2]
KEY_O[3]
KEY_I[3]
SPI_nSS
EIRQ[0]
EIRQ[1]
nNMI
TX[0]
RX[0]
TX[1]
RX[1]
TX[2]
RX[2]
TX[3]
RX[3]
TMO[0]
TMO[1]
TMO[2]
TMO[3]
TMO[4]
TMO[5]
TMO[6]
TMO[7]
nTRST
TCK
TMS
TDI
POREN
SPI_MOSI
SPI_MISO
SPI_SCK
CAP[0]
CAP[1]
CAP[2]
CAP[3]
CAP[4]
CAP[5]
CAP[6]
CAP[7]
CONFIDENTIAL
AD[3]
AD[4]
AD[5]
AD[6]
AD[7]
AD[8]
AD[9]
AD[10]
AD[11]
AD[12]
AD[13]
AD[14]
AD[15]
SRAM_ALE0
SRAM_ALE1
SRAM_nRE
SRAM_nWE
SRAM_nCS[0]
SRAM_nCS[1]
SRAM_nCS[2]
SRAM_nCS[3]
nWAIT
nBE[1]
NDFL_nWE
NDFL_ALE
NDFL_CLE
NDFL_nCS
NDFL_nRE
NDFL_nBUSY
I2S_SDO
I2S_SDI
SDCD_DATA[3]
SDCD_DATA[2]
SDCD_CLK
SDCD_CMD
TWI_SCL
TWI_SDA
SDCD_DATA[1]
SDCD_DATA[0]
I2S_LRCK
I2S_SCLK
I2S_MCLK
A[16]
A[17]
A[18]
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P6.0
P6.1
P6.2
P6.3
P6.4
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
8.2 Port Control
GPIO ports comprise six 8-bit blocks and one 5-bit block, and provide total 53 I/O ports. Each
port can be easily configured by register setting and is available for various I/O applications and
system configuration.
-
P0.x has 8 I/O Ports
P1.x has 8 I/O Ports
P2.x has 8 I/O ports
P3.x has 8 I/O ports
P4.x has 8 I/O ports
P5.x has 8 I/O ports
P6.x has 5 I/O ports
Each GPIO port is set either as output mode by PxODIR register or as input mode by PxIDIR
register. Each port setting can be verified with PxDIR register. PxODIR and PxIDIR registers affect
GPIO operation only when their bits are set to “1” but do not affect any operation when the bits are
set to “0.”
Output level of GPIO ports is set to high level by PxOHIGH register and to low level by PxOLOW
register, when Output mode has been set. The output level setting can be verified with PxOLEV
register.
Input level of GPIO ports can be verified with PxILEV register. Pull-up resistance connected to
each port can be removed when there is an external input or when the port is used for output, to
reduce the leakage current when the signal level is “Low.”
Table 8-2 Internal Pull-up Resistance Characteristics
Parameter
Min
Typ
Max
Pull-Up Resistance
30
66
130
Advanced Digital Chips, Inc.
CONFIDENTIAL
Unit
K
65
CANTUS
Ver 2.04
8.3 Port Edge Detect
Each group of GPIO port can perform external interrupts in addition to external interrupts through
EIRQ pin, through GPIO Port Edge Detect functions. The GPIO ports support Rising Edge, Falling
Edge, and Any Edge modes.
8.4 GPIO Registers
Port Alternate Function 0 Register (PAF0)
Address: 0x8002_0020
Bit
R/W
Description
31 : 16
R
Reserved
15 : 14
R/W
P0.7 : P0.7 Port Selection bit
00 : Reserved
01 : Reserved
10 : AD[7]
11 : P0.7
13 : 12
R/W
P0.6 : P0.6 Port Selection bit
00 : Reserved
01 : Reserved
10 : AD[6]
11 : P0.6
11 : 10
R/W
P0.5 : P0.5 Port Selection bit
00 : Reserved
01 : Reserved
10 : AD[5]
11 : P0.5
9:8
R/W
P0.4 : P0.4 Port Selection bit
00 : Reserved
01 : Reserved
10 : AD[4]
11 : P0.4
7:6
R/W
P0.3 : P0.3 Port Selection bit
00 : Reserved
01 : Reserved
10 : AD[3]
11 : P0.3
5:4
R/W
P0.2 : P0.2 Port Selection bit
00 : Reserved
01 : Reserved
10 : AD[2]
11 : P0.2
3:2
R/W
P0.1 : P0.1 Port Selection bit
00 : Reserved
01 : Reserved
10 : AD[1]
11 : P0.1
1:0
R/W
P0.0 : P0.0 Port Selection bit
00 : Reserved
01 : Reserved
10 : AD[0]
11 : P0.0
66
CONFIDENTIAL
Default Value
11
11
11
11
11
11
11
11
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
Port Alternate Function 1 Register (PAF1)
Address: 0x8002_0024
Bit
R/W
Description
31 : 16
R
Reserved
15 : 14
R/W
P1.7 : P1.7 Port Selection bit
00 : RX[7]
01 : KEYI[3]
10 : AD[15]
11 : P1.7
13 : 12
R/W
P1.6 : P1.6 Port Selection bit
00 : TX[7]
01 : KEYO[3]
10 : AD[14]
11 : P1.6
11 : 10
R/W
P1.5 : P1.5 Port Selection bit
00 : RX[6]
01 : KEYI[2]
10 : AD[13]
11 : P1.5
9:8
R/W
P1.4 : P1.4 Port Selection bit
00 : TX[6]
01 : KEYO[2]
10 : AD[12]
11 : P1.4
7:6
R/W
P1.3 : P1.3 Port Selection bit
00 : RX[5]
01 : KEYI[1]
10 : AD[11]
11 : P1.3
5:4
R/W
P1.2 : P1.2 Port Selection bit
00 : TX[5]
01 : KEYO[1]
10 : AD[10]
11 : P1.2
3:2
R/W
P1.1 : P1.1 Port Selection bit
00 : RX[4]
01 : KEYI[0]
10 : AD[9]
11 : P1.1
1:0
R/W
P1.0 : P1.0 Port Selection bit
00 : TX[4]
01 : KEYO[0]
10 : AD[8]
11 : P1.0
Advanced Digital Chips, Inc.
CONFIDENTIAL
Default Value
11
11
11
11
11
11
11
11
67
CANTUS
Ver 2.04
Port Alternate Function 2 Register (PAF2)
Address: 0x8002_0028
Bit
R/W
Description
31 : 16
R
Reserved
15 : 14
R/W
P2.7 : P2.7 Port Selection bit
00 : Reserved
01 : SPI_nSS
10 : SRAM_nCS[3]
11 : P2.7
13 : 12
R/W
P2.6 : P2.6 Port Selection bit
00 : Reserved
01 : Reserved
10 : SRAM_nCS[2]
11 : P2.6
11 : 10
R/W
P2.5 : P2.5 Port Selection bit
00 : Reserved
01 : Reserved
10 : SRAM_nCS[1]
11 : P2.5
9:8
R/W
P2.4 : P2.4 Port Selection bit
00 : Reserved
01 : Reserved
10 : SRAM_nCS[0]
11 : P2.4
7:6
R/W
P2.3 : P2.3 Port Selection bit
00 : Reserved
01 : Reserved
10 : SRAM_nWE
11 : P2.3
5:4
R/W
P2.2 : P2.2 Port Selection bit
00 : Reserved
01 : Reserved
10 : SRAM_nRE
11 : P2.2
3:2
R/W
P2.1 : P2.1 Port Selection bit
00 : Reserved
01 : Reserved
10 : SRAM_ALE1
11 : P2.1
1:0
R/W
P2.0 : P2.0 Port Selection bit
00 : Reserved
01 : Reserved
10 : SRAM_ALE0
11 : P2.0
68
CONFIDENTIAL
Default Value
11
11
11
11
11
11
11
11
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
Port Alternate Function 3 Register (PAF3)
Address: 0x8002_002C
Bit
R/W
Description
31 : 16
R
Reserved
15 : 14
R/W
P3.7 : P3.7 Port Selection bit
00 : nNMI
01 : Reserved
10 : NDFL_nBUSY
11 : P3.7
13 : 12
R/W
P3.6 : P3.6 Port Selection bit
00 : Reserved
01 : Reserved
10 : NDFL_nRE
11 : P3.6
11 : 10
R/W
P3.5 : P3.5 Port Selection bit
00 : Reserved
01 : Reserved
10 : NDFL_nCS
11 : P3.5
9:8
R/W
P3.4 : P3.4 Port Selection bit
00 : Reserved
01 : Reserved
10 : NDFL_CLE
11 : P3.4
7:6
R/W
P3.3 : P3.3 Port Selection bit
00 : Reserved
01 : Reserved
10 : NDFL_ALE
11 : P3.3
5:4
R/W
P3.2 : P3.2 Port Selection bit
00 : Reserved
01 : Reserved
10 : NDFL_nWE
11 : P3.2
3:2
R/W
P3.1 : P3.1 Port Selection bit
00 : EIRQ[1]
01 : Reserved
10 : nBE1
11 : P3.1
1:0
R/W
P3.0 : P3.0 Port Selection bit
00 : EIRQ[0]
01 : Reserved
10 : nWAIT
11 : P3.0
Advanced Digital Chips, Inc.
CONFIDENTIAL
Default Value
11
11
11
11
11
11
11
11
69
CANTUS
Ver 2.04
Port Alternate Function 4 Register (PAF4)
Address: 0x8002_0030
Bit
R/W
Description
31 : 16
R
Reserved
15 : 14
R/W
P4.7 : P4.7 Port Selection bit
00 : RX[3]
01 : Reserved
10 : TWI_SDA
11 : P4.7
13 : 12
R/W
P4.6 : P4.6 Port Selection bit
00 : TX[3]
01 : Reserved
10 : TWI_SCL
11 : P4.6
11 : 10
R/W
P4.5 : P4.5 Port Selection bit
00 : RX[2]
01 : Reserved
10 : SDCD_CMD
11 : P4.5
9:8
R/W
P4.4 : P4.4 Port Selection bit
00 : TX[2]
01 : SPI_SCK
10 : SDCD_CLK
11 : P4.4
7:6
R/W
P4.3 : P4.3 Port Selection bit
00 : RX[1]
01 : SPI_MISO
10 : SDCD_D[2]
11 : P4.3
5:4
R/W
P4.2 : P4.2 Port Selection bit
00 : TX[1]
01 : SPI_MOSI
10 : SDCD_D[3]
11 : P4.2
3:2
R/W
P4.1 : P4.1 Port Selection bit
00 : RX[0]
01 Reserved
10 : I2S_SDI
11 : P4.1
1:0
R/W
P4.0 : P4.0 Port Selection bit
00 : TX[0]
01 : Reserved
10 : I2S_SDO
11 : P4.0
70
CONFIDENTIAL
Default Value
11
11
11
11
11
11
11
11
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
Port Alternate Function 5 Register (PAF5)
Address: 0x8002_0034
Bit
R/W
Description
31 : 16
R
Reserved
15 : 14
R/W
P5.7 : P5.7 Port Selection bit
00 : TMO[7]
01 : CAP[7]
10 : A[18]
11 : P5.7
13 : 12
R/W
P5.6 : P5.6 Port Selection bit
00 : TMO[6]
01 : CAP[6]
10 : A[17]
11 : P5.6
11 : 10
R/W
P5.5 : P5.5 Port Selection bit
00 : TMO[5]
01 : CAP[5]
10 : A[16]
11 : P5.5
9:8
R/W
P5.4 : P5.4 Port Selection bit
00 : TMO[4]
01 : CAP[4]
10 : I2S_MCLK
11 : P5.4
7:6
R/W
P5.3 : P5.3 Port Selection bit
00 : TMO[3]
01 : CAP[3]
10 : I2S_SCLK
11 : P5.3
5:4
R/W
P5.2 : P5.2 Port Selection bit
00 : TMO[2]
01 : CAP[2]
10 : I2S_LRCK
11 : P5.2
3:2
R/W
P5.1 : P5.1 Port Selection bit
00 : TMO[1]
01 : CAP[1]
10 : SDCD_D[0]
11 : P5.1
1:0
R/W
P5.0 : P5.0 Port Selection bit
00 : TMO[0]
01 : CAP[0]
10 : SDCD_D[1]
11 : P5.0
Advanced Digital Chips, Inc.
CONFIDENTIAL
Default Value
11
11
11
11
11
11
11
11
71
CANTUS
Ver 2.04
Port Alternate Function 6 Register (PAF6)
Address: 0x8002_0038
Bit
R/W
Description
31 : 10
R
Reserved
9:8
R/W
P6.4 : P6.4 Port Selection bit
00 : POREN
01 : Reserved
10 : Reserved
11 : P6.4
7:6
R/W
P6.3 : P6.3 Port Selection bit
00 : TDI
01 : Reserved
10 : Reserved
11 : P6.3
5:4
R/W
P6.2 : P6.2 Port Selection bit
00 : TMS
01 : Reserved
10 : Reserved
11 : P6.2
3:2
R/W
P6.1 : P6.1 Port Selection bit
00 : TCK
01 : Reserved
10 : Reserved
11 : P6.1
1:0
R/W
P6.0 : P6.0 Port Selection bit
00 : TRST
01 : Reserved
10 : Reserved
11 : P6.0
72
CONFIDENTIAL
Default Value
00
00
00
00
00
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
Port Direction Registers ( PxDIR )
Address: 0x8002_3400 / 0x8002_3440 / 0x8002_3480 /
0x8002_3500 / 0x8002_3540 / 0x8002_3580 /
0x8002_3600
Bit
R/W
Description
31 : 8
R
Reserved
7:0
R
Px.yDIR : Px.y Direction bit
0 : Input
1 : Output
Default Value
0x00
Port Direction Output Mode Setting Registers ( PxODIR )
Address: 0x8002_3400 / 0x8002_3440 / 0x8002_3480 /
0x8002_3500 / 0x8002_3540 / 0x8002_3580 /
0x8002_3600
Bit
R/W
Description
Default Value
31 : 8
R
Reserved
7
W
Px.7ODIR : Px.7 Direction Output Mode Setting bit
6
W
Px.6ODIR : Px.6 Direction Output Mode Setting bit
5
W
Px.5ODIR : Px.5 Direction Output Mode Setting bit
4
W
Px.4ODIR : Px.4 Direction Output Mode Setting bit
3
W
Px.3ODIR : Px.3 Direction Output Mode Setting bit
2
W
Px.2ODIR : Px.2 Direction Output Mode Setting bit
1
W
Px.1ODIR : Px.1 Direction Output Mode Setting bit
0
W
Px.0ODIR : Px.0 Direction Output Mode Setting bit
*** Port Direction Output Mode Setting bit
0: No effect
1 : Set to output mode the corresponding bit in the PxDIR registers
Port Direction Input Mode Setting Registers ( PxIDIR )
Address: 0x8002_3404 / 0x8002_3444 / 0x8002_3484 /
0x8002_3504 / 0x8002_3544 / 0x8002_3584 /
0x8002_3604
Bit
R/W
Description
Default Value
31 : 8
R
Reserved
7
W
Px.7IDIR : Px.7 Direction Input Mode Setting bit
6
W
Px.6IDIR : Px.6 Direction Input Mode Setting bit
5
W
Px.5IDIR : Px.5 Direction Input Mode Setting bit
4
W
Px.4IDIR : Px.4 Direction Input Mode Setting bit
3
W
Px.3IDIR : Px.3 Direction Input Mode Setting bit
2
W
Px.2IDIR : Px.2 Direction Input Mode Setting bit
1
W
Px.1IDIR : Px.1 Direction Input Mode Setting bit
0
W
Px.0IDIR : Px.0 Direction Input Mode Setting bit
*** Port Direction Input Mode Setting bit
0: No effect
1 : Set to input mode the corresponding bit in the PxDIR registers
Advanced Digital Chips, Inc.
CONFIDENTIAL
73
CANTUS
Ver 2.04
Port Output Data Level Registers ( PxOLEV )
Address: 0x8002_3408 / 0x8002_3448 / 0x8002_3488 /
0x8002_3508 / 0x8002_3548 / 0x8002_3588 /
0x8002_3608
Bit
R/W
Description
31 : 8
R
Reserved
7:0
R
Px.yOLEV : Px.y Output Level bit
0 : Low Level
1 : High Level
Default Value
0x00
Port Output Data High Level Setting Registers ( PxOHIGH )
Address: 0x8002_3408 / 0x8002_3448 / 0x8002_3488 /
0x8002_3508 / 0x8002_3548 / 0x8002_3588 /
0x8002_3608
Bit
R/W
Description
31 : 8
R
Reserved
7
W
Px.7OH : Px.7 Output Data High Level Setting bit
6
W
Px.6OH : Px.6 Output Data High Level Setting bit
5
W
Px.5OH : Px.5 Output Data High Level Setting bit
4
W
Px.4OH : Px.4 Output Data High Level Setting bit
3
W
Px.3OH : Px.3 Output Data High Level Setting bit
2
W
Px.2OH : Px.2 Output Data High Level Setting bit
1
W
Px.1OH : Px.1 Output Data High Level Setting bit
0
W
Px.0OH : Px.0 Output Data High Level Setting bit
*** Port Output Data High Level Setting bit
0: No effect
1 : Set to high level output data the corresponding bit in the PxOLEV registers
Port Output Data Low Level Setting Registers ( PxOLOW )
Address: 0x8002_340C / 0x8002_344C / 0x8002_348C /
0x8002_350C / 0x8002_354C / 0x8002_358C /
0x8002_360C
Bit
R/W
Description
31 : 8
R
Reserved
7
W
Px.7OL : Px.7 Output Data Low Level Setting bit
6
W
Px.6OL : Px.6 Output Data Low Level Setting bit
5
W
Px.5OL : Px.5 Output Data Low Level Setting bit
4
W
Px.4OL : Px.4 Output Data Low Level Setting bit
3
W
Px.3OL : Px.3 Output Data Low Level Setting bit
2
W
Px.2OL : Px.2 Output Data Low Level Setting bit
1
W
Px.1OL : Px.1 Output Data Low Level Setting bit
0
W
Px.0OL : Px.0 Output Data Low Level Setting bit
*** Port Output Data Low Level Setting bit
0: No effect
1 : Set to low level output data the corresponding bit in the PxOLEV registers
74
CONFIDENTIAL
Default Value
-
Default Value
-
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
Port Input Data Level Registers ( PxILEV )
Address: 0x8002_3410 / 0x8002_3450 / 0x8002_3490 /
0x8002_3510 / 0x8002_3550 / 0x8002_3590 /
0x8002_3610
Bit
R/W
Description
31 : 8
R
Reserved
7
R
Px.7ILEV : Px.7 Input Level bit
0 : Low Level
1 : High Level
6
R
Px.6ILEV : Px.6 Input Level bit
0 : Low Level
1 : High Level
5
R
Px.5ILEV : Px.5 Input Level bit
0 : Low Level
1 : High Level
4
R
Px.4ILEV : Px.4 Input Level bit
0 : Low Level
1 : High Level
3
R
Px.3ILEV : Px.3 Input Level bit
0 : Low Level
1 : High Level
2
R
Px.2ILEV : Px.2 Input Level bit
0 : Low Level
1 : High Level
1
R
Px.1ILEV : Px.1 Input Level bit
0 : Low Level
1 : High Level
0
R
Px.0ILEV : Px.0 Input Level bit
0 : Low Level
1 : High Level
Advanced Digital Chips, Inc.
CONFIDENTIAL
Default Value
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
Pull-up
75
CANTUS
Ver 2.04
Port Pull-up Status Registers ( PxPUS )
Address: 0x8002_3418 / 0x8002_3458 / 0x8002_3498 /
0x8002_3518 / 0x8002_3558 / 0x8002_3598 /
0x8002_3618
Bit
R/W
Description
31 : 8
R
Reserved
7:0
R
Px.yUP : Px.y Pull-up Status bit
0 : Pull-up Disable
1 : Pull-up Enable
Port Pull-up Enable Registers ( PxPUEN )
Address: 0x8002_3418 / 0x8002_3458 / 0x8002_3498 /
0x8002_3518 / 0x8002_3558 / 0x8002_3598 /
0x8002_3618
Bit
R/W
Description
31 : 8
R
Reserved
7
W
Px.7PUEN : Px.7 Pull-up enable bit
6
W
Px.6PUEN : Px.6 Pull-up enable bit
5
W
Px.5PUEN : Px.5 Pull-up enable bit
4
W
Px.4PUEN : Px.4 Pull-up enable bit
3
W
Px.3PUEN : Px.3 Pull-up enable bit
2
W
Px.2PUEN : Px.2 Pull-up enable bit
1
W
Px.1PUEN : Px.1 Pull-up enable bit
0
W
Px.0PUEN : Px.0 Pull-up enable bit
*** Port Pull-up enable bit
0: No effect
1: Set to pull-up the corresponding bit in the PxPUS registers
Port Pull-up Disable Registers ( PxPUDIS )
Address: 0x8002_341C / 0x8002_345C / 0x8002_349C /
0x8002_351C / 0x8002_355C / 0x8002_359C /
0x8002_361C
Bit
R/W
Description
31 : 8
R
Reserved
7
W
Px.7PUDIS : Px.7 Pull-up disable bit
6
W
Px.6PUDIS : Px.6 Pull-up disable bit
5
W
Px.5PUDIS : Px.5 Pull-up disable bit
4
W
Px.4PUDIS : Px.4 Pull-up disable bit
3
W
Px.3PUDIS : Px.3 Pull-up disable bit
2
W
Px.2PUDIS : Px.2 Pull-up disable bit
1
W
Px.1PUDIS : Px.1 Pull-up disable bit
0
W
Px.0PUDIS : Px.0 Pull-up disable bit
*** Port Pull-up disable bit
0: No effect
1: Set to pull-up the corresponding bit in the PxPUS registers
76
CONFIDENTIAL
Default Value
0xFF
Default Value
-
Default Value
-
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
Port Rising Edge Detect Registers ( PxRED )
Address: 0x8002_3420 / 0x8002_3460 / 0x8002_34A0 /
0x8002_3520 / 0x8002_3560 / 0x8002_35A0 /
0x8002_3620
Bit
R/W
Description
Default Value
31 : 8
R
Reserved
7
R/W
Px.7RED : Px.7 Rising Edge Detect bit
0
0 : Disable
1 : Enable
6
R/W
Px.6RED : Px.6 Rising Edge Detect bit
0
0 : Disable
1 : Enable
5
R/W
Px.5RED : Px.5 Rising Edge Detect bit
0
0 : Disable
1 : Enable
4
R/W
Px.4RED : Px.4 Rising Edge Detect bit
0
0 : Disable
1 : Enable
3
R/W
Px.3RED : Px.3 Rising Edge Detect bit
0
0 : Disable
1 : Enable
2
R/W
Px.2RED : Px.2 Rising Edge Detect bit
0
0 : Disable
1 : Enable
1
R/W
Px.1RED : Px.1 Rising Edge Detect bit
0
0 : Disable
1 : Enable
0
R/W
Px.0RED : Px.0 Rising Edge Detect bit
0
0 : Disable
1 : Enable
*** When Rising Edge and Falling Edge are set at the same time, Any Edge mode is enabled.
Port Falling Edge Detect Registers ( PxFED )
Address: 0x8002_3424 / 0x8002_3464 / 0x8002_34A4 /
0x8002_3524 / 0x8002_3564 / 0x8002_35A4 /
0x8002_3624
Bit
R/W
Description
Default Value
31 : 8
R
Reserved
7
R/W
Px.7FED : Px.7 Falling Edge Detect bit
0
0 : Disable
1 : Enable
6
R/W
Px.6FED : Px.6 Falling Edge Detect bit
0
0 : Disable
1 : Enable
5
R/W
Px.5FED : Px.5 Falling Edge Detect bit
0
0 : Disable
1 : Enable
4
R/W
Px.4FED : Px.4 Falling Edge Detect bit
0
0 : Disable
1 : Enable
3
R/W
Px.3FED : Px.3 Falling Edge Detect bit
0
0 : Disable
1 : Enable
2
R/W
Px.2FED : Px.2 Falling Edge Detect bit
0
0 : Disable
1 : Enable
1
R/W
Px.1FED : Px.1 Falling Edge Detect bit
0
0 : Disable
1 : Enable
0
R/W
Px.0FED : Px.0 Falling Edge Detect bit
0
0 : Disable
1 : Enable
*** When Rising Edge and Falling Edge are set at the same time, Any Edge mode is enabled.
Advanced Digital Chips, Inc.
CONFIDENTIAL
77
CANTUS
Ver 2.04
Port Edge Detect Status Registers ( PxEDS )
Address: 0x8002_3428 / 0x8002_3468 / 0x8002_34A8 /
0x8002_3528 / 0x8002_3568 / 0x8002_35A8 /
0x8002_3628
Bit
R/W
Description
31 : 8
R
Reserved
7
R/W
Px.7EDS : Px.7 Edge Detect Status bit
6
R/W
Px.6EDS : Px.6 Edge Detect Status bit
5
R/W
Px.5EDS : Px.5 Edge Detect Status bit
4
R/W
Px.4EDS : Px.4 Edge Detect Status bit
3
R/W
Px.3EDS : Px.3 Edge Detect Status bit
2
R/W
Px.2EDS : Px.2 Edge Detect Status bit
1
R/W
Px.1EDS : Px.1 Edge Detect Status bit
0
R/W
Px.0EDS : Px.0 Edge Detect Status bit
*** Port Edge Detect Status bit
0: No edge detect has occurred on pin
1: Edge detect has occurred on pin
Default Value
0
0
0
0
0
0
0
0
*** Status bits are cleared by writing a one to them.
*** Writing a zero to a status bit is no effect.
78
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
9 INTERRUPTS
CANTUS has 32 channel interrupts that include 30 interrupts generated from internal devices
such as timer, SPI, TWI, UART and so on and two external interrupts.
Key Features
- 32 channel interrupts (external interrupts from 2 channels and internal interrupts from 30
channels)
- Operating condition setting for external interrupts (5 conditions)
- Operating condition setting for internal interrupts (2 conditions)
- Interrupt Enable for each channel
- Interrupt Mask for each channel
- Individually programmable interrupt priority
Interrupts are processed in the following sequence:
1. Each interrupt source requests the interrupt controller for an interrupt.
2. An interrupt is selected by Interrupt Enable Register and then stored in Interrupt Pending
Register.
3. After determining the interrupt priority, the interrupt controller requests CPU for an interrupt.
4. When an interrupt is requested, CPU interrupt is deactivated and the interrupt controller
reads the interrupt vector address to enter into the corresponding Interrupt Service Routine
(ISR).
5. It performs ISR.
6. After completing the ISR, the interrupt controller reads the corresponding vector value on
Interrupt Pending Clear Register, to erase the interrupt value stored in the Interrupt
Pending Register.
7. When the ISR is over, the CPU interrupt is activated.
Interrupt overlapping is done in the following process:
1. Each interrupt source requests the interrupt controller for an interrupt.
2. An interrupt is selected by Interrupt Enable Register and then stored in Interrupt Pending
Register.
3. After determining the interrupt priority, the interrupt controller requests CPU for an interrupt.
4. When an interrupt is requested, CPU interrupt is deactivated and the interrupt controller
reads the interrupt vector address, to enter into the corresponding Interrupt Service
Routine (ISR).
5. To allow interrupt overlapping, the interrupt controller reads the corresponding vector value
on Interrupt Pending Clear Register, to erase the interrupt value stored in Interrupt
Pending Register and then activate the CPU interrupt through asm (“set 13”).
6. It performs the ISR.
7. If another interrupt occurs during the current ISR, the interrupt controller enters into the
corresponding ISR as overlapping has been allowed.
8. When the newly activated ISR is completed, the interrupt controller returns to the previous
ISR to complete it.
9. When the ISR is over, the interrupt controller completely exits from the routine.
Advanced Digital Chips, Inc.
CONFIDENTIAL
79
CANTUS
Ver 2.04
9.1 Interrupt Vector and Priority
EIRQ0 has the highest interrupt priority. Each interrupt vector address has 4 byte size as CPU
does 32bit addressing.
Vector No.
0x3F
0x3E
0x3D
0x3C
0x3B
0x3A
0x39
0x38
0x37
0x36
0x35
0x34
0x33
0x32
0x31
0x30
0x2F
0x2E
0x2D
0x2C
0x2B
0x2A
0x29
0x28
0x27
0x26
0x25
0x24
0x23
0x22
0x21
0x20
80
Table 9-1 Interrupt Vector & Priority
Description
UART Ch7 | OCR 3B Interrupt
DMA Ch1 Interrupt
TIMER Ch7 | KEYSCAN Interrupt
GPIO5 Interrupt
UART Ch6 | OCR 3A Interrupt
NFCTRL | SDHC Interrupt
TIMER Ch6 Interrupt
GPIO4 Interrupt
UART Ch5 / OCR 2B Interrupt
VOICE Interrupt
TIMER Ch5 Interrupt
GPIO3 Interrupt
UART Ch4 | OCR 2A Interrupt
TWI / PWK and RTC Interrupt
TIMER Ch4 Interrupt
GPIO2 Interrupt
UART Ch3 Interrupt
SPI Interrupt
TIMER Ch3 Interrupt
GPIO1 Interrupt
UART Ch2 Interrupt
USB Device Interrupt
TIMER Ch2 Interrupt
GPIO0 Interrupt
UART Ch1 Interrupt
DMA Ch0 Interrupt
TIMER Ch1 Interrupt
EIRQ1 Interrupt
UART Ch0 Interrupt
I2S Interrupt
TIMER Ch0 Interrupt
EIRQ0 Interrupt (Highest Priority)
CONFIDENTIAL
Vector Address
0x000000FC
0x000000F8
0x000000F4
0x000000F0
0x000000EC
0x000000E8
0x000000E4
0x000000E0
0x000000DC
0x000000D8
0x000000D4
0x000000D0
0x000000CC
0x000000C8
0x000000C4
0x000000C0
0x000000BC
0x000000B8
0x000000B4
0x000000B0
0x000000AC
0x000000A8
0x000000A4
0x000000A0
0x0000009C
0x00000098
0x00000094
0x00000090
0x0000008C
0x00000088
0x00000084
0x00000080
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
9.2 External Interrupt (EIRQ0/EIRQ1)
For external interrupt, CANTUS receives 5 types of external interrupts by EINTMOD register
setting
- In Low Level mode, CANTUS generate interrupts every system cycle while External Interrupt
signal keeps “Low.”
- In High Level mode, it generates interrupts every system cycle while External Interrupt signal
keeps “High.”
- In Falling Edge mode, it generates interrupts when External Interrupt signal changes from
“High->Low.”
- In Rising Edge mode, it generates interrupts when External Interrupt signal changes from
“Low->High.”
- In Any Edge mode, it generates interrupts when External Interrupt signal changes from
“High->Low” or from “Low-> High.”
External
Interrupt
Low Level
Interrupt Event
High Level
Interrupt Event
Falling Edge
Interrupt Event
Rising Edge
Interrupt Event
Any Edge
Interrupt Event
Figure 9-1 External Interrupt Mode
Advanced Digital Chips, Inc.
CONFIDENTIAL
81
CANTUS
Ver 2.04
9.3 Internal Interrupt Mode
All internal interrupts operate as “Rising Edge.” However, if you want to handle interrupts as
“High Level,” you can set them with Internal Interrupt Mode Registers.
9.4 Interrupt Pending and Interrupt Pending Clear
Each interrupt state can be verified with Interrupt Pending Registers. Once generated, the
interrupt is stored in Interrupt Pending Register until it is cleared by Interrupt Pending Clear
Register. Also, if interrupts with higher priorities than that of a newly generated current interrupt
have been stored in Interrupt Pending Register without being masked, the new interrupt is pended
in Interrupt Pending Register and waits until its priority comes as those with higher priorities are all
cleared.
To clear the interrupts stored in Interrupt Pending Register, the corresponding interrupt vector
number values should be written in the Interrupt Pending Clear Register.
9.5 Interrupt Enable
While the interrupts masked by Interrupt Mask Register are kept stored in Interrupt Pending
Registers, those disabled by Interrupt Enable Register (IENR) are not stored in the Interrupt
Pending Register. Therefore, this register is used for disabling the interrupt it does not want to
receive.
9.6 Interrupt Mask Set/Clear Register
When Interrupt Mask is Set, the interrupt request is enabled and when it is Clear, the request is
disabled.
Each interrupt can be requested with Interrupt Mask Register. When Interrupt Mask Set bit is “1,”
the interrupt stored in Interrupt Pending Register is requested to CPU and when Interrupt Mask
Clear bit is “1,” the interrupt stored in Interrupt Pending Register cannot be requested to CPU.
As even the interrupt of which Mask bit is set to “0” is stored in Interrupt Pending Registers (IPR),
the interrupts stored in Interrupt Pending Register are requested again according to their priorities
if the Mask bit is re-set to “1.”
82
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
9.7 Interrupt Control Registers
Interrupt Pending Clear Register (PENDCLR)
Offset Address: 0x8002_0800
Bit
R/W
Description
Default Value
31 : 8
R
Reserved
7:0
W
Interrupt Pending Register Clear Value
0xFF
(0x20 ~ 0x3F)
*** Pending interrupts can be cleared by writing the corresponding interrupt vector number in this
register. Refer to Table 9-1 Interrupt Vector & Priority.
External Interrupt Mode and External PIN Level Register (EINTMOD)
Offset Address: 0x8002_0804
Bit
R/W
Description
31 : 8
R
Reserved
7
R
EIRQ1ST : EIRQ1 PIN Level
6:4
R/W
EIRQ1MOD : EIRQ1 Active State
000 : Low Level
001 : High Level
010 : Falling Edge 011 : Rising Edge
1xx : Any Edge
3
R
EIRQ0ST : EIRQ0 PIN Level
2:0
R/W
EIRQ0MOD : EIRQ0 Active State
000 : Low Level
001 : High Level
010 : Falling Edge 011 : Rising Edge
1xx : Any Edge
Advanced Digital Chips, Inc.
CONFIDENTIAL
Default Value
010
010
83
CANTUS
Ver 2.04
Internal Interrupt Mode Register (IINTMOD)
Offset Address: 0x8002_0808
Bit
R/W
Description
31
R/W
Vector No. 0x3F Interrupt Mode bit
30
R/W
Vector No. 0x3E Interrupt Mode bit
29
R/W
Vector No. 0x3D Interrupt Mode bit
28
R/W
Vector No. 0x3C Interrupt Mode bit
27
R/W
Vector No. 0x3B Interrupt Mode bit
26
R/W
Vector No. 0x3A Interrupt Mode bit
25
R/W
Vector No. 0x39 Interrupt Mode bit
24
R/W
Vector No. 0x38 Interrupt Mode bit
23
R/W
Vector No. 0x37 Interrupt Mode bit
22
R/W
Vector No. 0x36 Interrupt Mode bit
21
R/W
Vector No. 0x35 Interrupt Mode bit
20
R/W
Vector No. 0x34 Interrupt Mode bit
19
R/W
Vector No. 0x33 Interrupt Mode bit
18
R/W
Vector No. 0x32 Interrupt Mode bit
17
R/W
Vector No. 0x31 Interrupt Mode bit
16
R/W
Vector No. 0x30 Interrupt Mode bit
15
R/W
Vector No. 0x2F Interrupt Mode bit
14
R/W
Vector No. 0x2E Interrupt Mode bit
13
R/W
Vector No. 0x2D Interrupt Mode bit
12
R/W
Vector No. 0x2C Interrupt Mode bit
11
R/W
Vector No. 0x2B Interrupt Mode bit
10
R/W
Vector No. 0x2A Interrupt Mode bit
9
R/W
Vector No. 0x29 Interrupt Mode bit
8
R/W
Vector No. 0x28 Interrupt Mode bit
7
6
5
4
Vector No. 0x27 Interrupt Mode bit
Vector No. 0x26 Interrupt Mode bit
Vector No. 0x25 Interrupt Mode bit
Reserved
1
1
1
-
3
R/W
Vector No. 0x23 Interrupt Mode bit
2
R/W
Vector No. 0x22 Interrupt Mode bit
1
R/W
Vector No. 0x21 Interrupt Mode bit
0
Reserved
*** Internal Interrupt Mode bit
0: High Level Mode
1: Rising Edge Mode
1
1
1
-
84
R/W
R/W
R/W
-
Default Value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
Interrupt Pending Register (INTPEND)
Offset Address: 0x8002_080C
Bit
R/W
Description
31
R
Vector No. 0x3F Interrupt Pending bit
30
R
Vector No. 0x3E Interrupt Pending bit
29
R
Vector No. 0x3D Interrupt Pending bit
28
R
Vector No. 0x3C Interrupt Pending bit
27
R
Vector No. 0x3B Interrupt Pending bit
26
R
Vector No. 0x3A Interrupt Pending bit
25
R
Vector No. 0x39 Interrupt Pending bit
24
R
Vector No. 0x38 Interrupt Pending bit
23
R
Vector No. 0x37 Interrupt Pending bit
22
R
Vector No. 0x36 Interrupt Pending bit
21
R
Vector No. 0x35 Interrupt Pending bit
20
R
Vector No. 0x34 Interrupt Pending bit
19
R
Vector No. 0x33 Interrupt Pending bit
18
R
Vector No. 0x32 Interrupt Pending bit
17
R
Vector No. 0x31 Interrupt Pending bit
16
R
Vector No. 0x30 Interrupt Pending bit
15
R
Vector No. 0x2F Interrupt Pending bit
14
R
Vector No. 0x2E Interrupt Pending bit
13
R
Vector No. 0x2D Interrupt Pending bit
12
R
Vector No. 0x2C Interrupt Pending bit
11
R
Vector No. 0x2B Interrupt Pending bit
10
R
Vector No. 0x2A Interrupt Pending bit
9
R
Vector No. 0x29 Interrupt Pending bit
8
R
Vector No. 0x28 Interrupt Pending bit
7
6
5
4
R
R
R
R
Vector No. 0x27 Interrupt Pending bit
Vector No. 0x26 Interrupt Pending bit
Vector No. 0x25 Interrupt Pending bit
Vector No. 0x24 Interrupt Pending bit
Default Value
-
3
R
Vector No. 0x23 Interrupt Pending bit
2
R
Vector No. 0x22 Interrupt Pending bit
1
R
Vector No. 0x21 Interrupt Pending bit
0
R
Vector No. 0x20 Interrupt Pending bit
*** Each bit value of Interrupt Pending Register indicates that the corresponding interrupt has
occurred.
This register specifies whether interrupts are pending.
This register is cleared by writing a desired vector value to the Interrupt Pending Clear register.
In general, the register is cleared when the corresponding interrupt is over.
Advanced Digital Chips, Inc.
CONFIDENTIAL
85
CANTUS
Ver 2.04
Interrupt Enable Register (INTEN)
Offset Address: 0x8002_0810
Bit
R/W
Description
31
R/W
Vector No. 0x3F Interrupt Enable bit
30
R/W
Vector No. 0x3E Interrupt Enable bit
29
R/W
Vector No. 0x3D Interrupt Enable bit
28
R/W
Vector No. 0x3C Interrupt Enable bit
27
R/W
Vector No. 0x3B Interrupt Enable bit
26
R/W
Vector No. 0x3A Interrupt Enable bit
25
R/W
Vector No. 0x39 Interrupt Enable bit
24
R/W
Vector No. 0x38 Interrupt Enable bit
23
R/W
Vector No. 0x37 Interrupt Enable bit
22
R/W
Vector No. 0x36 Interrupt Enable bit
21
R/W
Vector No. 0x35 Interrupt Enable bit
20
R/W
Vector No. 0x34 Interrupt Enable bit
19
R/W
Vector No. 0x33 Interrupt Enable bit
18
R/W
Vector No. 0x32 Interrupt Enable bit
17
R/W
Vector No. 0x31 Interrupt Enable bit
16
R/W
Vector No. 0x30 Interrupt Enable bit
15
R/W
Vector No. 0x2F Interrupt Enable bit
14
R/W
Vector No. 0x2E Interrupt Enable bit
13
R/W
Vector No. 0x2D Interrupt Enable bit
12
R/W
Vector No. 0x2C Interrupt Enable bit
11
R/W
Vector No. 0x2B Interrupt Enable bit
10
R/W
Vector No. 0x2A Interrupt Enable bit
9
R/W
Vector No. 0x29 Interrupt Enable bit
8
R/W
Vector No. 0x28 Interrupt Enable bit
7
6
5
4
R/W
R/W
R/W
R/W
3
R/W
2
R/W
1
R/W
0
R/W
*** Interrupt Enable bit
0: Interrupt Disable
1: Interrupt Enable
86
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Vector No. 0x27 Interrupt Enable bit
Vector No. 0x26 Interrupt Enable bit
Vector No. 0x25 Interrupt Enable bit
Vector No. 0x24 Interrupt Enable bit
0
0
0
0
Vector No. 0x23 Interrupt Enable bit
Vector No. 0x22 Interrupt Enable bit
Vector No. 0x21 Interrupt Enable bit
Vector No. 0x20 Interrupt Enable bit
0
0
0
0
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
Interrupt Mask Status Register (INTMASK)
Offset Address: 0x8002_0814
Bit
R/W
Description
31 : 0
R
Interrupt Mask Status Register
*** It is possible to check the state of all Mask bits.
Interrupt Mask Set Register (MASKSET)
Offset Address: 0x8002_0814h
Bit
R/W
Description
31
W
Vector No. 0x3F Interrupt Request Set bit
30
W
Vector No. 0x3E Interrupt Request Set bit
29
W
Vector No. 0x3D Interrupt Request Set bit
28
W
Vector No. 0x3C Interrupt Request Set bit
27
W
Vector No. 0x3B Interrupt Request Set bit
26
W
Vector No. 0x3A Interrupt Request Set bit
25
W
Vector No. 0x39 Interrupt Request Set bit
24
W
Vector No. 0x38 Interrupt Request Set bit
23
W
Vector No. 0x37 Interrupt Request Set bit
22
W
Vector No. 0x36 Interrupt Request Set bit
21
W
Vector No. 0x35 Interrupt Request Set bit
20
W
Vector No. 0x34 Interrupt Request Set bit
19
W
Vector No. 0x33 Interrupt Request Set bit
18
W
Vector No. 0x32 Interrupt Request Set bit
17
W
Vector No. 0x31 Interrupt Request Set bit
16
W
Vector No. 0x30 Interrupt Request Set bit
15
W
Vector No. 0x2F Interrupt Request Set bit
14
W
Vector No. 0x2E Interrupt Request Set bit
13
W
Vector No. 0x2D Interrupt Request Set bit
12
W
Vector No. 0x2C Interrupt Request Set bit
11
W
Vector No. 0x2B Interrupt Request Set bit
10
W
Vector No. 0x2A Interrupt Request Set bit
9
W
Vector No. 0x29 Interrupt Request Set bit
8
W
Vector No. 0x28 Interrupt Request Set bit
7
6
5
4
W
W
W
W
Vector No. 0x27 Interrupt Request Set bit
Vector No. 0x26 Interrupt Request Set bit
Vector No. 0x25 Interrupt Request Set bit
Vector No. 0x24 Interrupt Request Set bit
3
W
Vector No. 0x23 Interrupt Request Set bit
2
W
Vector No. 0x22 Interrupt Request Set bit
1
W
Vector No. 0x21 Interrupt Request Set bit
0
W
Vector No. 0x20 Interrupt Request Set bit
*** Interrupt Request Set bit
0: No effect interrupt Mask.
1: Pending interrupt is allowed to become active (interrupts sent to CPU).
Advanced Digital Chips, Inc.
CONFIDENTIAL
Default Value
0x0000_0000
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
87
CANTUS
Ver 2.04
Interrupt Mask Clear Register (MASKCLR)
Offset Address: 0x8002_0818
Bit
R/W
Description
31
W
Vector No. 0x3F Interrupt Request Clear bit
30
W
Vector No. 0x3E Interrupt Request Clear bit
29
W
Vector No. 0x3D Interrupt Request Clear bit
28
W
Vector No. 0x3C Interrupt Request Clear bit
27
W
Vector No. 0x3B Interrupt Request Clear bit
26
W
Vector No. 0x3A Interrupt Request Clear bit
25
W
Vector No. 0x39 Interrupt Request Clear bit
24
W
Vector No. 0x38 Interrupt Request Clear bit
23
W
Vector No. 0x37 Interrupt Request Clear bit
22
W
Vector No. 0x36 Interrupt Request Clear bit
21
W
Vector No. 0x35 Interrupt Request Clear bit
20
W
Vector No. 0x34 Interrupt Request Clear bit
19
W
Vector No. 0x33 Interrupt Request Clear bit
18
W
Vector No. 0x32 Interrupt Request Clear bit
17
W
Vector No. 0x31 Interrupt Request Clear bit
16
W
Vector No. 0x30 Interrupt Request Clear bit
15
W
Vector No. 0x2f Interrupt Request Clear bit
14
W
Vector No. 0x2E Interrupt Request Clear bit
13
W
Vector No. 0x2D Interrupt Request Clear bit
12
W
Vector No. 0x2C Interrupt Request Clear bit
11
W
Vector No. 0x2B Interrupt Request Clear bit
10
W
Vector No. 0x2A Interrupt Request Clear bit
9
W
Vector No. 0x29 Interrupt Request Clear bit
8
W
Vector No. 0x28 Interrupt Request Clear bit
7
6
5
4
W
W
W
W
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Vector No. 0x27 Interrupt Request Clear bit
Vector No. 0x26 Interrupt Request Clear bit
Vector No. 0x25 Interrupt Request Clear bit
Vector No. 0x24 Interrupt Request Clear bit
0
0
0
0
3
W
Vector No. 0x23 Interrupt Request Clear bit
2
W
Vector No. 0x22 Interrupt Request Clear bit
1
W
Vector No. 0x21 Interrupt Request Clear bit
0
W
Vector No. 0x20 Interrupt Request Clear bit
*** Interrupt Request Clear bit
0: No effect Interrupt Mask.
1: Pending interrupt is masked from becoming active (interrupts not sent to CPU).
88
CONFIDENTIAL
0
0
0
0
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
Programmable Interrupt Priority Enable Register (PPENR)
Offset Address: 0x8002_081C
Bit
R/W
Description
31 : 1
R
Reserved
0
R/W
Programmable Priority Enable bit
0 : Programmable Priority Disable
1 : Programmable Priority Enable
Interrupt Priority Vector 0 Register (IPVR0)
Offset Address: 0x8002_0820
Bit
R/W
Description
31 : 29
R
Reserved
28 : 24
R/W
Vector No. 0x23 Interrupt Priority
23 : 21
R
Reserved
20 : 16
R/W
Vector No. 0x22 Interrupt Priority
Default Value
0
Default Value
0x03
0x02
15 : 13
12 : 8
R
R/W
Reserved
Vector No. 0x21 Interrupt Priority
0x01
7:5
4:0
R
RW
Reserved
Vector No. 0x20 Interrupt Priority
0x00
Interrupt Priority Vector 1 Register (IPVR1)
Offset Address: 0x8002_0824
Bit
R/W
Description
31 : 29
R
Reserved
28 : 24
R/W
Vector No. 0x27 Interrupt Priority
23 : 21
R
Reserved
20 : 16
R/W
Vector No. 0x26 Interrupt Priority
Default Value
0x07
0x06
15 : 13
12 : 8
R
R/W
Reserved
Vector No. 0x25 Interrupt Priority
0x05
7:5
4:0
R
R/W
Reserved
Vector No. 0x24 Interrupt Priority
0x04
Advanced Digital Chips, Inc.
CONFIDENTIAL
89
CANTUS
Ver 2.04
Interrupt Priority Vector 2 Register (IPVR2)
Offset Address: 0x8002_0828
Bit
R/W
Description
31 : 29
R
Reserved
28 : 24
R/W
Vector No. 0x2B Interrupt Priority
23 : 21
R
Reserved
20 : 16
R/W
Vector No. 0x2A Interrupt Priority
15 : 13
12 : 8
R
R/W
Reserved
Vector No. 0x29 Interrupt Priority
0x09
7:5
4:0
R
R/W
Reserved
Vector No. 0x28 Interrupt Priority
0x08
Interrupt Priority Vector 3 Register (IPVR3)
Offset Address: 0x8002_082C
Bit
R/W
Description
31 : 29
R
Reserved
28 : 24
R/W
Vector No. 0x2F Interrupt Priority
23 : 21
R
Reserved
20 : 16
R/W
Vector No. 0x2E Interrupt Priority
Default Value
0x0F
0x0E
15 : 13
12 : 8
R
R/W
Reserved
Vector No. 0x2D Interrupt Priority
0x0D
7:5
4:0
R
R/W
Reserved
Vector No. 0x2C Interrupt Priority
0x0C
Interrupt Priority Vector 4 Register (IPVR4)
Offset Address: 0x8002_0830
Bit
R/W
Description
31 : 29
R
Reserved
28 : 24
R/W
Vector No. 0x33 Interrupt Priority
23 : 21
R
Reserved
20 : 16
R/W
Vector No. 0x32 Interrupt Priority
90
Default Value
0x0B
0x0A
Default Value
0x13
0x12
15 : 13
12 : 8
R
R/W
Reserved
Vector No. 0x31 Interrupt Priority
0x11
7:5
4:0
R
R/W
Reserved
Vector No. 0x30 Interrupt Priority
0x10
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
Interrupt Priority Vector 5 Register (IPVR5)
Offset Address: 0x8002_0834
Bit
R/W
Description
31 : 29
R
Reserved
28 : 24
R/W
Vector No. 0x37 Interrupt Priority
23 : 21
R
Reserved
20 : 16
R/W
Vector No. 0x36 Interrupt Priority
Default Value
0x17
0x16
15 : 13
12 : 8
R
R/W
Reserved
Vector No. 0x35 Interrupt Priority
0x15
7:5
4:0
R
R/W
Reserved
Vector No. 0x34 Interrupt Priority
0x14
Interrupt Priority Vector 6 Register (IPVR6)
Offset Address: 0x8002_0838
Bit
R/W
Description
31 : 29
R
Reserved
28 : 24
R/W
Vector No. 0x3B Interrupt Priority
23 : 21
R
Reserved
20 : 16
R/W
Vector No. 0x3A Interrupt Priority
Default Value
0x1B
0x1A
15 : 13
12 : 8
R
R/W
Reserved
Vector No. 0x39 Interrupt Priority
0x19
7:5
4:0
R
R/W
Reserved
Vector No. 0x38 Interrupt Priority
0x18
Interrupt Priority Vector 7 Register (IPVR7)
Offset Address: 0x8002_083C
Bit
R/W
Description
31 : 29
R
Reserved
28 : 24
R/W
Vector No. 0x3F Interrupt Priority
23 : 21
R
Reserved
20 : 16
R/W
Vector No. 0x3E Interrupt Priority
Default Value
0x1F
0x1E
15 : 13
12 : 8
R
R/W
Reserved
Vector No. 0x3D Interrupt Priority
0x1D
7:5
4:0
R
R/W
Reserved
Vector No. 0x3C Interrupt Priority
0x1C
Advanced Digital Chips, Inc.
CONFIDENTIAL
91
CANTUS
Ver 2.04
10 TIMERS
CANTUS has 8 built-in channels for 32-bit timer/counter with Timer/Counter, Capture, PWM, and
Output Compare functions.
Key Features
- 15-bit Pre-scale
- 32-bit Timer/Counter
- 32-bit Capture
- 32-bit PWM
- 32-bit Output Compare
92
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
10.1 15-bit Pre-scaler with clock source selection
Pre-scaler selects system clock and external clocks received via the external clock pin, through
CLKSEL bit, generates 1/2 ~ 1/32768 times divided clocks through 15-bit pre-scaler, and transfers
it to Timer/Counter. The timer/counter selects a divided clock through the pre-scaler to activate 32bit counter.
When an accurate phase of the clock divided by the pre-scaler is needed, the pre-scaler counter
should be reset through CNTCLR bit in TPxCON register.
System Clock
15-bit Timer/Counter Pre-scaler
External Clock
Sel Clock / 32768
Sel Clock / 8192
Sel Clock / 2048
Sel Clock / 512
Sel Clock / 128
Sel Clock / 32
Sel Clock / 8
Sel Clock / 2
Timer Clock Source Select
Pre-scaler Counter Reset
Timer/Counter Clock Select
3
Timer/Counter Clock
Figure 10-1 Pre-scaler Block Diagram
Advanced Digital Chips, Inc.
CONFIDENTIAL
93
CANTUS
Ver 2.04
10.2 Timer/Counter
For every clock divided by the pre-scaler, Timer/Counter value increases by “1” from the initial
value of 0x0. When the counter value reaches the timer counter register value set by the user,
timer interrupt is generated.
Timer Counter
0
1
TCNTR
-1
0
1
TCNTR
-1
0
1
TCNTR
-1
0
Timer Interrupt
Figure 10-2 Timer Operation
Timer period is determined by the selected clock frequency, pre-scaler factor and the timer
counter.
1
1

 TMCNT  sec 
Clock Source Frequency Pr e  scaler Factor
1
1
Timer Period 

 TMCNT  1 sec 
Clock Source Frequency Pr e  scaler Factor
Timer Period 
TMCNT  3
TMCNT  3
Timer Period Example:
- Clock Source Frequency : 12MHz System Clock
- Pre-scaler Factor
: 1 / 1024
- Timer Counter Value (TMCNT) : 1000
=> 1/12MHz X 1024 X 1000 = 85.333msec = 11.718Hz
Registers required to be set to operate Timer/Counter are as follows:
- TPxCON: Determines the clock input to the pre-scaler, and clears the pre-scaler if
necessary.
- TMxCON‟s TMOD: Sets Timer/Counter mode.
- TMxCON‟s WAVE: Determines whether to or not to output the clock generated at
Timer/Counter period.
- TMxCON‟s PFSEL: Determines the clock to be used by Timer/Counter.
- TMxCON‟s TMEN: Enables Timer Counter.
- TMxCNT: Determines the maximum counter value for Timer/Counter.
Timer/Counter should operate according to the sequence of following settings:
- TPxCON setting
- TMxCNT setting
- TMxCTRL setting
- TPxCTRL‟s CNTCLR bit setting, if needed
94
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
10.3 Pulse Width Modulation (PWM)
PWM is a controller to output pulse signals of programmable duty and period.
It operates through the clock set by the pre-scaler and outputs the waveform in the form set by
the user by repeating the count at the period of PWM Period register value.
Output pulse of PWM is made into output waveform as the level is reversed whenever the 32-bit
counter value reaches PWM Duty and PWM Period register values. Output count of PWM is
determined by PWM Pulse Number register and when it is reached, PWM interrupt is generated.
However, even though PWM interrupt is generated, PWM output is kept being generated if there is
no other setting. Therefore, in order to stop PWM pulse, PWM should be disabled by Timer
interrupt.
1
1

 TMCNT  sec 
Clock Source Frequency Pr e  scaler Factor
1
1
PWM Pulse Period 

 TMCNT  1 sec 
Clock Source Frequency Pr e  scaler Factor
TMCNT  3
PWM Pulse Period 
TMCNT  3
PWM Period Example:
- Clock Source Frequency: 12MHz System Clock
- Pre-scaler Factor: 1 / 1024
- PWM Period Value (TMxCNT): 10
- PWM Duty Value: 6
=> 1/12MHz X 1024 X 10 = 0.853msec = 1.171KHz
Registers required to be set to operate PWM are as follows:
- TPxCTRL: Determines the clock input to the pre-scaler, and clears the pre-scaler if
necessary.
- TMxCTRL‟s TMOD: Sets PWM mode.
- TMxCTRL‟s PWML: Determines the start level of PWM output.
- TMxCTRL‟s PFSEL: Determines the clock to be used by PWM.
- TMxCTRL‟s TMEN: Enables PWM.
- TMxCNT: Determines PWM period.
- TMxDUT: Determines PWM duty.
- TMxPUL: Determines PWM pulse count. When PWM pulse count reaches this register
value, Timer Interrupt is generated. But, PWM pulse is kept being generated without
stopping.
PWM operates according to the sequence of following settings:
- TPxCTRL setting
- TMxCNT setting
- TMxDUT setting
- TMxPUL setting
- TPxCTRL‟s CNTCLR setting, if needed
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PWM Period Value
PWM Duty Value
PWM Pulse Number Value
Internal Counter
0
= 0x09h
= 0x06h
= 0x01h
1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9
PWM Output
Period
Duty
Pulse Number
PWM Interrupt
Figure 10-3 PWM Operation
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10.4 Capture
Capture is a function to measure external input based on the clock set by the pre-scaler.
There are 5 types of pulses to be measured such as Low/High Pulse, Only Low Pulse, Only High
Pulse, Falling to Falling Period, and Rising to Rising Period.
When Timer is enabled as Capture mode, the first captured value should be ignored as it is an
in-between value made as the signal changes.
Low/High Pulse Capture Mode
Capture Input
Capture Counter
Capture Interrupt
Capture Value
High Pulse Capture Mode
Low Pulse Capture Mode
Capture Input
Capture Input
Capture Counter
Capture Counter
Capture Interrupt
Capture Interrupt
Capture Value
Capture Value
Falling to Falling Capture Mode
Rising to Rising Capture Mode
Capture Input
Capture Input
Capture Counter
Capture Counter
Capture Interrupt
Capture Interrupt
Capture Value
Capture Value
Figure 10-4 Capture Mode Operation
Capture period is measured as follows:
Capture Signal Width Time 
1
1

 OCA  1 sec 
Clock Source Frequency Pr e  scaler Factor
Capture Time Example:
- Clock Source Frequency : 12MHz System Clock
- Pre-scaler Factor
: 1 / 1024
- Capture Value
:9
=> 1/12MHz X 1024 X 10 = 0.853msec
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Registers required to be set to operate Timer as Capture mode are as follows:
- TPxCTRL: Determines the clock input to the pre-scaler, and clears the pre-scaler if
necessary.
- TMxCTRL‟s TMOD: Sets Capture mode.
- TMxCTRL‟s CAPMOD: Determines Capture Pulse type.
- TMxCTRL‟s PFSEL: Determines the clock to be used for Capture.
- TMxCTRL‟s TMEN : Enable Capture mode.
Capture mode should operate according to the sequence of the following settings:
- TPxCTRL setting
- TMxCTRL setting
- TPxCTRL‟s CNTCLR setting, if needed
- Check Capture period, by reading TMxDUT register.
- Check Overflow state, by reading TMxCTRL‟s OVST.
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10.5 Output Compare Mode
Timer Channels 2 and 3 have 2 Output Compare registers, so that Timer can perform two Output
Compare operations before its counter value overflows.
Counter Value
OCA
Value
OCB
Value
Timer
Counter
Value
Timer Interrupt
Output Compare
A Interrupt
Output Compare
B Interrupt
Figure 10-5 Timing Diagram of Output Compare Operation
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10.6 Timer Control Registers
Timer Pre-scale Control Registers ( TPxCTRL )
Address: 0x8002_1000 / 0x8002_1020 / 0x8002_1040 / 0x8002_1060 /
0x8002_1080 / 0x8002_10A0 / 0x8002_10C0 / 0x8002_10E0
Bit
R/W
Description
31 : 2
R
Reserved
1
R/W
CNTCLR : Pre-scale Counter and Timer Counter
Reset
When this bit is “1,” the Timer Pre-scale and Counter
will be reset.
0
R/W
CLKSEL : Pre-scale Clock Selection
0 : System clock
1 : CAPx
*** CAPx is assigned to each Timer channel.
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Default Value
0
0
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Timer Control Registers ( TMxCTRL)
Address: 0x8002_1004 / 0x8002_1024 / 0x8002_1044 / 0x8002_1064 /
0x8002_1084 / 0x8002_10A4 / 0x8002_10C4 / 0x8002_10E4
Bit
R/W
Description
31 : 16
R
Reserved
15 : 14
R/W
TMOD : Timer/Counter Mode
00 : Timer
01 : PWM
1x : Capture
13
R/W
OCEN : Output Compare Mode Enable bit for channel
2 and channel 3
0 : Disable
1 : Enable
12
R
Reserved
11
Default Value
00
0
0
R/W
OVST : Capture Overflow Status bit
0
Read시 Overflow status bit가 clear된다.
10 : 8
R/W
CAPMOD : Capture Mode Selection
000
00x : Low/High Pulse Capture mode
010 : Low Pulse Capture mode
011 : High Pulse Capture mode
10x : Failing to Failing Period Capture mode
11x : Rising to Rising Period Capture mode
7
R
Reserved
6
R/W
PWMO : PWM Output One Period Generation
0
0 : Disable
1 : Enable
5
R/W
PWML : PWM Output Start Level
0
0 : Start Level is Low
1 : Start Level is High
4
R
Reserved
3:1
R/W
PFSEL : Pre-scale Factor Selection
111
000 : 1/2
001 : 1/8
010 : 1/32
011 : 1/128
100 : 1/512
101 : 1/2048
110 : 1/8192
111 : 1/32768
0
R/W
TMEN : Timer/Counter or PWM Enable
0
0 : Disable
1 : Enable
*** PWM Output One Period Generation: Bit that generates only one period, during PWM mode
operation. After one period is generated, PWM is automatically disabled.
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Timer Counter / PWM Period Registers ( TMxCNT )
Address: 0x8002_1008 / 0x8002_1028 / 0x8002_1048 / 0x8002_1068 /
0x8002_1088 / 0x8002_10A8 / 0x8002_10C8 / 0x8002_10E8
Bit
R/W
Description
31 : 0
R/W
(Timer mode)
- Write : Timer Counter Value
- Read : Current Up-counter Value
Default Value
0xFFFF_FFFF
(PWM mode)
- Read/Write : PWM Period Value
Capture Counter Registers / PWM Duty Registers / Output Compare A Registers ( TMxDUT )
Address: 0x8002_100C / 0x8002_102C / 0x8002_104C / 0x8002_106C /
0x8002_108C / 0x8002_10AC / 0x8002_10CC / 0x8002_10EC
Bit
R/W
Description
Default Value
31 : 0
R/W
(Capture mode)
0xFFFF_FFFF
- Read : Result value of counting at the sampling
period
(PWM mode)
- Read/Write : PWM Duty Value
(Output Compare Mode)
- Read/Write : Output Compare A Value
- Supported in channel2 and channel3
*** PWM Duty: First Halt Duty of PWM Pulse
PWM Pulse Count Registers / Output Compare B Registers ( TMxPUL )
Address: 0x8002_1010 / 0x8002_1030 / 0x8002_1050 / 0x8002_1070 /
0x8002_1090 / 0x8002_10B0 / 0x8002_10D0 / 0x8002_10F0
Bit
R/W
Description
31 : 0
R/W
(PWM mode)
- Read/Write : PWM Pulse Number Value
Default Value
0xFFFF_FFFF
(Output Compare Mode)
- Read/Write : Output Compare B Value
- Supported in channel2 and channel3
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11 SPI (SERIAL PERIPHERAL INTERFACE)
SPI built in CANTUS exchanges data with external devices or other CPUs via synchronous serial
buses. As being compatible with SPIs of Motorola M68HC11, M68HC05 and MC68HC16 series,
this SPI is capable of performing full duplex 3-wire transfer or half duplex 2-wire transfer.
For high-speed SPI transfer, CANTUS SPI has 8-byte built-in FIFO so that it can perform Mbps
rate transfer without overloading CPU.
CANTUS SPI supports both Master and Slave modes:
Key Features
- Full duplex mode. Three-wired synchronous Transfer
- Master or Slave Operation
- Programmable clock polarity and phase
- End of transmission interrupt flag
- Write collision flag protection
- Master-master mode fault protection capability
- 8Bytes FIFO
As clock polarity and two clock protocols are selected at the clock control circuit, SPI becomes
compatible with most of synchronous serial peripherals. When SPI is set as Master mode, 256
various serial clocks can be created by software.
SPI can perform data transfer and data reception simultaneously. Information sampling and
shifting at two serial data lines are synchronized by the serial clock line. Selection of individual
slave SPI devices can be made through Slave Select line. Slave devices that are not selected do
not affect SPI bus operation. In Master SPI device, Slave Select line can be used for indicating
multiple master bus collision.
Error detection circuit is used for connecting processes. If data is written on Serial Shifter register
during transfer operation, Write Collision occurs. Upon detection of multiple Master mode failures,
output driver is disabled when more than one CPU attempts to become the bus master.
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11.1 SPI Registers Summery
SPI Control Register (SPICTRL): Contains parameters related to SPI setting. This register is
readable/writable at all times.
SPI Baud Register (SPIBR): Sets baud rate to generate SCK.
SPI Status Register (SPISTAT): Contains SPI status information. SPI is capable of only setting
the value of these register bits. CPU can check the current SPI status by reading this status register.
SPI Data Register (SPIDATA): This register is used for transmitting and receiving data to/from the
serial bus. It consists of TX data register and RX buffer register. Data is written directly on TX data
register. After a byte or a word is transmitted, SPIF status bits of Master and Slave devices are set.
SPIBR
Counter
SPICTRL
sck_in
Clock
Logic
Control Logic
sck_out
SCK
sck_oen
APB BUS
ssx_in
ssx_out
SPISTAT
nSS
ssx_oen
CLK
32-BIT RX Shift Register
mosi_in
master input
mosi_out
master output
mosi_oen
MOSI
8/16/32-BIT TX Shift Register
SPIDATA
(8Bytes)
miso_in
miso_out
slave input
slave output
MISO
miso_oen
Ouput Control Logic
nSSCTRL
SPIINT
Figure 11-1 SPI Block Diagram
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11.2 SPI Pins
SPI has four both-way pins such as MISO, MOSI, SCK and nSS. WOMP bit in SPI Control
register determines Open Drain output or CMOS output for the output operation of each pin.
MSTR bit in SPI Control register determines Master or Slave operation, according to which pin
operation is determined.
Pin Name
Master in, slave out(MISO)
Master out, slave in (MOSI)
serial clock(SCK)
Slave select(nSS)
Table 11-1 SPI Pin Functions
Mode
Function
Master
Provides serial data input to the SPI
Slave
Provides serial data output from the SPI
Master
Provides serial output from the SPI
Slave
Provides serial input to the SPI
Master
Provides clock output from the SPI
Slave
Provides clock input to the SPI
Master
Output: Selects slave devices
Slave
Input: chip select for SPI
11.3 SPI Operating Modes
SPI operates either in Master or in Slave mode. Master mode is used when CPU is in charge of
data transfer, which Slave mode is used when serial transfer is made by an external device to CPU.
Whether SPI is to operate in Master mode or in Slave mode is determined by MSTR bit in SPI
Control register.
Master Mode
When MSTR bit in SPICTRL is set, Master mode operation is selected. In Master mode, SPI can
initialize serial transfer but does not respond to the transfer initialized from the outside.
In order to use SPI in Master mode, the following process is required:
In Master mode, MISO pin is used for serial data input and MOSI pin for serial data output.
Depending on specific applications, one or both may be needed.
Assign the values of BAUD, CPHA, CPOL, SIZE, MSBF, and WOMP to SPICTRL register. Set
MSTR bit for Master operation. Set SPIEN bit to enable SPI.
Enable Slave devices.
Start writing proper data on SPIDATA register to start transfer.
When transfer is completed, SPI sets SPIF flag of SPISTAT register by hardware. When SPIF is
applied, an interrupt request is generated. While SPIF is set, SPI reads SPISTAT register and when
it does reading or writing data from or on SPIDATA register, SPIF flag is automatically cleared.
Data transfer is synchronized to the serial clock (SCK) generated inside. CPHA and CPOL bits of
SPICTRL register control phase and polarity of the clock. SCK edge at which CPU sends data from
MOSI pin and SCK edge which latches data coming through MISO pin are determined by CPHA
and CPOL.
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Slave Mode
When MSTR bit in SPICTRL register is set to “0,” SPI operates in Slave mode. In Slave mode, SPI
cannot reset serial transfer but the transfer is initialized by an external bus master. Slave mode is
used in particular by multiple master SPI bus, as only one device can be the bus master within a
given time.
In Slave mode, MISO pin is used for serial data output and MOSI pin for serial data input.
Depending on specific application, one or both pins are required. SCK is input serial clock. When
nSS is activated, it is selected as Slave.
Write data on the data register for data transfer. In Slave mode, SCK, MOSI and nSS are input
while MISO is output.
Write values on SPI Control register for setting CPHA, CPOL, SIZE, MSBF, and WOMP. Select
Slave operation by clearing MSTR bit. Enable SPI by setting SPIEN. For Slave devices, BAUD
value does not affect SPI operation.
When SPIEN is set and MSTR is cleared, “Low” status of nSSpin input initializes Slave mode
operation. nSS pin is used only for input.
After sending a data byte or word, SPI sets SPIF flag. When SPIE bit in Control register has been
set, an interrupt request is generated when SPIF is activated.
Data transfer is synchronized to SCK generated from the outside. CPHA and CPOL latches data
that Slave CPU receives through MOSI pin or decides the clock edge for data that is sent through
MISO pin.
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11.4 SCK Phase and Polarity Control
Two bits of Control register determine phase and polarity of SCK. Clock Polarity bit, CPOL,
selects polarity of the clock (High or Low). Clock Phase bit, CPHA, selects one of two transfer types
that affect transfer timing. Phase and polarity of the clock should be the same for both Master and
Slave. In some cases, phase and polarity change during transfer, so that Master device may
exchange data with Slave device on different conditions. Such flexibility of SPI enables direct
connection with almost all synchronous serial peripherals.
nSS
SCK
(CPOL=0, CPHA=0)
SCK
(CPOL=0, CPHA=1)
SCK
(CPOL=1, CPHA=0)
SCK
(CPOL=1, CPHA=1)
MSB 1
2
3
4
5
6
LSB
MSB if CPHA=0
Internal strobe for data capture (for all modes)
Figure 11-2 SCK Phase and Polarity
11.5 Data Transfer Timing
Figure 11-3 illustrates the timing of 1-byte data transfer when CPHA=‟0‟ and in MSB start mode.
There are two types of SCK waveforms. One is when CPOL is „0‟ and the other is when CPOL is
„1.‟ This timing diagram is considered either as Master timing diagram or Slave timing diagram as
Master and Slave are directly connected through SCK, MISO and MOSI pins. MISO signal is output
from Slave, while MOSI signal is output from Master. nSS signal is a signal to select the chip to
Slave.
When Master initializes data transfer by writing data on SPDR, while Slave initializes data
transfer when nSS is on falling edge. SCK signal remains inactive until half-period of the first SCK
cycle. SPIF bit that indicates the completion of transfer is set at the end of the 8th SCK cycle.
When CPHA=‟0,‟ nSS is low but within a short time after 1 byte transfer, it becomes inactive (High).
If Slave writes a value on the data register when nSS is low, write collision error occurs.
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SCK CYCLE
1
2
3
4
5
6
7
8
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
(Master Out)
MISO
(Master In)
MSB
MSB
6
5
4
3
2
1
LSB
6
5
4
3
2
1
LSB
nSS
(To Slave)
Figure 11-3 Transfer Timing when CPHA = „0‟
The following figure shows the transfer timing when CPHA=‟1.‟ SCK becomes inactive at the half
period of the last 8th cycle. SPIF bit is set at the end of the 8th SCK cycle. As the last edge arises
in the middle period of the 8th SCK cycle, Slave samples the last data in the middle of the 8th SCK
cycle and then finishes reception. nSS keeps low for a certain period of time after completing 1 byte
transfer. Therefore, if CPU continuously transfers data by polling transfer status, it keeps low state.
SCK CYCLE
1
2
3
4
5
6
7
8
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MSB
6
5
4
3
2
1
MISO
MSB
6
5
4
3
2
1
LSB
LSB
nSS
Figure 11-4 Transfer Timing when CPHA = „1‟
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11.6 SPI Serial Clock Baud Rate
For SPI baud rate, values from 1 to 255 can be stored in SPBR register.
In Slave mode, SPI receives SCK provided by an external SPI Master. Therefore, SPI baud rate
is not affected by SPIBRR register setting. However, the maximum rate operable in Slave mode is
affected by system clock.
SCK Baud Rate 
f PCLK
2  ( SPIBR  1)
or
f PCLK
SPIBR 

2  SCK Baud Rate
1
11.7 Open-Drain Output for Wired-OR
If not for multiple SPI Masters, SPI bus output does not need to support Open-Drain. When
Open-Drain output is needed, WOMP bit in SPICTRL register should be set to provide Open-Drain
output. When SPI bus is set as Open-Drain, each output line must be attached with pull-up
resistance.
11.8 Transfer Size and Direction
SPISIZE bit in SPICTRL register selects the transfer size (8/16/32bits). MSBF bit in SPICTRL
register sets the start of data transfer either from MSB (MSBF=1) or LSB.
11.9 Write Collision
When it is attempted to write data on SPIDATA register while data transfer is in progress, write
collision occurs.
11.10 MODE Fault
If mode fault error occurs when SPI system is set as Master and nSS signal input line is asserted,
MODF bit in SPISTAT is set. Only Master device can generate MODF when another SPI device is
to become master.
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11.11 Interrupt
SPIF Interrupt
Occurs when both data stored in FIFO and TX Shift register are emptied, indicating that SPI
transfer is completed. This interrupt verifies that SPI transfer is completed.
MODF Interrupt
Occurs when a mode fault occurs. The mode fault refers to a situation in which two or more
masters transfer data.
nSS Interrupt
Occurs when there is a change in the detected nSS port signal.
TX_FIFO_FULL, TX_FIFO_EMPTY, RX_FIFO_FULL, RX_FIFO_EMPTY
- TX_FIFO_FULL: Indicates that internal FIFO of 8Byte is full. If more data is added to TX
FIFO, wrong data transfer occurs.
- TX_FIFO_EMPTY: Indicates that data that filled TX FIFO has all been transferred.
However, as TX Shift register has not yet been emptied, it does not mean that SPI transfer has
been completed.
- RX_FIFO_FULL: Indicates that RX_FIFO is full.
- RX_FIFO_EMPTY: Indicates that RX_FIFO is emptied.
SSX
SCK
F
E
F
E
F
E
F
MOSI
1Byte TX FIFO Write
1Byte TX FIFO Write
1Byte TX FIFO Write
1Byte TX FIFO Write
Figure 11-5 1-Byte Transfer vs. Status and Interrupt
SSX
SCK
E F
E F
E F
MOSI
nByte TX FIFO Write
nByte TX FIFO Write
nByte TX FIFO Write
Figure 11-6 n-Bytes Transfer vs. Status and Interrupt
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11.12 SPI Control Registers
SPI Control Register (SPICTRL)
Address: 0x8002_1C00
Bit
R/W
Description
31 : 8
R
Reserved
7
R/W
SPIEN : SPI Enable
0 : SPI is disabled.
1 : SPI is enabled
6
R/W
WOMP : Wired-OR Mode for SPI Pins
0 : Outputs have normal CMOS drivers.
1 : Open-drain drivers
5
R/W
MSTR : Master/Slave Mode Select
0 : Slave operation
1 : Master operation
4
R/W
CPOL : Clock Polarity
0 : The inactive state value of SCK is logic level zero
1 : The inactive state value of SCK is logic level one.
3
R/W
CPHA : Clock Phase
0 : Data captured on the leading edge of SCK and
changed on the trailing edge of SCK.
1 : Data is changed on the leading edge of SCK and
captured on the trailing edge of SCK.
2
R/W
MSBF : Most Significant Bit First
0 : Serial data transfer starts with LSB.
1 : Serial data transfer starts with MSB.
1:0
R/W
SPISIZE : Transfer Data Size
00 : 8-bit data transfer.
01 : 16-bit data transfer.
10 : 32-bit data transfer.
SPI Baud Rate Register (SPIBR)
Address: 0x8002_1C04
Bit
R/W
Description
31 : 8
R
Reserved.
7:0
R/W
Serial Clock Baud Rate
SCK 
Default Value
0
0
0
0
0
0
0
Default Value
0xFF
f PCLK
2  ( SPIBR  1)
Master Mode SCK ≤ System Clock / 2
Slave Mode SCK ≤ System Clock / 4
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SPI Status Register (SPISTAT)
Address: 0x8002_1C08
Bit
R/W
Description
15 : 8
R
Reserved
7
R
SPIF : SPI Finished Flag
0 : SPI is not finished.
1 : SPI is finished.
6
R
WCOL : Write Collision
0 : No attempt to write to the SPDR happened
during the serial transfer.
1 : Write collision occurred.
5
R
MODF : Mode Fault Flag
0 : Normal operation
1 : Another SPI node requested to become the
network SPI master while the SPI was enabled in
master mode
4
R
nSS : Slave Select Flag
0 : Current Value of nSS port is low
1 : Current Value of nSS port is high
3
R
STXF : TX FIFO Full Status bit
0 : FIFO_TX is not full
1 : FIFO_TX is full
2
R
STXE : TX FIFO Empty Status bit
0 : FIFO_TX is not empty
1 : FIFO_TX is empty
1
R
SRXF : RX FIFO Full Status bit
0 : FIFO_RX is not full
1 : FIFO_RX is full
0
R
SRXE : RX FIFO Empty Status bit
0 : FIFO_RX is not empty
1 : FIFO_RX is empty
SPI Data Register (SPIDATA)
Address: 0x8002_1C0C
Bit
R/W
Description
31 :0
R/W
SPI Data
At 32-bit transfer mode
- MSB of Data is SPDR[31]
At 16-bit transfer mode
- MSB of Data is SPDR[15]
At 8-bit transfer mode
- MSB of Data is SPDR[7]
Default Value
0
0
0
0
0
0
0
0
Default Value
0x0000_0000
LSB of Data (received or transmit) is SPDR[0] in any
transfer mode
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SPI nSS Control Register (nSSCTRL)
Address: 0x8002_1C10
Bit
R/W
Description
31 : 1
R
Reserved
0
RW
nSSCON : nSS Output Level
SPI Interrupt Mask Register (SPIINT)
Address: 0x8002_1C14
Bit
R/W
Description
31 : 8
R
Reserved
7
RW
SPIFE : SPIF Interrupt en/disable
SPIF Interrupt occurs when transfer has completed.
0 : SPIF interrupt is disabled
1 : SPIF is enabled
6
RW
MODFE : MODFI Interrupt en/disable
MODFI Interrupt occurs when two more master use
data line.
0 : MODFI interrupt is disabled
1 : MODFI is enabled
5
R
Reserved
4
RW
nSSEN : nSS Interrupt en/disable
nSS Interrupt occurs when nSS signal has changed.
0 : nSS Interrupt is disabled
1 : nSS Interrupt is enabled
3
RW
STXFE : FIFO_TX_FULL Interrupt en/disable
FIFO_TX_FULL Interrupt occurs when FIFO_TX is
full
0 : FIFO_TX_FULL Interrupt is disabled
1 : FIFO_TX_FULL Interrupt is enabled
2
RW
STXEE : FIFO_TX_EMPTY Interrupt en/disable
FIFO_TX_EMPTY Interrupt occurs when FIFO_TX is
empty
0 : FIFO_TX_EMPTY Interrupt is disabled
1 : FIFO_TX_EMPTY Interrupt is enabled
1
RW
SRXFE : FIFO_RX_FULL Interrupt en/disable
FIFO_RX_FULL Interrupt occurs when FIFO_RX is
full
0 : FIFO_RX_FULL Interrupt is disabled
1 : FIFO_RX_FULL Interrupt is enabled
0
RW
SRXEE : FIFO_RX_EMPTY Interrupt en/disable
FIFO_RX_EMPTY Interrupt occurs when FIFO_RX is
empty
0 : FIFO_RX_EMPTY Interrupt is disabled
1 : FIFO_RX_EMPTY Interrupt is enabled
Advanced Digital Chips, Inc.
CONFIDENTIAL
Default Value
1
Default Value
0
0
0
0
0
0
0
0
113
CANTUS
Ver 2.04
12 TWI (TWO WIRED INTERFACE)
For interface with universal TWI bus, CANTUS has a built-in TWI controller. TWI has SCL and
SDA signals.
Key Features
- Master transmitter mode
- Master receive mode
- Slave transmitter mode
- Slave receive mode
- Software programmable clock frequency
- Software programmable acknowledge bit
- Interrupt driven data-transfers
- Start/Stop/Repeated Start/Acknowledge generation
- Multi master operation
SDA
SCL
TWIBR0/TWIBR1
START/STOP Condition
Generaion
APB BUS
TWICTRL
Arbitration and
START/STOP Detection
TWISTAT
Address Compare
TWIADR
8-bit Address Shifter
TWIDATA
8-bit Shifter
Figure 12-1 TWI Block Diagram
114
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
12.1 DATA TRANSFER FORMAT
On SDA line, all data length is 8bits. The number of bytes that can be transmitted every transfer
is not limited. The first byte next to Start condition is used as address field. When TWI-bus operates
in Master mode, the address filed is transferred by Master. All bytes are accompanied by ACK bit.
Transfer always starts with data and MSB bit of address.
Write Mode Format with 7-bit Addresses
S
Slave Address 7bits
R/W A
"0"
(Write)
DATA(1Byte)
A P
Data Transferred
(Data + Acknowledge)
Read Mode Format with 7-bit Addresses
S
Slave Address 7bits
R/W A
"1"
(Read)
DATA(1Byte)
A P
Data Transferred
(Data + Acknowledge)
NOTES:
1. S:Start, rS:Repeat Start, P:Stop, A:Acknoledge
2.
:From Master to Slave,
from Slave to Master
Figure 12-2 TWI-Bus Interface Data Format
12.2 START AND STOP CONDITIONS
Start condition can transfer 1 byte data, and Stop condition completes data transfer. For Start
condition, SDA line is transited from high to low when SCL is high and Stop condition, SDA line is
transited from low to high when SCL is high. When Start condition occurs, TWI bus becomes busy
but when Stop condition occurs, TWI bus becomes free.
SDA
MSB
1
SCL
Acknowledgement Signal
from Receiver
7
2
8
Start
Acknowledgement Signal
from Receiver
9
Stop
ACK
Byte Complete, Interrupt within
Receiver
Clock Line Held Low While
Interrupts are Serviced
Figure 12-3 Data Transfer on the TWI-Bus
Advanced Digital Chips, Inc.
CONFIDENTIAL
115
CANTUS
Ver 2.04
12.3 ACK SIGNAL TRANSMISSION
To complete one byte transfer, Receiver should transmit ACK bit to Transmitter. ACK pulse
should be generated from the 9th clock of SCL line. Therefore, to transfer one byte data, total 9
clocks are needed. Master should generate clock pulse for ACK bit transmission.
Upon receiving ACK clock pulse, Transmitter should release SDA line in order to make the SDA
“High.” Also, Receiver should keep SDA line as “Low” at the time of sending ACK pulse, so that
th
SDA can be “Low” in the 9 “High” section of SCL.
ACK bit can be selected by software either as ACK or NOACK by TXACK bit setting of the
control register.
Clock to Output
Data Output by
Transmitter
Data Output by
Receiver
SCL from
Master
Start
1
2
7
Start
Condition
8
9
Clock Pulse for
Acknowledgement
Figure 12-4 Acknowledgement of TWI
12.4 READ-WRITE OPERATION
After transmitting data in Tx operation mode, TWI-bus interface should wait until data is ready in
Data Shifter register. Until data is written, SCL is kept “Low.” It is released after new data is written
in Data Shifter register.
When interrupts are used, TWI requests for interrupt after transferring the current data. CPU
writes new data in the buffer after receiving the interrupt request.
After receiving data in Rx operation mode, TWI bus waits until data is read. Until the received
data is read, SCL is kept “Low.” It is released after new data is read.
When interrupts are used, TWI generates interrupt after receiving data. CPU that receives the
interrupt request reads the data.
116
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
12.5 BUS ARBITRATION PROCEDURES
These are procedures to prevent several masters from controlling a bus simultaneously. When a
master that has sent high level to SDA line acknowledges low-level SDA line set by another master,
it acknowledges that other master is controlling TWI bus and does not proceed with data transfer
any more.
Clocks generated in SCL line when Device 1 and Device 2 are operating simultaneously as
Masters are synchronized as shown below:
start counting
HIGH period
wait state
CLK1
counter reset
CLK2
SCL
Figure 12-5 Bus arbitration 1 of TWI
In the above situation, Device 1 or Device 2 has priority according to the data value indicated on
SDA line as shown in the following figure.
master1 loses Arbitration
DATA1
SDA

DATA1
DATA2
SDA
SCL
S
Figure 12-6 Bus arbitration 2
Advanced Digital Chips, Inc.
CONFIDENTIAL
117
CANTUS
Ver 2.04
12.6 ABORT CONDITIONS
When arbitration does not occur:
1. When MSTR bit in TWICTRL register is cleared, STOP condition occurs.
2. NO ACK is generated for STOP condition to occur. In other words, STOP condition occurs when
SDA signal is not “Low” in ACK section.
When arbitration occurs:
When control is lost by arbitration, MSTR bit is cleared but Stop condition does not occur. SLC
clock in progress proceeds until transfer of one byte is over and SDA for data output becomes
“High.”
12.7 Operational Flow Diagrams
TWI initialization
TWI should be initialized first.
BEGIN
Enable TWI by setting
TWIEN
Register setting
Enable TWI interrupt
(Optional)
END
Figure 12-7 TWI Initialization Flow Char
118
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
Master Transmit /Receive
The following is the flow chart for data transmission/reception by TWI. The biggest difference
between transmission and reception is that at the time of reception there is a step to set ACK bit to
NOACK before receiving the last data. It is for Master to inform Slave of the fact that it is the last Rx
data. In addition, dummy read step for TWIDATA register is required to generate SCL clock for
receiving actual data.
BEGIN
YES
Bus Busy ?
NO
Write TWI Header in
TWIDATA
Set MSTA in
TWICON to Generate
START
Transfer
Complete ?
NO
YES
Write Data to
TWIDATA
Transfer
Complete ?
NO
YES
NO
Last Word?
YES
Negate MSTA in
TWICON to Generate
STOP
END
Figure 12-8 Master Transmit Flow Char
Advanced Digital Chips, Inc.
CONFIDENTIAL
119
CANTUS
Ver 2.04
BEGIN
YES
Bus Busy ?
NO
Write TWI Header in
TWIDATA
Set MSTA in
TWICON to Generate
START
Transfer
Complete ?
NO
YES
Write TWI Header in
TWIDATA
Set REPST in
TWICON to Generate
RESTART
NO
Transfer
Complete ?
YES
Dummy Read
TWIDATA
Transfer
Complete ?
NO
Read Data from
TWIDATA
YES
last work -1 ?
NO
YES
Set TXAK in
TWICON to Turn of
ACK
YES
Read data from
TWIDATA
Transfer
Complete ?
NO
YES
END
Figure 12-9 Master Receive Flow Char
120
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
Slave Mode (Polling mode)
BEGIN
Receive
Header ?
(tcf = 1?)
Addressed as
Salve ?
NO
YES
Check SRW bit in
TWISTAT for
Xmit/Rcv
Rx
Tx
Read dummy data
from TWIDATA
(for tcf bit clear)
Transfer
complete ?
Write Tx Data in
TWIDATA
NO
YES
Transfer
complete ?
Read Rx Data
from TWIDATA
YES
YES
NO
YES
YES
Bus Busy ?
Bus Busy ?
NO
NO
END
Figure 12-10 Slave Mode Flow Chart (Polling)
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CONFIDENTIAL
121
CANTUS
Ver 2.04
Slave Mode (Interrupt mode)
BEGIN
(tcf Interrupt occurred)
Addressed
as Salve ?
NO
YES
Check SRW bit in
TWISTAT for
Rcv/Xmit
Read/Write
TWIDATA
END
Figure 12-11 Slave Mode Flow Chart (Interrupt)
122
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
12.8 TWI Control Registers
TWI Control Register (TWICTRL)
Address: 0x8002_2000
Bit
R/W
Description
31 : 8
R
Reserved.
7
RW
TWIEN : TWI Controller Enable.
This bit must be set before any other control register bits
have any effect.
0 : Resets and disables the TWI controller
1 : Enables the TWI controller
6
R
Reserved.
5
RW
TWIMOD : Master/Slave Mode Select.
When the microprocessor changes this bit from “0” to “1”,
the TWI controller generates a START condition in Master
mode. When this bit is cleared, a STOP condition is
generated and the TWI controller switches to Slave mode.
If this bit is cleared, however, because arbitration for the
bus has been lost, a STOP condition is not generated.
1 : Generate Start condition
0 : Generate Stop condition
4
RW
TWITR : Transmit/Receive Mode Select.
This bit selects the direction of Master transfers. Available
only in master device.
0 : Master Receive
1 : Master Transmit
3
RW
TWIAK : Transmit Acknowledge Enable.
This bit specifies the value driven onto the SDA line during
acknowledge cycles for both Master and Slave receivers
0 : Acknowledge
1 : No acknowledge
Since Master receivers indicate the end of data reception
by not acknowledging the last byte of the transfer, this bit
is the means of the microprocessor to end a Master
receiver transfer.
2
RW
REPST : Repeated Start.
Writing a “1” to this bit generates a repeated START
condition on the bus if the TWI controller is the current bus
Master. This bit is always read as “0”
1
R/W
TCIE : Transfer complete Interrupt enable bit
This bit initiates the interrupt request for one byte of data
transfer.
1 : Interrupt enable
0 : Interrupt disable
0
R/W
LSTIE : Lost arbitration Interrupt enable bit
This bit enables interrupt request generation for a master
which lost arbitration.
1 : Interrupt enable
0 : Interrupt disable
Advanced Digital Chips, Inc.
CONFIDENTIAL
Default Value
0
0
0
0
0
0
0
123
CANTUS
Ver 2.04
TWI Status Register (TWISTAT)
Address: 0x8002_2004
Bit
R/W
Description
31 : 10
R
Reserved.
9
RW
TXEMPTY : TX Buffer Empty.
This bit represents TX buffer status. User may write to
buffer when this bit is 0.
1: TX buffer is empty.
0: Data to transmit exists in TX buffer.
8
RW
RXFULL : RX Buffer Full.
This bit represents RX buffer status. User may read
when this bit is 1.
1: Data to read in RX buffer.
0: RX buffer is empty.
7
R
TWIDT : Data Transferring Bit.
While one byte of data and one bit of ACK are being
transferred, this bit is cleared. It is set by the falling
edge of the 9th clock of SCL and is cleared by reading
status register.
0 : Transfer in progress
1 : Transfer is complete
6
R
TWIAS : Addressed as Slave Bit.
When the address on the TWI bus matches the Slave
address in the TWIADDR register, the TWI controller is
being addressed as a Slave and switches to Slave
mode.
1: Address is matched.
0: No matched address.
5
R
TWIBUSY : Bus Busy Bit.
This bit indicates the status of the TWI bus. This bit is
set when a START condition is detected and cleared
when a STOP condition is detected.
0 : Indicates the bus is idle
1 : Indicates the bus is busy
4
RW
TWILOST : Lost Arbitration Bit.
This bit is set by hardware when arbitration for the TWI
bus is lost. This bit must be cleared by microprocessor
writing a „1‟ this bit.
3
R
TWISRW : Slave Read/Write Bit.
When the TWI controller has been addressed as a
Slave (AAS is set), this bit indicates the value of the
read/write bit sent by the Master. This bit is only valid
when a complete transfer has occurred and no other
transfers have been initiated.
0 : Indicates Master writing to Slave
1 : Indicates Master reading from Slave
2
R
Reserved.
1
RW
RSF : Repeated start flag
This flag bit is used to confirm the occurrence of
repeated Start condition. This bit is set when repeated
Start condition occurs and cleared by Stop condition or
by writing a 1 to this bit.
1: Repeated Start condition occurred.
0: Repeated Start condition did not occur or Stop
124
CONFIDENTIAL
Default Value
1
0
0
0
0
0
0
0
Advanced Digital Chips, Inc
Ver 2.04
0
CANTUS
R
condition occurred.
TWIRXAK : Received Acknowledge Bit.
This bit reflects the value of the SDA signal during the
acknowledge cycle of the transfer.
0 : Indicates that an acknowledge was received
1 : Indicates that no acknowledge was received
TWI Address Register(TWIADR)
Address: 0x8002_2008
Bit
R/W
Description
31 : 8
R
Reserved.
7: 0
RW
Slave Address.
7-bit slave address, latched from the TWI bus. You can
read the TWIADDR value at any time, regardless of
the current serial output enables bit (TWICON) setting.
bit[7:1] : Slave Address
bit[0] : Not mapped
TWI Data Register (TWIDATA)
Address: 0x8002_200C
Bit
R/W
Description
31 : 8
R
Reserved.
7:0
RW
TWI data.
Write – Data to transfer
Read – Received data
TWI Baud-Rate 0 Register (TWIBR0)
Address: 0x8002_2010
Bit
R/W
Description
31 : 4
R
Reserved.
7:0
RW
Baud-rate 0 Value. TWIBR0 ≥ 3
Advanced Digital Chips, Inc.
CONFIDENTIAL
1
Default Value
0x00
Default Value
0x00
Default Value
0x0F
125
CANTUS
Ver 2.04
TWI Baud-Rate 1 Register (TWIBR1)
Address: 0x8002_2014
Bit
R/W
Description
31 : 9
R
Reserved.
8:0
RW
Baud-rate 1 Value.. TWIBR1 ≥ 0
Default Value
0xFF
TWIBR 0  f PCLK  700ns  3
f PCLK
(2TWIBR1  TWIBR 0  7)
f
TWIBR 0  7
TWIBR1  PCLK 
2SCL
2
SCL 
* f PCLK = AMBA APB clock frequency
*SCL = TWI bud rate
ex) When APB clock is 50MHz and TWI baud rate is 400Kbps, (
TWIBR 0  50 MHz  700ns  3  50 10  700 10
6
SCL 
9
f PCLK
= 50MHz, SCL = 400Kbps)
 3  38
f PCLK
50MHz
50 10 6
 400 Kbps 
 400 10 3 
(2TWIBR1  TWIBR 0  7)
(2TWIBR1  38  7)
(2TWIBR1  45)
<Baud-rate Register Setting Reference Table>
TWIBR1
f PCLK
TWIBR0
400Kbps 300Kbps 200Kbps
48Mhz
37(0x25) 38(0x26) 58(0x3A) 98(0x62)
24Mhz
20(0x14) 17(0x11) 27(0x1B) 47(0x2F)
12Mhz
12(0xC)
6(0x6)
11(0xB)
21(0x15)
6Mhz
7(0x7)
1(0x0)
3(0x3)
8(0x8)
11.2896Mhz
11(0xB)
5(0x5)
10(0xA)
19(0x13)
5.6448Mhz
7(0x7)
0(0x0)
3(0x3)
7(0x8)
* There may be slight errors in the values in the above table.
126
CONFIDENTIAL
100Kbps
218(0xDA)
107(0x6B)
51(0x33)
23(0x17)
48(0x30)
21(0x16)
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
13 UART
CANTUS has a built-in 8-channel Universal Asynchronous Receiver/ Transmitter (UART)
Controller that has various control functions for serial asynchronous communication with general
PC and I/O devices with RS-232C interface function.
Key Features
- Compatible with standard 16450/16550 UARTs
- Fully programmable serial-interface protocols
5,6,7,8-bit characters
Even, odd or no-parity, stick parity generation and detection
1, 1.5, 2 stop bit generation
Baud rate generator
- Line break generation and detection
- False start bit detection
- Prioritized transmit, receive and line status control interrupts
- Independent 16 characters transmit and receive 16Bytes FIFOs
- 8 Ch. UARTs
Receiver
Buffer
Register
S
E
L
E
C
T
Receiver
FIFO
Transmitter
Tr
Holding
Register
Transmitter
FIFO
APB BUS
Receiver
Shift
Register
S
E
L
E
C
T
Transmitter
Shift
Register
Serial
Input
Serial
Output
FIFO
Control
Register
Divisor
Latch(MS,LS)
Baud
Generator
Line
Control
Register
Line
Status
Register
Interrupt
Enable
Register
Interrupt
Control
Logic
UART
Interrupt
Interrupt
ID
Register
Figure 13-1 UART Block Diagram
Advanced Digital Chips, Inc.
CONFIDENTIAL
127
CANTUS
Ver 2.04
13.1 UART Registers Summary
Table 13-1 UART Register Summary
DLAB = 0
DLAB = 0
DLAB = 0
DLAB = 0
DLAB = X
DLAB = X
DLAB = X
DLAB = 1
DLAB = 1
0x00
0x00
0x04
0x08
0x08
0x0C
0x14
0x00
0x04
Interrupt
Interrupt
FIFO
Line
Line
Divisor
Divisor
Enable
Ident.
Control
Control
Status
Latch
Latch
Register
Register
Register
Register
Register
(LSB)
(MSB)
DLM
Receiver
Bit
No.
Buffer
Register
0
Transmitte
r
Holding
Register
RBR
THR
IER
IIR
FCR
LCR
LSR
DLL
R
R/W
R/W
R
R/W
R/W
R
R/W
R/W
Data Bit 0
Data Bit 0
Enable
“0” if
FIFO
Word
Data
Bit 0
Bit 0
Received
Interrupt
Enable
Length
Ready
Data
Pending
Bit 1
Bit 1
Bit 2
Bit 2
Bit 3
Bit 3
Bit 4
Bit 4
Bit 5
Bit 5
Bit 6
Bit 6
Bit 7
Bit 7
Select
Available
Bit 0
Interrupt
1
Data Bit 1
Data Bit 1
Enable
Interrupt
RCVR
Word
Overrun
Transmitte
ID Bit 0
FIFO
Length
Error
Reset
Select
r
Holding
Bit 1
Register
Empty
Interrupt
2
Data Bit 2
Data Bit 2
Enable
Interrupt
XMIT
Number of
Parity
Receiver
ID Bit 1
FIFO
Stop
Error
Reset
Bits
Line
Status
Interrupt
3
Data Bit 3
Data Bit 3
0
Interrupt
0
ID Bit 2
4
Data Bit 4
Data Bit 4
0
0
Reserved
Parity
Framing
Enable
Error
Even
Break
Parity
Interrupt
Select
5
Data Bit 5
Data Bit 5
0
0
Reserved
Stick
Transmitte
Parity
r
Holding
Register
6
Data Bit 6
Data Bit 6
0
FIFOs
RCVR
Set
Transmitte
Enabled
Trigger(LS
Break
r
FIFOs
RCVR
Divisor
Error in
Enabled
Trigger(M
Latch
RCVR
SB)
Access Bit
FIFO
B)
7
Data Bit 7
Data Bit 7
0
Empty
(DLAB)
* DLAB = LCR[7](Divisor Latch Access Bit)
* FIFO Control Register :
- DLAB = 0 : Register Write
- DLAB = 1 : Register Read
* Addresses 0x10(0x30), 0x18(0x38), and 0x1C(0x3C) are reserved for compatibility with 16550 UART Standard.
128
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
13.2 Serial Data Format
For UART of CANTUS, it is possible to change serial data format for UART communication by
register setting of ULCRn[4:0] bit. The following table describes the data format that can be
changed by register setting of ULCRn[4:0] bit.
ULCRn[4:0]
Description
Start bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Stop bit
00010
No Parity /
1 Stop bit /
7 Data bit
Start bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Stop bit
Start bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Stop bit
Stop bit
Data bit
Stop bit
00011
No Parity /
1 Stop bit /
8 Data bit
00110
No Parity /
2 Stop bit /
7 Data bit
Start bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Stop bit
00111
No Parity /
2 Stop bit /
8 Data bit
Start bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Parity bit
Stop bit
11010
Even Parity /
1 Stop bit /
7 Data bit
Start bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Parity bit
Stop bit
11011
Even Parity /
1 Stop bit /
8 Data bit
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CONFIDENTIAL
129
CANTUS
Ver 2.04
Start bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Parity bit
Stop bit
Stop bit
11110
Even Parity /
2 Stop bit /
7 Data bit
Start bit
Data bit
Data bit Data bit
Data bit
Data bit
Data bit Data bit Data bit Parity bit Stop bit
Stop bit
11111
Even Parity /
2 Stop bit /
8 Data bit
Start bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Parity bit
Stop bit
01010
Odd Parity/
1 Stop bit /
7 Data bit
Start bit
Data bit
Start bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Stop bit
Parity bit
01011
Odd Parity/
1 Stop bit /
8 Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Data bit
Parity bit
Stop bit
Stop bit
01110
Odd Parity/
2 Stop bit /
7 Data bit
Start bit
Data bit
Data bit Data bit
Data bit
Data bit Data bit
Data bit Data bit Parity bit Stop bit
Stop bit
01111
Odd Parity/
2 Stop bit /
8 Data bit
Figure 13-2 UART LCR Register Setting and Serial Data Format
130
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
13.3 UART Baud Rate
TX/RX baud rate is calculated using the following formula:
UART Baud Rate 
f PCLK
16  UDL
UART Divisor Latch Value (UDL) = UDLM[7:0] << 8 + UDLL[7:0]
Table 13-2 UART Baud Rate
f PCLK (MHz)
2400 bps
4800 bps
9600 bps
14400
bps
19200
bps
38400
bps
57600
bps
115200b
ps
1.024
2.048
5.6448
11.2896
24.0
48.0
27
1.23
53
0.63
147
0.00
294
0.00
625
0.00
1250
0.00
-
27
1.23
74
0.68
147
0.00
313
0.16
625
0.00
-
-
37
0.68
74
0.68
156
0.16
313
0.16
-
9
1.23
25
2.00
49
0.00
104
0.16
208
0.16
-
-
18
2.08
37
0.68
78
0.16
156
0.16
-
-
9
2.08
18
2.08
39
0.16
78
0.16
-
-
6
2.08
12
2.08
26
0.16
52
0.16
-
-
3
2.08
6
2.08
13
0.16
26
0.16
UDL
ERR(%
)
UDL
ERR(%
)
UDL
ERR(%
)
UDL
ERR(%
)
UDL
ERR(%
)
UDL
ERR(%
)
UDL
ERR(%
)
UDL
ERR(%
)
*** When ERR is 2.2% or higher, stability of UART operation cannot be guaranteed.
Advanced Digital Chips, Inc.
CONFIDENTIAL
131
CANTUS
Ver 2.04
13.4 UART Control Registers
UART Channel Receiver Buffer Registers ( UxRB )
Address: 0x8002_1400 / 0x8002_1420 / 0x8002_1440 / 0x8002_1460
0x8002_1800 / 0x8002_1820 / 0x8002_1840 / 0x8002_1860
Bit
R/W
Description
31: 8
R
Reserved.
7:0
R
Receive Buffer Data
Default Value
-
*** Accessible when DLAB is “0.”
UART Channel Transmitter Holding Registers ( UxTH )
Address: 0x8002_1400 / 0x8002_1420 / 0x8002_1440 / 0x8002_1460
0x8002_1800 / 0x8002_1820 / 0x8002_1840 / 0x8002_1860
Bit
R/W
Description
31: 8
W
Reserved.
7:0
W
Transmit Holding Data
Default Value
-
*** Accessible when DLAB is “0.”
UART Channel Interrupt Enable Registers ( UxIE )
Address: 0x8002_1404 / 0x8002_1424 / 0x8002_1444 / 0x8002_1464
0x8002_1804 / 0x8002_1824 / 0x8002_1844 / 0x8002_1864
Bit
R/W
Description
31: 3
R
Reserved.
2
RW
RLSIEN : Receiver Line Status Interrupt Enable bit
0 : Disable
1 : Enable
1
RW
THEIEN : Transmitter Holding Empty Interrupt Enable
bit
0 : Disable
1 : Enable
0
RW
RDAIEN : Received Data Available Interrupt Enable bit
0 : Disable
1 : Enable
Default Value
0
0
0
*** Accessible when DLAB is “0.”
132
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UART Channel Interrupt Identification Register ( UxII )
Address: 0x8002_1408 / 0x8002_1428 / 0x8002_1448 / 0x8002_1468
0x8002_1808 / 0x8002_1828 / 0x8002_1848 / 0x8002_1868
Bit
R/W
Description
31 : 8
R
Reserved.
7:6
R
FIFOST : FIFOs Enabled Status bit.
00 : not in FIFO mode
11 : FIFO mode
5:4
R
Reserved
3:1
R
INTID : UART Interrupt ID
( Note, UART Interrupt Control Function)
0
R
INTP : UART Interrupt Pending bit
When this bit is a logic 1, no interrupt is pending
Default Value
00
0
000
1
*** Accessible as Read mode only when DLAB is “0.”
Table 13-3 UART Interrupt Control Function
Interrupt
Identification Register
Bit
Bit
Bit
Bit
3
2
1
0
Priorit
y
Level
Interrupt
Type
Interrupt Reset
Condition
Interrupt Source
0
0
0
1
-
None
None
-
0
1
1
0
Highes
t
Receiver Line
Status
Overrun Error or Parity Error
Framing Error or Break Interrupt
Reading the Line Status
Register
0
1
0
0
Secon
d
Received
Data
Available
Receiver Data Available or
Trigger Level Reached
Reading
the
Receiver
Buffer
Register or the FIFO Drops
Below the Trigger Level
1
1
0
0
Secon
d
Character
Timeout
Indication
No Characters have been
removed
from or input to the RCVR FIFO
during the last 4 Char. times,
and
there is at least 1 Char. in it
during this Time
Reading the Receiver
Buffer Register
0
0
1
0
Third
Transmitter
Holding
Register
Empty
Transmitter Holding
Register Empty
Reading the IIR Register
(if source of interrupt) or
Writing into the Transmitter
Holding Register
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UART Channel FIFO Control Register ( UxFC )
Address: 0x8002_1408 / 0x8002_1428 / 0x8002_1448 / 0x8002_1468
0x8002_1808 / 0x8002_1828 / 0x8002_1848 / 0x8002_1868
Bit
R/W
Description
31 : 8
R
Reserved.
7:6
RW
RFTL : Receiver FIFO Trigger Level
00 : 1 Byte
01 : 4 Byte
10: 8 Byte
11 : 14 Byte
5:3
R
Reserved
2
RW
XFR : XMIT FIFO Reset
When XFR is “1,” all data in XMIT FIFO is reset. But,
data in Shift Register is not reset.
1
RW
RFR : RCVR FIFO Reset
When RFR is “1,” all data in RCVR FIFO is reset. But,
data in Shift Register is not.
0
RW
FIFOEN : FIFO Enable Bit
0 : 16450 UART Mode 1 : Enables FIFO
Default Value
00
0
0
0
*** Write mode when DLAB is “0” and read mode when it is “1.”
UART Channel Line Control Register ( UxLC )
Address: 0x8002_140C / 0x8002_142C / 0x8002_144C / 0x8002_146C
0x8002_180C / 0x8002_182C / 0x8002_184C / 0x8002_186C
Bit
R/W
Description
31 : 8
R
Reserved.
7
RW
DLAB : Divisor Latch Access Bit
When DLAB is “1,” Divisor Latch Registers are
readable/writable and FIFO Control Register is
readable.
6
RW
SB : Set Break
When SB is “1,” Logic “0” is output from Serial Data
Output. SB does not affect the internal Transmitter
Logic but affects Serial Output only.
5
RW
SP: Stick Parity
0: Disables Stick Parity
1: When PEN, EPS and SP are “1,” Parity Bit is “0.”
When PEN and SP are “1” and EPS is “0,” Parity
Bit is “1.”
4
RW
EPS: Even Parity Select
0: Select Odd Parity 1: Select Even Parity
3
RW
PEN : Parity Enable Bit
0: Disables Parity
1: Enables Parity
2
RW
STB: Number of Stop Bit
0: 1 Stop bit
1: 2 Stop bits (If WLS bit selects 5 bits/character, this
register has 1.5 Stop bits.)
1:0
RW
WLS: Word Length Select
00 : 5 Bits/Character 01 : 6 Bits/Character
10 : 7 Bits/Character 11 : 8 Bits/Character
Default Value
0
0
0
0
0
0
00
UART Channel Line Status Register ( UxLS )
Address: 0x8002_1414 / 0x8002_1434 / 0x8002_1454 / 0x8002_1474
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Bit
31 : 8
7
6
5
4
3
2
1
0
CANTUS
0x8002_1814 / 0x8002_1834 / 0x8002_1854 / 0x8002_1874
R/W
Description
R
Reserved.
R
EIRF: Error in RCVR FIFO
If not in FIFO mode, EIRF is always “0.” In FIFO
mode, EIRF becomes “1” if any of OE, PE, FE and PI
in RCVR FIFO is set to “1.” EIRF is cleared (“0”)
when LSR register is read, unless there are
continuous errors in FIFO.
R
TEMP: Transmitter Empty
If not in FIFO mode, TEMT is set to “I” when both
Transmitter Holding Register (THR) and Transmitter
Shift Register (TSR) are empty. It is cleared if there is
any data in THR or TSR. In FIFO mode, TEMT
becomes “1” when both Transmitter FIFO and TSR
are empty.
R
THRE: Transmitter Holding Register Empty
If not in FIFO mode, THRE becomes “1” when THR is
emptied as data from THR is sent to TSR. Then, it is
possible to write new data on THR to be sent. In FIFO
mode, THRE becomes “1” when Transmit FIFO is
empty and it is cleared when any byte is written on
Transmit FIFO. If THRE interrupt (ETHREI) is “1” and
THR is “1,” interrupt occurs.
R
BINT : Break Interrupt
: When received input data is stayed as “0” during fullword transfer time, BI becomes “1.” Full-word transfer
time means the entire time for sending Start, Data,
Parity, and Stop bits. In FIFO mode, this error is
applied to each byte in FIFO and when BI occurs, “0”
is written in FIFO, and cleared when CPU reads LSR.
R
FERR : Framing Error
FE becomes “1” when the received input data does
not have valid Stop bit. In FIFO mode, this error is
applied to each byte in FIFO and cleared when CPU
reads LSR.
R
PERR : Parity Error
PE becomes “1” when the received input data does
not matches with Parity bit selected by LCR register.
In FIFO mode, this error is applied to each byte in
FIFO, and cleared when CPU reads LSR.
R
OERR : Overrun Error
If not in FIFO mode, OE becomes “1” when new data
is written before data in RBR is read. In FIFO mode, it
becomes “1” when a new full-word is received in
Receiver Shift Register (RSR) while FIFO is full. In
this case, RSR continues to be updated with data but
is not sent to FIFO. This error is cleared when CPU
reads LSR.
R
DRDY: Data Ready
DR becomes “1” when the received data is written on
RBR or FIFO. It is cleared when all data in RBR or
FIFO is read by CPU.
Advanced Digital Chips, Inc.
CONFIDENTIAL
Default Value
0
1
1
0
0
0
0
0
135
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UART Channel Divisor Latch LSB Register ( UxDLL )
Address: 0x8002_1400 / 0x8002_1420 / 0x8002_1440 / 0x8002_1460
0x8002_1800 / 0x8002_1820 / 0x8002_1840 / 0x8002_1860
Bit
R/W
Description
31: 8
R
Reserved.
7:0
RW
Divisor Latch Least Significant Byte
Default Value
0x00
*** Accessible when DLAB is “1.”
UART Channel Divisor Latch MSB Register ( UxDLM )
Address: 0x8002_1404 / 0x8002_1424 / 0x8002_1444 / 0x8002_1464
0x8002_1804 / 0x8002_1824 / 0x8002_1844 / 0x8002_1864
Bit
R/W
Description
31: 8
R
Reserved.
7:0
RW
Divisor Latch Most Significant Byte
*** Accessible when DLAB is “1.”
136
CONFIDENTIAL
Default Value
0x00
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14 DMA (DIRECT MEMORY ACCESS)
DMA controller is capable of transferring a large-scale data for memory and IO. It has 2 channels,
and each channel has 16x4 byte FIFO. It can operate as 4/8/16 Burst mode at the time of
transferring word-unit transfer. Interrupt signals are generated upon DMA error or when DMA count
is over.
Figure 14-1 Structure of DMA Controller
Key Features
- 2 channel DMA
- Controls 32-bit addresses in 4-GByte area
- 24-bit counter that can transfer up to 16Mbytes at a time
- DMA request by software
- Chain mode that supports scattering/gathering for a unlimited number of data blocks
- Supports direct mode that can be set directly
- No burst, and 4/8/16 bursts using 16 x 4 byte FIFO
- Supports the functions to fix/increase/decrease addresses
- Supports DMA status flag bit for interrupt operation
- Adjusts data size so that it is possible to access down to byte unit
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14.1 DMA Operation
DMA controller can process each request source as individual DMA request. DMA operation
responds only to the selected request. In order for DMA controller to perform the selected DMA
operation, DMA Operation Enable and Cancel (DMAEN) bit in DMACTRL register should be set.
When DMA operation is completed, DMAEN bit is automatically cleared.
DMA request is generated by program or by other peripherals. Request sources are determined
by the setting of DMA Request Source Selection bit of DMACTRL.
DMA controller operates in two modes: Direct mode and Chain mode. In Direct mode, the user
can directly control DMASA, DMADA, and DMATCNT while in Chain mode, the user should records
the descriptor address on DMADT and then set DMAEN and DMAMODE bits in DMACTRL to
operate them.
DMA controller generates 3 types of addresses for Source and Destination addresses: For Fixed
address, the recorded address of DMASA and DMADA are outputted whenever data is transferred;
for Increment address, DMA controller increases the recorded address of DMASA and DMADA
whenever data is transferred; and for Decrement address, DMA controller decreases the recorded
addresses of DMASA and DMADA whenever data is transferred.
138
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14.2 DMA Descriptor Table
Descriptor contains information necessary for DMA controller to transfer data. The user should
prepare the descriptor for each block to be transferred and connect each descriptor using the next
description address in the descriptor field. When the user operates DMA controller after saving the
location of the start descriptor, DMA controller starts reading the descriptors. After reading one
descriptor, DMA controller transfers the data using the information contained in the descriptor. Then,
it repeats reading and execution until the last descriptor is carried out. Description of each
descriptor is summarized below:
Descriptor field
Source Address
Destination Address
Transfer Count
Next Description
Address
Control Flag
Table 14-1 DMA Descriptor summary
Description
After reading the descriptor from memory, DMA controller saves the
content of this field in DMASA.
After reading the descriptor from memory, DMA controller saves the
content of this field in DMADA.
After reading the descriptor from memory, DMA controller saves the
content of this field in DMATCNT.
After reading the descriptor from memory, DMA controller saves the
content of this field in the next description address buffer inside DMA
controller.
Control setting for DMA transfer. After reading the descriptor from
memory, DMA controller saves the content of this field in DMACTRL
and temporary flag buffer.
31
source address
offset
0
0x0
Reserved
Destination address
Reserved
Count
Next description address
Reserved
Control flag
0x4
0x8
0xc
0x10
0x14
0x18
0x1c
Figure 14-2 Structure of DMA Descriptor
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Descriptor table address register
31
Source address
Reserved
Destination address
Reserved
Count
Descriptor 1 address
Reserved
Control flag
Descriptor 0
31
Source address
Reserved
Destination address
Reserved
Count
Descriptor 2 address
Reserved
Control flag
Descriptor 1
Descriptor 2Descriptor 3
Descriptor N-1
31
1 offset
00 h
04 h
08 h
0C h
10 h
14 h
18 h
1C h
1 offset
00 h
04 h
08 h
0C h
10 h
14 h
18 h
1C h
1 offset
Source address
00 h
Reserved
04 h
Destination address
08 h
Reserved
0C h
Count
10 h
Descriptor N +1
14 h
address
Reserved
18 h
Control flag
1C h
Descriptor N
Figure 14-3 Example of DMA Descriptor flow
140
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Structure of Descriptor
struct {
long a;
long Ra;
long b;
long Rb;
long c;
long d;
long Rd;
long e;
} descriptor;
/* 0x11223344
/* 0xxxxxxxxx
/* 0x55667788
/* 0xxxxxxxxx
/* 0x123456
/* 0xabcdef01
/* 0xxxxxxxxx
/* 0x00000000
*/
*/
*/
*/
*/
*/
*/
*/
Result:
Source address
Destination address
Count
Next descriptor address
State flag
Advanced Digital Chips, Inc.
= 0x11223344
= 0x55667788
= 0x123456
= 0xabcdef01
= 0x00000000
CONFIDENTIAL
141
CANTUS
Ver 2.04
14.3 Control Flag of Descriptor
Control flags recorded in the descriptor is read by DMA controller and recorded in DMACTRL.
They are the same as the flags of DMACTRL, except that there is no status flag indicating DMA
controller status but instead there are Bits 31 and 30 indicating the validity of the next descriptor.
DMA controller transfers data, referring to the corresponding content in the current descriptor. In
Chain mode, DMA controller attempts to read the next descriptor when Next Descriptor Flag bit is
“1.” But, if this bit is “0,” it acknowledges the current descriptor as the last one and requests
interrupt, to finish its operation. Bit 30 is to allow interrupt to occur when the descriptor is read. (The
others applies the same as DMACTRL.)
142
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14.4 DMA Control Registers
DMA Interrupt Status Register (DMAINTSTAT)
Address: 0x8000_0800
Bit
R/W
Description
31 : 18
R
Reserved
17
R
Ch1 Error Interrupt Status bit
0 : Okay
1 : Error
16
R
Ch0 Error Interrupt Status bit
0 : Okay
1 : Error
15 : 2
R
Reserved
1
R
Ch1 Terminal count Interrupt Status bit
0 : Idle
1 : Occurred Interrupt
0
R
Ch0 Terminal count Interrupt Status bit
0 : Idle
1 : Occurred Interrupt
DMA Interrupt Enable Register (DMAINTEN)
Address: 0x8000_0804
Bit
R/W
Description
31 : 18
R
Reserved
17
R/W
Ch1 Error Interrupt Enable bit
0 : Enable
1 : Disable
16
R/W
Ch0 Error Interrupt Enable bit
0 : Enable
1 : Disable
15 : 2
R
Reserved
1
R/W
Ch1 Terminal Count Interrupt Enable bit
0 : Enable
1 : Disable
0
R/W
Ch0 Terminal Count Interrupt Enable bit
0 : Enable
1 : Disable
DMA Channel Enable Status Register (DMACHSTAT)
Address: 0x8000_0808
Bit
R/W
Description
31 : 2
R
Reserved
1
R
Ch1 Enable Status
0 : Disable
1 : Enable
0
R
Ch0 Enable Status
0 : Disable
1 : Enable
Advanced Digital Chips, Inc.
CONFIDENTIAL
Default Value
0
0
0
0
Default Value
0
0
0
0
Default Value
0
0
143
CANTUS
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DMA Request Status Register (DMAREQSTAT)
Address: 0x8000_080C
Bit
R/W
Description
31 : 9
R
Reserved
8
R
Ch1 SDCD Request Status
0 : DMA Request
1 : Idle
7
R
Ch1 NAND Flash Read Request Status
0 : DMA Request
1 : Idle
6
R
Ch1 NAND Flash Write Request Status
0 : DMA Request
1 : Idle
5:1
R
Reserved
0
R
Ch0 I2S Request Status
0 : DMA Request
1 : Idle
Default Value
1
1
1
1
DMA Configuration Register (DMACFG)
Address: 0x8000_0810
Bit
R/W
Description
31 : 12
R
Reserved
11 : 10
R/W
Ch1 Data Swap mode
00 : Reserved
01 : Byte Swap in 16bit Transfer mode
10 : Half-Word Swap in 32bit Transfer mode
11 : Byte Swap in 32bit Transfer mode
9:8
R/W
Ch0 Data Swap mode
00 : Reserved
01 : Byte Swap in 16bit Transfer mode
10 : Half-Word Swap in 32bit Transfer mode
11 : Byte Swap in 32bit Transfer mode
7:1
R
Reserved
0
R/W
DMA Request Enable
0 : Enable
1 : Disable
Default Value
00
00
0
Byte Swap in 16bit Transfer mode
BYTE 1
BYTE 0
BYTE 0
BYTE 1
Half-Word Swap in 32bit Transfer mode
BYTE 3
BYTE 2
BYTE 1
BYTE 0
BYTE 1
BYTE 0
BYTE 3
BYTE 2
BYTE 2
BYTE 3
Byte Swap in 32bit Transfer mode
BYTE 3
BYTE 2
BYTE 1
BYTE 0
BYTE 0
BYTE 1
Figure 14-4 DMA Data Swap mode
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DMA Last Request Register (DMALREQ)
Address: 0x8000_0818
Bit
R/W
31 : 2
R
Reserved
1
R/W
Ch1 Last Request
0 : Continue
0
R/W
Ch0 Last Request
0 : Continue
Advanced Digital Chips, Inc.
CANTUS
Description
Default Value
0
1 : Last Transfer
0
1 : Last Transfer
CONFIDENTIAL
145
CANTUS
Ver 2.04
DMA Control Register (DMAnCTRL)
Address: 0x8000_0820 / 0x8000_0840
Bit
R/W
Description
31
R/W
Next Descriptor Flag (Only Chain Mode)
0 : Next Descriptor Enable
1 : Next Descriptor Disable
30
R/W
Descriptor Read Interrupt Mask
(Only Chain Mode)
0 : Disable Interrupt Mask
1 : Enable interrupt Mask
29 : 25
R
Reserved
24
R/W
DMAEN : DMA Operation Enable and Cancel bit
0 : Cancels DMA Operation
1 : DMA Operation Enable by Software
23
R/W
Memory initialize mode selection
0: Normal DMA operation
1: Copy DMAnMIV Register value to Memory for
Initializing memory
22 : 19
R
Reserved
18 : 16
R/W
DMA Request Source Selection
DMA Ch 0
DMA Ch 1
000 : I2S
000 : NAND Flash Write
11x : Software
001 : NAND Flash Read
010 : SDCD
1xx : Software
15
R
DMAMODE : DMA Chain Mode Enable bit
0 : Direct Mode
1 : Chain Mode
14 : 12
R/W
Protection and Access Information
(System Bus Protection control)
- bit 14
0 : Cacheable
1 : Not Cacheable
- bit 13
0 : Bufferable
1 : Not Bufferable
- bit 12
0 : Privileged
1 : User
11
R/W
Lock(System bus Lock)
0: Unlock
1 : Lock
10
R/W
DMA Transfer Count Mode
0 : Reference Count
1 : Not used (unlimited transfer)
9:8
R/W
DMA Burst Size
00 : No burst
01 : 4 beat incrementing burst
10 : 8 beat incrementing burst
11 : 16 beat incrementing burst
7:6
R/W
Direction of DMA Source Address
00 : Fixed Address
01 : Reserved
10 : Increment
11 : Decrement
5:4
R/W
Direction of DMA Destination Address
00 : Fixed Address
01 : Reserved
10 : Increment
11 : Decrement
3:2
R/W
Data Size for Transfer
00 : 8-bit(1byte)
01 : 16-bit(1half-word)
10 : 32-bit(1word)
11 : Reserved
146
CONFIDENTIAL
Default Value
0
0
0
0
-
000
0
000
0
0
00
00
00
00
Advanced Digital Chips, Inc
Ver 2.04
1:0
CANTUS
R
Reserved
-
DMA Source Address Register (DMAnSA)
Address: 0x8000_0824 / 0x8000_0844
Bit
R/W
Description
31 : 0
R/W
DMA Source Address A[31:0]
Default Value
0x0000_0000
DMA Destination Address Register (DMAnDA)
Address: 0x8000_0828 / 0x8000_0848
Bit
R/W
Description
31 : 0
R/W
DMA Destination Address A[31:0]
Default Value
0x0000_0000
DMA Transfer Count Register (DMAnTCNT)
Address: 0x8000_082C / 0x8000_084C
Bit
R/W
Description
31 : 24
R
Reserved
23 : 0
R/W
DMA Transfer Count Register.
Decreases by 1 for every data transfer.
Also decreases by 1 for burst.
ex) 16burst * 32bit * 1(Count) = 64byte
DMA Descriptor Table Address Register (DMAnDT)
Address: 0x8000_0830 / 0x8000_0850
Bit
R/W
Description
31 : 0
R/W
DMA Descriptor Table Address A[31:0]
Default Value
0x000000
Default Value
0x0000_0000
DMA Memory Initialize Value Register (DMAnMIV)
Address: 0x8000_0834 / 0x8000_0854
Bit
R/W
Description
Default Value
31 : 0
R/W
Value for initialing memory
0x0000_0000
*** Sets in the destination area a value to be initialized when DMA controller operates in Memory
Initialize mode.
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CONFIDENTIAL
147
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15 NAND FLASH CONTROLLER
NAND Flash controller controls 8-bit I/O type NAND Flash Memory and data transfer. Data
transfer can be done either by using internal data register or by setting the internal 2K byte SRAM
as a buffer.
Key Features
- 8bit I/O support
- 3-cycle/4-cycle/5-cycle Address support
- 2KBytes Buffer mode
- 1bit for SLC and 4bit ECC for MLC
NFCTRL_IRQ
(To Interrupt Controller)
SYS_RESETX
(To All Blocks)
adr_siz
(From external pin)
NFCFG
NF_nCS
NF_CLE
NFCTRL
Controller /
Auto Boot logic
NF_nWE
NF_nRE
AHB BUS
NFSTAT
NF_nBUSY
1bit ECC
4bit ECC
NFCMD
NFADD
NF_IO[7:0]
NFDATA
Memory
Controller
2KBytes
Buffer
Figure 15-1 NAND Flash Controller Block Diagram
148
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15.1 NAND Flash Operation
Data Read/Write
1. Set the timing for data transfer in NFCFG register.
2. Set NAND Flash Memory command in NFCMD register.
3. Set NAND Flash Memory address to be access, through NFADR register. At this time,
the address should be set as many times as the address cycle required for accessing
NAND Flash.
4. Perform Read/Write operation through NFCPUDATA register. Before reading data or
writing data, NDFL_nBUSY pin must be checked.
HCLK
NAND_ALE
NAND_CLE
NAND_nWE
NAND_nRE
Ts
Twp /
Trp
Th
Figure 15-2 Read/Write Timing Diagram of NAND Flash Memory
Buffer Memory (2Kbytes)
NAND Flash controller is cable of fast transfer when internal memory is set as buffer memory.
The buffer memory can be accessed through N2U, N2L, U2N, and L2N bits of NFCTRL register.
When 1-page size of NAND Flash Memory is 512 bytes, only 512 bytes can be transferred but
when it is 2Kbytes, both 512 bytes and 1 Kbytes can be transferred.
Start address of internal memory (SRAM) to be set as buffer memory should be set in NFLBADR
and NFUBADR registers.
Advanced Digital Chips, Inc.
CONFIDENTIAL
149
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Buffer
(Internal SRAM)
N2U
Upper
1024 Bytes
CPU
Access
Lower
1024 Bytes
U2N
N2L
NAND Flash
Controller
NAND
Flash
Memory
L2N
AHB BUS
Figure 15-3 Transmission through Buffer of NAND Flash Controller
DMA Operation
NAND Flash controller supports DMA transmission. First, DMA controller should be set and then,
NAND Flash controller should be set. When DMA operation is set in NFCTRL register, DMA
nd
controller starts NAND Flash Memory and DMA transfer. For large-type (2 generation) NAND
st
Flash Memory, up to 2Kbytes can be set as transfer unit and for small-type (1 generation) NAND
Flash Memory, up to 512bytes can be set.
DMA setting can be available either as Single or as Burst transfer. It should be noted that burst
access is available only for 32-bit data width.
150
CONFIDENTIAL
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CANTUS
15.2 ECC
CANTUS supports not only SLC-type NAND Flash but also MLC-type NAND Flash. MLC-type
NAND Flash has higher error rate than that of SLC-type, these errors should be corrected in order
for MLC-type to be used.
NAND Flash controller of CANTUS generates Parity bit using 4-bit BCH algorithm, and provides
data error recovery function using the algorithm. It also supports detecting and restoring up to 4-bit
errors for 512 byte data.
ECC Encoding
1. In order to use NAND Flash, set NFCFG register and then send the command and
address.
2. Read NFECC1 register, and clear ECC status and the ECC-related registers.
3. Set ECC GEN bit in NFCTRL register to “1.” (ECC Generation enable)
4. Send 512byte data. Whenever data is transferred, 52-bit size Parity bits are generated
and stored in NFECC0/NFECC1.
5. When 512byte data transmission is completed, read NFECC0 and then NFECC1
registers in order and stores the content in memory.
6. In order to transfer by the unit of 512bytes again, repeat Steps 2 through 5.
7. When 2Kbyte data transmission is completed, set ECC GEN bit in NFCTRL register to
“0.” (ECC Generation disable)
8. Save the parity bits for each 512 bytes that have been stored in memory, in the spare
area of NAND Flash.
ECC Decoding
1. In order to use NAND Flash, set NFCFG register and then send the command and
address.
2. Read NFECC1 register, and clear ECC status and the ECC-related registers.
3. Set ECC GEN bit in NFCTRL register to “1.” (ECC Decoding enable)
4. Read 512byte data.
5. When 512byte data reading is completed, access the spare area and read the
corresponding parity bits.
6. When reading the parity bits is completed, decoding is automatically started. Then, you
can check in NFSTAT register whether decoding is completed and whether it is successful.
7. When decoding is completed, the error locations are stored in NFERRLOC0~3 registers
and 8bit error patterns are stored in NFERRPTN0~3 registers.
8. Perform Exclusive-OR for 8bit data in NFERRLOC0~3 registers and for the values of
NFERRPTN0~3 registers, to restore the damaged data.
9. Repeat Steps 2 through 8 until 2Kbytes are read.
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15.3 NAND Flash Control Registers
NAND Flash Memory Control Register (NFCTRL)
Address: 0x8000_0C00
Bit
R/W
Description
31: 13
R
Reserved
12
R/W
4-bit ECC Generation Enable bit
0 : Disable
1 : Enable
11
R/W
Endian Select bit
0 : Little Endian
1 : Big Endian
10
R/W
Data Swap Size
0 : 8bit
1 : 16bit
9
R/W
DMA Write Request bit
0 : DMA Write Request Clear
1 : DMA Write Request
8
R/W
DMA Read Request bit
0 : DMA Read Request Clear
1 : DMA Write Request
7
R/W
Interrupt Enable at Busyx End
0 : Interrupt Disable
1 : Interrupt Enable
6
R/W
Interrupt Enable at Internal Buffer Transfer End
0 : Interrupt Disable
1 : Interrupt Enable
5
R/W
BCH ECC Decoding Done Interrupt Enable
0 : Interrupt Disable
1 : Interrupt Enable
4
R/W
Transfer Data Size in Internal Buffer mode
0 : 512Bytes
1 : 1KBytes (at 2Kbytes Page type)
3
R/W
N2U : NAND Flash to Upper Buffer
0 : Read Complete
1 : Enable NAND Flash to Upper Buffer Transfer
2
R/W
N2L : NAND Flash to Lower Buffer
0 : Read Complete
1 : Enable NAND Flash to Lower Buffer Transfer
1
R/W
U2N : Upper Buffer to NAND Flash
0 : Write Complete
1 : Enable Upper Buffer to NAND Flash Transfer
0
R/W
L2N : Lower Buffer to NAND Flash
0 : Write Complete
1 : Enable Lower Buffer to NAND Flash Transfer
152
CONFIDENTIAL
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
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NAND Flash Memory Command Set Register (NFCMD)
Address: 0x8000_0C04
Bit
R/W
Description
31 : 8
R
Reserved
7:0
R/W
NAND Flash Memory Command
Ex) Read, Programming, Erasing
NAND Flash Memory Address Register (NFADR)
Address: 0x8000_0C08
Bit
R/W
Description
31 : 8
R
Reserved
7:0
R/W
NAND Flash Memory Address
Ex) 3Bytes/4Bytes/5Bytes Address
Default Value
0x00
Default Value
0x00
NAND Flash Memory Data Register (NFCPUDATA)
Address: 0x8000_0C0C
Bit
R/W
Description
31 : 8
R
Reserved
7:0
R/W
NAND Flash Memory Read/Program Data
At CPU Write : Programming data
At CPU Read : Read data
Default Value
0x00
NAND Flash Memory DMA Data Register (NFDMADATA)
Address: 0x8000_0C10
Bit
R/W
Description
31 : 0
R/W
NAND Flash Memory Read/Program Data
At DMA Write : Programming data
At DMA Read : Read data
Default Value
0x0000_0000
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NAND Flash Memory Operation Status Register (NFSTAT)
Address: 0x8000_0C14
Bit
R/W
Description
31 : 8
R
Reserved
7
R
BCH Decoding Done Status
This bit is set when 4-bit ECC decoding is completed,
and cleared when it is read.
6:4
R
Error bits Count
This bit indicates the number of error bits. It is cleared
when this register is read.
3
R
BCH Decoding Result
0 : Decoding Failed
1 : Decoding Success
2
R
NAND Write/Read Operation Complete Status
This bit is to check the status of transfer using internal
2KB SRAM. It is “1” when transfer is completed, and
cleared when this register is read.
1: Completion
0: Transfer in Progress
1
R
NAND Flash Memory nBusy Level
0 : Busy
1 : Ready
0
R
NAND Flash Memory Busyx Rising Edge Status
This bit is set to “1” when Ready/Busyx signal
changes from “low” to “high,” and cleared when it is
read.
NAND Flash Memory ECC(Error Correction Code) Register (NFECC)
Address: 0x8000_0C18
Bit
R/W
Description
31 : 24
R
Reserved
23 : 16
R/Clea ECC2
r
(~P4, ~P4‟, ~P2, ~P2‟, ~P1, ~P1‟, ~P2048, ~P2048‟)
15 : 8
R/Clea ECC1
r
(~P1024, ~P1024‟, ~P512, ~P512‟, ~P256, ~P256‟,
~P128, ~P128‟)
7:0
R/Clea ECC0
r
(~P64, ~P64‟, ~P32, ~P32‟, ~P16, ~P16‟, ~P8, ~P8‟)
*** P1~P4 : Column Parity , P8~P2048 : Row Parity
*** ~ : Logically inverse operation
154
CONFIDENTIAL
Default Value
-
000
0
1
nBUSY Level
0
Default Value
0xFF
0xFF
0xFF
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NAND Flash Memory Configuration Register (NFCFG)
Address: 0x8000_0C1C
Bit
R/W
Description
31 : 21
R
Reserved
20
R/w
Read data Latch timing Adjust bit. Configure as system
clock.
0 : Minimum ~ 60Mhz
1 : 40Mhz ~ Maximum
19 : 17
R
Reserved
16
R/W
NDFL_nCS Control
0 : Chip Enable
1 : Chip Disable
15
R
Reserved
14 : 12
R/W
Ts : NDFL_ALE/NDFL_CLE Set-up Time
000 : 1 Clock
001 : 2 Clocks
010 : 3 Clocks
011 : 4 Clocks
100 : 5 Clocks
101 : 6 Clocks
110 : 7 Clocks
111 : 8 Clocks
11
R
Reserved
10 : 8
R/W
Twp : NDFL_nWE Pulse Width
000 : 1 Clock
001 : 2 Clocks
010 : 3 Clocks
011 : 4 Clocks
100 : 5 Clocks
101 : 6 Clocks
110 : 7 Clocks
111 : 8 Clocks
7
R
Reserved
6:4
R/W
Trp : NDFL_nRE Pulse Width
000 : 1 Clock
001 : 2 Clocks
010 : 3 Clocks
011 : 4 Clocks
100 : 5 Clocks
101 : 6 Clocks
110 : 7 Clocks
111 : 8 Clocks
3
R
Reserved
2:0
R/W
Th : NDFL_ALE/ NDFL_CLE/ NDFL_nCS Hold Time
000 : 1 Clock
001 : 2 Clocks
010 : 3 Clocks
011 : 4 Clocks
100 : 5 Clocks
101 : 6 Clocks
110 : 7 Clocks
111 : 8 Clocks
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Default Value
1
1
111
111
111
111
155
CANTUS
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NAND Flash Memory ECC Code for LSN data (NFECCL)
Address: 0x8000_0C20
Bit
R/W
Description
31 : 16
R
Reserved
15 : 8
R
S_ECC1
(1, 1, 1, 1, 1, 1, ~P4_s, ~P4‟_s)
7:0
R
S_ECC0
(~P2_s, ~P2‟_s, ~P1_s, ~P1‟_s, ~P16_s, ~P16‟_s,
~P8_s, ~P8‟_s)
*** P1_s~P4_s : Column Parity, P8_s~P16_s : Row Parity
*** ~ : Logically inverse operation
Default Value
0xFF
0xFF
NAND Flash Memory Lower Buffer Start Address Register (NFLBADR)
Address: 0x8000_0C24
Bit
R/W
Description
31 : 11
R
Reserved
10 : 0
R/W
Lower Buffer Start Address
Default Value
0x000
NAND Flash Memory Upper Buffer Start Address Register (NFUBADR)
Address: 0x8000_0C2C
Bit
R/W
Description
31 : 11
R
Reserved
10 : 0
R/W
Upper Buffer Start Address
Default Value
0x000
NAND Flash Memory MLC ECC0 Register (NFECC0)
Address: 0x8000_0C34
Bit
R/W
Description
31 : 0
R
4-bit ECC Parity Value
Low 32bits value of 52-bit parity
NAND Flash Memory MLC ECC1 Register (NFECC1)
Address: 0x8000_0C38
Bit
R/W
Description
31 : 20
R
Reserved
19 : 0
R
4-bit ECC Parity Value
High 20bits value of 52-bit parity
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CONFIDENTIAL
Default Value
0x0000_0000
Default Value
0x0000_0000
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NAND Flash Memory Error Location 0 Register (NFERRLOC0)
Address: 0x8000_0C40
Bit
R/W
Description
31 : 13
R
Reserved
st
12 : 0
R
1 Error byte location
Default Value
NAND Flash Memory Error Location 1 Register (NFERRLOC1)
Address: 0x8000_0C44
Bit
R/W
Description
31 : 13
R
Reserved
nd
12 : 0
R
2 Error byte location
Default Value
NAND Flash Memory Error Location 2 Register (NFERRLOC2)
Address: 0x8000_0C48
Bit
R/W
Description
31 : 13
R
Reserved
rd
12 : 0
R
3 Error byte location
Default Value
NAND Flash Memory Error Location 3 Register (NFERRLOC3)
Address: 0x8000_0C4C
Bit
R/W
Description
31 : 13
R
Reserved
th
12 : 0
R
4 Error byte location
Default Value
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0x0000
0x0000
0x0000
0x0000
157
CANTUS
Ver 2.04
NAND Flash Memory Error Pattern 0 Register (NFERRPTN0)
Address: 0x8000_0C50
Bit
R/W
Description
31 : 8
R
Reserved
st
7:0
R
1 Error byte pattern
Default Value
NAND Flash Memory Error Pattern 1 Register (NFERRPTN1)
Address: 0x8000_0C54
Bit
R/W
Description
31 : 8
R
Reserved
nd
7:0
R
2 Error byte pattern
Default Value
NAND Flash Memory Error Pattern 2 Register (NFERRPTN2)
Address: 0x8000_0C58
Bit
R/W
Description
31 : 8
R
Reserved
rd
7:0
R
3 Error byte pattern
Default Value
NAND Flash Memory Error Pattern 3 Register (NFERRPTN3)
Address: 0x8000_0C5C
Bit
R/W
Description
31 : 8
R
Reserved
th
7:0
R
4 Error byte pattern
Default Value
158
CONFIDENTIAL
0x00
0x00
0x00
0x00
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
16 I2S
CANTUS has a built-in I2S controller that is capable of connecting external audio Codec via I2S
Interface. Also, using the built-in voice Codec, I2S controller allows to configure a system at a
moderate price. As having a built-in IMA-ADPCM Codec Engine, it can process voice at the
compression ratio of 4:1.
Key Features
- I2S-bus, MSB-justified 2‟s complement format.
- Embedded Voice Codec interface.
- IMA-ADPCM Codec compatible
- 8/16-bit PCM data support.
- 16, 32, 48, 64 fs serial bit clock per channel. (fs : sampling frequency)
- 256, 384, 512 fs master clock.
- 128Bytes FIFOs for transmits and receives.
APB Bus
Bus Interface
Tx-Shifter
SDO
FIFO
IMA-ADPCM
Codec
Rx-Shifter
SDI
LRCK
Pre-Scaler
(Clock Gen)
SCLK
MCLK
Figure 16-1 I2S Block Diagram
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Ver 2.04
16.1 Frequency Control
In order to operate I2S controller, SCLK, LRCK, and MCLK frequencies should be set. The
following table illustrates the relationship between MCLK and LRCK. For example, if Master
frequency is set as 256fs for 44.1kHz, 11.2896MHz MCLK is required. The corresponding MCLK
should be set through the pre-scaler.
PCLK
Pre-Scaler Register
PMU
IMCLK
1/N
MCLK
Figure 16-2 I2S Pre-Scaler
LRCK
(fs)
MCLK
(MHz)
Table 16-1 I2S Sampling Frequency(LRCK) and MCLK Clock
8.000
11.025
16.000
32.000
44.100
48.000
KHz
KHz
KHz
KHz
KHz
KHz
256fs
2.048
2.8224
4.096
8.1920
11.2896 12.2880
384fs
3.072
4.2336
6.144
12.2880 16.9344 18.4320
512fs
4.096
5.6448
8.192
16.3840 22.5792 24.5760
96.000
KHz
24.5760
36.8640
49.1520
In addition, SCLK setting is as follows:
Table 16-2 I2S sampling frequency and serial bit clock
Serial bit per channel
8bit
16bit
CODEC Clock(MCLK)
Serial clock frequency(SCLK)
256fs
16fs, 32fs
32fs
384fs
16fs, 32fs, 48fs
32fs, 48fs
512fs
16fs, 32fs, 48fs, 64fs
32fs, 48fs, 64fs
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16.2 Interface Format
I2S controller supports I2S-bus format and MSB-justified 2‟s complement format.
For I2S-bus format, MSB bit is in the second cycle of SCLK after LEFT LRCK. If there is
remaining SCLK cycle after LSB, the bit is padded with „0.‟
MSB-justified format is the same as I2S-bus format except that MSB bit is in the first cycle of
SCLK.
Figure 16-3 I2S Interface format
16.3 Data Format
Data swap mode of I2SMODE register of I2S controller is 32-bit data, so that I2S controller can
receive any type of swappable data.
BYTE 3
BYTE 2
BYTE 1
BYTE 0
00
BYTE 3
BYTE 2
BYTE 1
BYTE 0
01
BYTE 0
BYTE 1
BYTE 2
BYTE 3
10
BYTE 1
BYTE 0
BYTE 3
BYTE 2
11
BYTE 2
BYTE 3
BYTE 0
BYTE 1
Figure 16-4 I2S Data Swap mode
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16.4 Transmit and Receive FIFO
Transmit FIFO and Receive FIFO of I2S controller consist of 64bytes respectively. However,
unless both Transmit and Receive occur at the same time, FIFO can be shared and used as
128bytes.
162
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16.5 Wave File Format
Wave file format starts with RIFF header. “WAVE” format consists of “fmt” Sub-Chunk and “data”
Sub-Chunk. “fmt” Sub-Chunk defines the sound data format, while “data” Sub-Chunk contains
information about the size of sound data.
Field
Chunk ID
Offset
(Byte)
0
Chunk size
4
Format
8
Subchunk1 ID
12
Subchunk1 size
16
Audio format
18
Num channels
Sample rate
Byte rate
20
24
28
Block align
30
Bits per sample
Extra size
Extra parameter
Subchunk2 ID
32
Subchunk2 size
Data
40
44
36
Table 16-3 Wave file format header
Size
Endian
Description
(Byte)
4
Big
Contain the letters “RIFF” in ASCII form.
(0x52494646 big-endian form)
4
Little
36 + Subchunk2 size, or more precisely:
This is the size of the rest of the chunk
following this number.
This is the size of the entire file in bytes
minus 8 bytes for the two fields not included
in this count:
Chunk ID and Chunk size.
4
Big
Contains the letters “WAVE”.
(0x57415645 big-endian form)
4
Big
Contain the letters “fmt”.
(0x666d7420 big-endian form)
4
Little
16 for PCM, or 20 for IMA-ADPCM
This is the size of the rest of the Subchunk1
which follows this number.
2
Little
PCM = 1 (i.e. Linear quantization)
Values other than 1 indicate some form of
compression:
IMA-ADPCM = 17
2
Little
Mono = 1, Stereo =2, etc.
4
Little
8000, 44100, etc.
4
Little
Sample rate * Num channels * Bits per
sample / 8
2
Little
Num channels * Bits per sample / 8:
The number of bytes for one sample
including all channels.
2
Little
8-bit = 8, 16-bit = 16, etc.
2
Little
If PCM, then doesn‟t exist.
X
Little
Space for extra parameters.
4
Big
Contain the letters “data”.
(0x64617461 big-endian form)
4
Little
This is the number of bytes in the data.
*
Little
The actual sound data.
*** Block align is included in the header of WAVE file format, of which value should be set in I2S
Mode register.
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16.6 I2S Control Registers
I2S Control Register ( I2SCTRL )
Address: 0x8002_2800
Bit
R/W
Description
31 : 8
R
Reserved
8
R/W
ADC input selection bit for recording
0 : I2S Interface (External Audio Codec)
1 : Embedded Voice Codec
7
R/W
Transmit access mode
0 : Normal / Interrupt
1 : DMA
6
R/W
Receive access mode
0 : Normal / Interrupt
1 : DMA
5
R/W
Transmit data request enable bit
0 : Disable
1 : Enable
4
R/W
Receive data request enable bit
0 : Disable
1 : Enable
3
R/W
Transmit pause enable bit
0 : Disable
1 : Enable
2
R/W
Receive pause enable bit
0 : Disable
1 : Enable
1
R/W
MCLK enable bit
0 : Disable
1 : Enable
0
R/W
I2S interface enable bit
0 : Disable
1 : Enable
164
CONFIDENTIAL
Default Value
0
0
0
0
0
0
0
0
0
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I2S Mode Register ( I2SMODE )
Address: 0x8002_2804
Bit
R/W
Description
31 : 30
R/W
Data swap mode
29
R
Reserved
28 : 16
R/W
Block align of WAVE file format header
15
R/W
Active level of LRCK
0 : High for left channel ( Low for right channel )
1 : Low for left channel ( High for right channel )
14
R/W
FIFO shared mode
0 : Separated mode
1 : Shared mode
13
R/W
Transmit volume control enable bit
0 : Disable
1 : Enable
12
R/W
Receive volume control enable bit
0 : Disable
1 : Enable
11 : 8
R/W
Quantization mode
0000 : PCM 8-bit unsigned stereo
0001 : PCM 8-bit unsigned mono
0010 : PCM 8-bit signed stereo
0011 : PCM 8-bit signed mono
0100 : PCM 16-bit unsigned stereo
0101 : PCM 16-bit unsigned mono
0110 : PCM 16-bit signed stereo
0111 : PCM 16-bit signed mono
1000 : IMA-ADPCM 4-bit stereo
1001 : IMA-ADPCM 4-bit mono
101x : Reserved
11xx : Reserved
7:6
R/W
Transfer mode
00 : No Transfer
01 : Receive
10 : Transmit
11 : Receive & Transmit
5
R/W
Device mode
0 : Master mode
1 : Slave mode
4
R/W
Serial interface format
0 : I2S-bus format
1 : MSB(Left)-justified format
3:2
R/W
MCLK frequency
00 : 256fs
01 : 384fs
10 : 512fs
11 : Revered
1:0
R/W
SCLK frequency
00 : 16fs
01 : 32fs
10 : 48fs
11 : 64fs
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CONFIDENTIAL
Default Value
00
0
0
0
0
0
0000
0
0
0
00
00
165
CANTUS
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I2S Pre-scaler Register ( I2SPRE )
Address: 0x8002_2808
Bit
R/W
Description
31 : 14
R
Reserved
4
R/W
MCLK selection bit
0 : PCLK
1 : IMCLK
3:0
R/W
Pre-scaler
Data value : 0 ~ 15 ( Division factor is N+1 )
I2S Status Register ( I2SSTAT )
Address: 0x8002_280C
Bit
R/W
Description
31 : 21
R
Reserved
20
R
LRCK channel index
When Active level of LRCK bit is „0‟,
0 : Right
1 : Left
19
R
Transmit FIFO half level status
When Tx FIFO is enable,
0 : More than half
1 : Less than half
18
R
Receive FIFO half level status
When Rx FIFO is enable,
0 : Less than half
1 : More than half
17
R
Transmit FIFO ready flag
When Transmit FIFO is enable,
0 : Not ready (empty) 1 : Ready (not empty)
16
R
Receive FIFO ready flag
When receive FIFO is enable,
0 : Not ready (full)
1 : Ready (not full)
15 : 8
R
Transmit FIFO data count
When FIFO is shared : 0 ~ 32 (Words)
When FIFO is not shared : 0 ~ 16 (Words)
7:0
R
Receive FIFO data count
When FIFO is shared : 0 ~ 32 (Words)
When FIFO is not shared : 0 ~ 16 (Words)
*** Half level at separated mode : 8 Words (32Bytes)
*** Half level at shared mode : 16 Words (64Bytes)
*** FIFO data count : 1 Word (4Bytes)
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CONFIDENTIAL
Default Value
0
0
Default Value
0
0
0
0
0
0x00
0x00
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I2S Data Register ( I2SDATA )
Address: 0x8002_2810
Bit
R/W
31 : 0
R/W
I2S data
CANTUS
Description
Default Value
0x00000000
I2S Volume Register ( I2SVOL )
Address: 0x8002_2814
Bit
R/W
Description
Default Value
31 : 29
R
Reserved
28 : 24
R/W
Transmit right volume control bit
0x00
Decrement -6dB per step
0(Max.) ~ 16(Min.)
23 : 21
R
Reserved
20 : 16
R/W
Transmit left volume control bit
0x00
Decrement -6dB per step
0(Max.) ~ 16(Min.)
15 : 13
R
Reserved
12 : 8
R/W
Receive right volume control bit
0x00
Decrement -6dB per step
0(Max.) ~ 16(Min.)
7:5
R
Reserved
4:0
R/W
Receive left volume control bit
0x00
Decrement -6dB per step
0(Max.) ~ 16(Min.)
*** It is reflected only when Transmit/Receive volume control enable bit has been set in I2S Mode
register.
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167
CANTUS
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17 USB DEVICE
CANTUS has a built-in USB device that supports 1.1 full-speed (12Mbps) and consists of 5
endpoints.
The USB device supports USB protocol using hardware, and also supports automatic data retry,
data toggle, and power management (suspend and resume) functions.
Key Features
- USB 1.1 Full Speed (12Mbps)
- Supports 5 endpoints.
- Supports USB protocol using hardware.
- Supports Suspend and Resume signaling.
Endpoint
0
1
2
3
4
168
Table 17-1. Endpoint List
Max Size (bytes)
Direction
16
IN/OUT
64
OUT
64
IN
16
OUT
16
IN
CONFIDENTIAL
Transaction Type
Control
Bulk
Bulk
Interrupt
Interrupt
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17.1 USB Registers Summary
Table 17-2 shows the registers associated with the USB block and the physical addresses used to
access them.
Table 17-2. USB Core Register List
Register
Address
R/W
USBFA
USBPM
USBEPI
USBINT
USBEPIEN
USBINTEN
USBLBFN
USBHBFN
USBIND
USBMP
USBEP0C
USBIC1
USBIC2
USBOC1
USBOC2
USBLBOWC
USBHBOWC
USBEP0
USBEP1
USBEP2
USBEP3
USBEP4
0x80022C00
0x80022C04
0x80022C08
0x80022C10
0x80022C14
0x80022C18
0x80022C1C
0x80022C20
0x80022C24
0x80022C28
0x80022C2C
0x80022C2C
0x80022C30
0x80022C38
0x80022C3C
0x80022C40
0x80022C44
0x80022C48
0x80022C4C
0x80022C50
0x80022C54
0x80022C58
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R/W
R/W
R/W
R/W
R/W
Description
Function address register
Power management register
Endpoint interrupt register
USB interrupt register
Endpoint interrupt enable register
USB interrupt enable register
Frame number1 register
Frame number2 register
Index register
MAXP register
EP0 control register
EP2, 4 IN Control register1
EP2, 4 IN Control register2
EP1, 3 OUT Control register 1
EP1, 3 OUT Control register 2
Low Byte OEP Write count register
High Byte OEP write count register
EP0 FIFO data register
EP1 FIFO data register
EP2 FIFO data register
EP3 FIFO data register
EP4 FIFO data register
Default
Value
0x00
0x00
0x00
0x00
0x1F
0x04
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
USB Function Address Register
This register maintains the USB Device Address assigned by host. The CPU writes the value
received through a SET_ADDRESS descriptor to this register. This value is used for the next token.
USB Power Management Register
This register is used for suspend, resume and signaling. The different bits in this register are
explained at next part.
Note. The CPU should use the USB_INTERRUPT register to poll for suspend, resume and reset
conditions.
USB Interrupt Registers
USB ENDPOINT Interrupt Register
USB Interrupt Register
These registers act as status registers for the CPU when it is interrupted.
The bits in these registers are cleared by the CPU by writing a 1 to each bit that was set.
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USB Interrupt Enable Registers
ENDPOINT Interrupt Enable Register
USB Interrupt Enable Register
If bit = 0, the interrupt is disabled.
If bit = 1, the interrupt is enabled.
Frame Number Registers
There are two registers, FRAME_NUMBER1 and FRAME_NUMBER2, which inform the frame
number received from the HOST.
Index Register
Since the core shall be customized to the customer‟s core specification, the number of endpoints
will be different from design to design. This INDEX register is used to select a specific endpoint
registers, CPU can access the endpoint registers (MAXP, IN CSR 1/2, OUT CSR 1/2,
WRITE_COUNT 1/2) for an endpoint inside the core using the INDEX register.
MAXP Register
This register has the maximum packet size for each endpoint. The packet size is varied in
multiple of 8 bytes.
EP0 Control Register
This register has the control and status bits for Endpoint 0. Since a control transaction involves
both IN and OUT tokens, there is only one CSR register. EP0 CSR is mapped to the IN CSR1
register. (share IN CSR1 and can access by writing index register “0” and read/write IN CSR1)
IN Control Registers
These registers maintain the control and status bits for IN endpoints.
They are split into IN CSR1 and IN CSR2. IN CSR1 maintains the status bits, while IN CSR2
maintains the configuration bits.
Out Control Registers
There are two CSR registers, OUT CSR1 and OUT CSR2, which are used to control OUT
endpoints by the CPU.
Out Write Count Registers
There are two registers, OUT_WRT_CNT1 and OUT_WRT_CNT2, which maintain the write
count. When OUT_PKT_RDY is set for OUT endpoints, these registers maintain the number of
bytes in the packet due to be unloaded by the CPU.
Endpoint FIFO Access Registers
These registers are able to access each Endpoint FIFOs.
170
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17.2 USB Control Registers
USB Function Address Register (USBFA)
Address: 0x8002_2C00
R/W
Bit
Description
CPU
USB
31 : 8
Reserved
7
R/W
R/
ADDUP: ADDR_UPDATE bit.
Clear
The CPU sets this bit whenever it updates the
FUNCTION_ ADDR field in this register. The
FUNCTION_ADDR field is used after the status phase
of a control transfer, which is signaled by the clearing of
the DATA_END bit in the Endpoint 0 CSR.
6:0
R/W
R
FUNADD: FUNCTION_ADDR bit.
The CPU writes the address to these bits.
Default
Value
0
0
USB Power Management Register (USBPM)
Address: 0x8002_2C04
R/W
Default
Bit
Description
Value
CPU
USB
31 : 4
Reserved
3
R
Set
UBRST: USB_RESET bit.
0
The USB sets this bit when Reset signal is received
from host. This bit remains set for as long as the reset
signaling persists on the bus.
2
R/W
R
UBRSUM: USB_RESUME bit.
0
The CPU sets this bit for 10ms (Max. 15ms) to initialize
the resume signal. The USB generates resume
signaling while this bit is set in suspend mode.
1
R
R/W
UBSPDMOD: SUSPEND_MODE bit.
0
This bit is set by the USB when is enters suspend
mode.
It is cleared under the following conditions:
- The CPU clears the UC_RESUME bit by writing 0,
to end remote resume signaling.
- The resume signal from host is received.
0
R/W
R
UBENSPD : ENABLE_SUSPEND bit.
0
= 1 Enable Suspend mode
= 0 Disable Suspend mode (Default)
If this bit is zero, the USB device will not enter suspend
mode.
To enter a suspend mode, set the USBENSPD bit to 1. This mode shuts down the USB PHY when
no transaction is received to save power.
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USB Endpoint Interrupt Register (USBEPI)
Address: 0x8002_2C08
R/W
Bit
Description
CPU
USB
31 : 5
Reserved
4
R/
Set
EP4INT: EP4 Interrupt bit. (Interrupt in mode)
Clear
This bit corresponds to the endpoint 4 interrupt.
Interrupt occurs when the following conditions are
satisfied.
- ICIPR(In Control 1 In Packet Ready) bit is cleared
- FIFO is flushed
- ICSTSTAL(In Control 1 Sent Stall) is set
3
R/
Set
EP3INT: EP3 Interrupt bit. (Interrupt out mode)
Clear
This bit corresponds to the endpoint 3 interrupt.
The USB sets this bit under the following conditions:
- Sets OCOPR(Out Control 1 Out Packet Ready) bit
- Sets OCSTSTAL(Out Control 1 Sent Stall) bit
2
R/
Set
EP2INT: EP2 Interrupt bit. (Bulk in mode)
Clear
This bit corresponds to the endpoint 2 interrupt
The USB sets this bit under the following conditions:
- ICIPR(In Control 1 In Packet Ready) bit is cleared
- FIFO is flushed
- ICSTSTAL(In Control 1 Sent Stall) is set
1
R/
Set
EP1INT: EP1 Interrupt bit. (Bulk out mode)
Clear
This bit corresponds to the endpoint 1 interrupt.
The USB sets this bit under the following conditions:
- Sets OCOPR(Out Control 1 Out Packet Ready) bit
- Sets OCSTSTAL(Out Control 1 Sent Stall) bit
0
R/
Set
EP0INT: EP0 Interrupt bit. (Control mode)
Clear
This bit corresponds to the endpoint 0 interrupt.
The USB sets this bit under the following conditions:
1. EP0OPR bit is set.
2. EP0IPR bit is cleared
3. EP0STSTAL bit is set
4. EP0STED bit is set
5. EP0DED bit is cleared (Indicates End of control
transfer)
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CONFIDENTIAL
Default
Value
0
0
0
0
0
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USB Interrupt Register (USBINT)
Address: 0x8002_2C10
R/W
Bit
Description
CPU
USB
31 : 3
Reserved
2
R/
Set
RSTINT: USB Reset Interrupt bit.
Clear
USB sets this bit, when it receives reset signaling.
1
R/
Set
RSUMINT: Resume Interrupt bit.
Clear
USB sets this bit when a resume signaling is received
while in suspend mode.
If the resume is due to a USB reset, then the CPU is
first interrupted with a RESUME interrupt. Once the
clocks resume and the SE0 condition persists for 3ms,
USB RESET interrupt will be asserted.
0
R/
Set
SPDINT: Suspend Interrupt bit
Clear
The USB sets this bit when it receives suspend
signalizing.
This bit is set whenever there is no activity for 3ms on
the bus. Thus, if the CPU does not stop the clock after
the first suspend interrupt, it will be continue to be
interrupted every 3ms as long as there is no activity on
the USB bus.
This interrupt is disabled by default.
Endpoint Interrupt Enable Register (USBEPIEN)
Address: 0x8002_2C14
Bit
R/W
Description
31 : 5
R
Reserved
4
R/W
EP4INTEN : Endpoint 4 Interrupt enable bit
3
R/W
EP3INTEN : Endpoint 3 Interrupt enable bit
2
R/W
EP2INTEN : Endpoint 2 Interrupt enable bit
1
R/W
EP1INTEN : Endpoint 1 Interrupt enable bit
0
R/W
EP0INTEN : Endpoint 0 Interrupt enable bit
USB Interrupt Enable Register (USBINTEN)
Address: 0x8002_2C18
Bit
R/W
Description
31 : 3
R
Reserved
2
R/W
RSTINTEN : USB RESET Interrupt enable bit
1
R
Reserved
0
R/W
SPDINTEN : SUSPEND Interrupt enable bit
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CONFIDENTIAL
Default
Value
0
0
0
Default Value
1
1
1
1
1
Default Value
1
0
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USB Low Byte Frame Number Register (USBLBFN)
Address: 0x8002_2C1C
Bit
R/W
Description
31 : 8
R
Reserved
7:0
R/W
FRAME_NUMBER1 register
It informs the lower byte of frame number
Default Value
0x00
USB High Byte Frame Number Register (USBHBFN)
Address: 0x8002_2C20
Bit
R/W
Description
31 : 8
R
Reserved
7:0
R/W
FRAME_NUMBER2 register
It informs the higher byte of frame number
Default Value
0x00
USB Index Register (USBIND)
Address: 0x8002_2C24
Bit
R/W
Description
31 : 3
R
Reserved
2:0
R/W
Index register
In indicates a certain endpoint for MAXP, IN CSR 1/2,
OUT CSR 1/2, OUT FIFO WRITE COUNT 1/2
register.
000 : Endpoint 0 001 : Endpoint 1
010 : Endpoint 2 011 : Endpoint 3
100 : Endpoint 4 101 : Reserved
110 : Reserved
111 : Reserved
USB MAXP Register (USBMP)
Address: 0x8002_2C28h
Bit
R/W
31 : 8
R
Reserved
7:0
R/W
Max. FIFO Size
0x01 : MAXP=8
0x02 : MAXP=16
0x04 : MAXP=32
0x08 : MAXP=64
174
Description
CONFIDENTIAL
Default Value
000
Default Value
0x00
Advanced Digital Chips, Inc
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USB EP0 Control Register (USBEP0C)
Address: 0x8002_2C2C
R/W
Bit
Description
CPU
USB
31 : 8
R
Reserved
7
Clear
EP0SUEC: EP0 Set Up End Clear bit.
The CPU writes a 1 to this bit to clear EP0STED (Bit4).
6
Clear
EP0OPRC: EP0 Out Packet Ready Clear bit.
The CPU writes a 1 to this bit to clear EP0OPR (Bit0).
5
Set
Clear EP0SDSTAL: EP0 Send Stall bit.
The CPU writes a 1 to this bit at the same time it clears
EP0OPR (Bit0), if it decodes an invalid token.
The USB issues a STALL handshake to the current
control transfer.
The CPU writes a 0 to end the STALL condition.
4
R
Set
EP0STED: EP0 Setup End bit. This is a READ ONLY bit.
The USB sets this bit when a control transfer ends
before EP0DED (Bit3) is set.
The CPU clears this bit by writing a 1 to the EP0SUEC
(Bit7).
When the USB sets this bit, an interrupt is generated to
the CPU.
When such a condition occurs, the USB flushes the
FIFO, and invalidates CPU access to the FIFO. When
CPU access to the FIFO is invalidated, this bit is
cleared.
3
Set/R
Clear EP0DED: EP0 Data End bit.
The CPU sets this bit:
1. after loading the last packet of data into the FIFO,
at the same time EP0IPR (Bit1) is set.
2. while it clears EP0OPR (Bit0) after unloading the
last packet of data.
3. for a zero length data phase, when it clears
EP0OPR (Bit0) and sets EP0IPR (Bit1)
2
Clear/
Set
EP0STSTAL: Sent Stall bit.
R
The USB sets this bit if a control transaction is ended
due to a protocol violation An interrupt is generated
when this bit is set.
1
Set/R
Clear EP0IPR: EP0 In Packet Ready bit.
The CPU sets this bit after writing a packet of data into
ENDPOINT 0 FIFO.
The USB clears this bit once the packet has been
successfully sent to the host.
An interrupt is generated when the USB clears this bit,
so the CPU can load the next packet.
For a zero length data phase, the CPU sets this bit and
EP0DED (Bit3) at the same time.
0
R
Set
EP0OPR: EP0 Out Packet Ready bit. This is a READ
ONLY bit.
The USB sets this bit once a valid packet is written to
the FIFO. An interrupt is generated when the USB sets
this bit. The CPU clears this bit by writing a 1 to the
EP0OPRC (Bit6).
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Default
Value
0
0
0
0
0
0
0
0
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USB IN Control 1 Register (USBIC1)
Address: 0x8002_2C2C
R/W
Bit
Description
CPU
USB
31 : 7
R
Reserved
6
Set
R/Clea ICCDT: In Control 1 Clear Data Toggle bit.
r
When the CPU writes a 1 to this bit, the data toggle bit
is cleared. This is a write-only bit.
5
R/
Set
ICSTSTAL: In Control 1 Sent Stall bit.
Clear
The USB sets this bit when a STALL handshake is
issued to an IN token, due to the CPU setting
ICSDSTAL bit (Bit4). When the USB issues a STALL
handshake, ICIPR (Bit0) is cleared.
The CPU clears by writing 0.
4
R/W
R
ICSDSTAL: In Control 1 Send Stall bit.
The CPU writes a 1 to this bit to issue a STALL
handshake to the USB.
The CPU clears this bit to end the STALL condition.
3
R/Set
Clear ICFFLU: In Control 1 FIFO Flush bit.
The CPU sets this bit if it intends to flush the IN FIFO.
This bit is cleared by the USB when the FIFO is
flushed. The CPU is interrupted when this happens. If a
token is in progress, the USB waits until the
transmission is complete before the FIFO is flushed. If
two packets are loaded into the FIFO, only the top-most
packet (one that was intended to be sent to the host) is
flushed, and the corresponding ICIPR bit (Bit0) for that
packet is cleared.
2
Reserved
1
R
Set
ICFNE: In Control 1 FIFO Not Empty bit.
Indicated there is a packet of data in FIFO
0: No Packet in the FIFO.
1: 1 Packet in the FIFO
0
Set /
Clear ICIPR: In Control 1 In Packet Ready bit.
R
The CPU sets this bit after writing a packet into the
FIFO.
The USB clears this bit once the packet has been
successfully sent to the host.
An interrupt is generated when the USB clears this bit,
so the CPU can load the next packet. While this bit is
set, CPU will not be able to write to the FIFO.
If the ICSDSTAL bit (Bit4) is set by the CPU, this bit
cannot be set.
USB IN Control 2 Register (USBIC2)
Address: 0x8002_2C30
R/W
Bit
Description
CPU
USB
31 : 8
R
Reserved
7
R/W
R
ICASET: In Control 2 Auto Set bit.
If set, whenever the CPU writes data as MAXP length,
ICIPR will automatically be set by the USB core, without
any intervention from CPU.
If the CPU writes less than MAXP data, then IPIPR bit
has to be set by the CPU.
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CONFIDENTIAL
Default
Value
0
0
0
0
0
0
0
Default
Value
0
Advanced Digital Chips, Inc
Ver 2.04
6
5
4:0
CANTUS
R/W
R
Reserved
ICMODIN: In Control 2 Mode In bit.
This bit allows the direction of endpoint programmable.
1 = Configures Endpoint Direction as IN.
0 = Configures Endpoint Direction as OUT.
Reserved
USB Out Control Register 1 (USBOC1)
Address: 0x8002_2C38
R/W
Bit
Description
CPU
USB
31 : 8
R
Reserved
7
R/W
R
OCCDT: Out Control 1 Clear Data Toggle bit.
When the CPU writes a 1 to this bit, data toggle
sequence bit is reset to DATA0.
6
Clear/
Set
OCSTSTAL: Out Control 1 Sent Stall bit.
R
The USB sets this bit when an OUT token is ended with
a STALL handshake.
The USB issues a stall handshake to the host if it sends
data more than MAXP length for the OUT TOKEN.
CPU clears this bit by writing a 0.
5
W/R
R
OCSDSTAL: Out Control 1 Send Stall bit.
The CPU writes 1 to this bit to issue a STALL
handshake to the USB. The CPU clears this bit by
writing 0 to end the STALL condition.
4
R/W
Clear OCFFLU: Out Control 1 FIFO Flush bit.
The CPU writes 1 to flush FIFO and write 0 to stop the
flushing the FIFO. This bit can be set only when
OCCPR bit (Bit0) is set. The packet due to be unloaded
by CPU will be flushed.
3:2
Reserved
1
R
R/W
OCFFUL: Out Control 1 FIFO Full bit.
Indicates no more packets can be accepted.
0: No Packet in the FIFO
1: 1 Packet in the FIFO
0
R/
Set
OCOPR: Out Control 1 Out Packet Ready bit.
Clear
The USB sets this bit once it has loaded a packet of
data into the FIFO.
Once the CPU read the FIFO for the entire packet, this
bit should be cleared by CPU.
The CPU clears by writing 0.
USB OUT Control Register 2 (USBOC2)
Address: 0x8002_2C3C
R/W
Bit
Description
CPU
USB
31 : 8
R
Reserved
7
R/W
R
OCACLR: Out Control 2 Auto Clear bit.
If set, whenever the CPU reads data from the OUT
FIFO, OCOPR will automatically be cleared by the
core, without any intervention from CPU.
6:0
Reserved
Advanced Digital Chips, Inc.
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0
1
Default
Value
0
0
0
0
0
0
Default
Value
0
0
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USB Low Byte Out Write Count Register (USBLOWC)
Address: 0x8002_2C40
Bit
R/W
Description
31 : 8
R
Reserved
7:0
R/W
Low Byte OEP write count register
It maintains the lower byte of write count.
USB High Byte Out Write Count Register (USBHBOWC)
Address: 0x8002_2C44
Bit
R/W
Description
31 : 8
R
Reserved
7:0
R/W
High Byte OEP write count register
It maintains the higher byte of write count.
178
CONFIDENTIAL
Default Value
0x00
Default Value
0x00
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EP0 FIFO Data Register (USBEP0)
Address: 0x8002_2C48
Bit
R/W
Description
31 : 8
R
Reserved
7:0
R/W
EP0 FIFO Data Register
Default Value
0x00
EP1 FIFO Data Register (USBEP1)
Address: 0x8002_2C4C
Bit
R/W
Description
31 : 8
R
Reserved
7:0
R/W
EP1 FIFO Data Register
Default Value
0x00
EP2 FIFO Data Register (USBEP2)
Address: 0x8002_2C50
Bit
R/W
Description
31 : 8
R
Reserved
7:0
R/W
EP2 FIFO Data Register
Default Value
0x00
EP3 FIFO Data Register (USBEP3)
Address: 0x8002_2C54
Bit
R/W
Description
31 : 8
R
Reserved
7:0
R/W
EP3 FIFO Data Register
Default Value
0x00
EP4 FIFO Data Register (USBEP4)
Address: 0x8002_2C58
Bit
R/W
Description
31 : 8
R
Reserved
7:0
R/W
EP4 FIFO Data Register
Default Value
0x00
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18 KEYSCAN
CANTUS has a built-in Key Scan Controller that can control up to 4x4 key matrices. The Key
Scan controller supports setting the scan period.
Key Features
- Scan Mode. (Key press, Key press / release) support
- Scan Period support
- Binary format and hexadecimal format support
I/O Port
Control
Signals
Control
Signals
Output Port
Controller
ROW
Output Ports
Input Port
Controller
Column
Input Ports
Key PAD
Main Controller
APB BUS
Interrupt
Request
Key Values
Scanned
Key Values
Figure 18-1 Key Scan Block Diagram
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18.1 Key Scan Matrix Circuit
Figure 18-2 4 x 4 Key Matrix
When SW is pressed, the corresponding bit is set to “1” and the interrupt occurs. When the key
scan circuit is configured, diodes should be connected to the scan output port (ROWxpin). If there
is no diode, key values are not recognized when two or more switches on the same column are
pressed.
18.2 Key Scan Mode and Interrupt
In Key Press mode, interrupt occurs only when the switch is pressed, resulting in the changes of
KSD1 and KSD2 register values.
In Key Press/Release mode, interrupt occurs both when the switch is pressed and when it is
released, resulting in the changes of KSD1and KSD2 register values.
SW01 pressed
SW02
pressed
Figure 18-3 Key Scan Time Diagram
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18.3 Key Scan Control Registers
Key Scan Control Register (KSCTRL)
Address: 0x8002_3000
Bit
R/W
Description
31 : 3
R
Reserved
2
R/W
Key Scan Mode Select bits
0 : Key press mode
1 : Key press / release mode
1
R
Reserved
0
R/W
Key Scan Enable bit
0: Scan Disable
1: Scan Enable
Key Scan Counter Register (KSCNT)
Address: 0x8002_3004
Bit
R/W
Description
31 : 16
R
Reserved
15 : 0
R/W
Scan clock divide ratio setting bits.
Scanning Frequency 
0
Default Value
0xFFFF
f PCLK
11  ( KSCNT  1)
Key Scan Data 1 Register (KSD1)
Address: 0x8002_3008
Bit
R/W
Description
31 : 16
R
Reserved
15
R
SW33
( When pressed, high level, otherwise low level)
14
R
SW32
13
R
SW31
12
R
SW30
11
R
SW23
10
R
SW22
9
R
SW21
8
R
SW20
7
R
SW13
6
R
SW12
5
R
SW11
4
R
SW10
3
R
SW03
2
R
SW02
1
R
SW01
0
R
SW00
*** This register shows the binary code value to identify which key is pressed.
182
Default Value
0
CONFIDENTIAL
Default Value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
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Ver 2.04
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Key Scan Data 2 Register (KSD2)
Address: 8002 300Ch
Bit
R/W
31:5
R
4: 0
R
Description
Default Value
Reserved
Scanned Switch value (Represented as hexadecimal
0x00
value)
*** Represents Key Scan Data 1 Register value as a hexadecimal value (as 0x4, in case of
SW03)
*** (Note) When two or more keys are pressed simultaneously, this register is set to “0.”
*** This register shows hexadecimal value from 0x0 to 0xF.
*** If two or more keys are pressed simultaneously, a 0 value will be shown.
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19 REAL TIMER CLOCK
CANTUS has RTC with separate power supply. The RTC operates using 32.768kHz clock, and
allows setting the registers for year, month, date, hour, minute and second and reading the current
time. RTC interrupts can be set as by the units of 0.25 sec., 0.5 sec., 2 sec., 4 sec., 8 sec., 16 sec.,
2 min., 4 min., 8min., 16 min., 2 hrs., 4 hrs., 2 days, and 4 days.
Key Features
- Separate power supply
- Supports lead years
- Generates periodic interrupts: 0.25 sec. ~ 4 days
184
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19.1 RTC Control Registers
Real Time Counter Control Register (RTCCTRL)
Address: 0x8002_3800
Bit
R/W
Description
Default Value
31 : 6
R
Reserved
5
R
RTC Control Register Update
0
0 : Update
1 : Not Yet Update
When Update bit is generated, it indicates that RTC
setting has been transferred.
4
R/W
Test Mode
0
0 : Normal Mode 1 : RTC Test Mode(Fast)
3:0
R/W
RTC Interrupt Select
0000
0000 : No Interrupt
0001 : Alarm Interrupt
0010 : 0.25 Sec
0011 : 0.5 Sec
0100 : 2 Sec
0101 : 4 Sec
0110 : 8 Sec
0111 : 16 Sec
1000 : 2 Min
1001 : 4 Min
1010 : 8 Min
1011 : 16 Min
1100 : 2 Hour
1101 : 4 Hour
1110 : 2 Day
1111 : 4 Day
*** In order to set RTC Interrupt Select register and generate interrupt, RTC Interrupt Enable bit in
Wake-Up Control register among Power Management Control registers should be activated.
Real Time Counter Sec Register (RTCSEC)
Address: 0x8002_3804
Bit
R/W
Description
31 : 7
R
Reserved
6
R
RTC Time Counter Register Update
0 : Update 1 : Not Yet Update
When Update bit is generated, it indicates that RTC
setting has been transferred.
5:0
R/W
Sec (0~59)
*** Time Counter register is updated when RTCSEC register is written.
*** Among Timer Counter registers, RTCSEC register should be handled last.
Advanced Digital Chips, Inc.
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Default Value
0
0x00
185
CANTUS
Ver 2.04
Real Time Counter Min Register (RTCMIN)
Address: 0x8002_3808
Bit
R/W
Description
31 : 6
R
Reserved
5:0
R/W
Min (0~59)
Default Value
0x00
Real Time Counter Hour Register (RTCHOUR)
Address: 0x8002_380C
Bit
R/W
Description
31 : 5
R
Reserved
4:0
R/W
Hour (0~23)
Default Value
0x00
Real Time Counter Day Register (RTCDAY)
Address: 0x8002_3810
Bit
R/W
Description
31 : 5
R
Reserved
4:0
R/W
Day (1~31)
Default Value
0x01
Real Time Counter Week Register (RTCWEEK)
Address: 0x8002_3814
Bit
R/W
Description
31 : 3
R
Reserved
2:0
R/W
Week (0~6)
Default Value
0x4
Real Time Counter Week Register (RTCMONTH)
Address: 0x8002_3818
Bit
R/W
Description
31 : 4
R
Reserved
3:0
R/W
Month (1~12)
Default Value
0x1
Real Time Counter Year Register (RTCYEAR)
Address: 0x8002_381C
Bit
R/W
Description
31 : 7
R
Reserved
6:0
R/W
Year (0~99)
Default Value
0x04
186
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
Real Time Alarm Register (RTCALM)
Address: 0x8002_3820
Bit
R/W
31 : 24
R
Reserved
23 : 21
R
Reserved
20 : 16
W
Hour(0~23)
15 : 14
R
Reserved
13 : 8
W
Min(0~59)
7:6
R
Reserved
5:0
W
Sec(0~59)
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CANTUS
Description
CONFIDENTIAL
Default Value
0x00
0x00
0x00
187
CANTUS
Ver 2.04
20 14-BIT VOICE CODEC
CANTUS has built-in 14-bit Sigma-Delta Voice Codec. Sigma-Delta A/D is configured with PreAmplifier, Sigma-Delta Modulator and Decimation Filter, and Sigma-Delta D/A with Interpolation
Filter, Sigma-Delta Modulator and Analog Post-Filter.
Key Features
- 14-bit Sigma-Delta A/D with 75dB SNR
- 14-bit Sigma-Delta D/A with 80dB SNR
- Digital Input/Output 2‟s Complement Format
- Sampling Frequency Max. 11.025KHz
- Record Gain supported using Pre-Amplifier with External Resisters
- A/D, D/A Converter Individual Power On/Off
- D/A Converter Analog Output Mute Function
Block Diagram
R2
VOA
0.1uF
Analog
Input 0
R1
Analog Input 1~3
VGA
Opa
AIN
3
0.1uF
Analog
Output
AOUT
50K
Post-Filter
Decimation
Filter
Sigma-Delta
Modulator
Interpolation
Filter
20pF
VREF
10uF
Opa
Sigma-Delta
Modulator
Controller
Logic
Reference
0.1uF
Bus Interface
APB Bus
14-bit data
I2S
Figure 20-1 Voice Codec Block Diagram
The record gain is set by R1 and R2 ratio. The gain of recording (ADC) is following simple equation.
Gain = R2/R1
(R1 = 50kOhm, R2=50kOhm for 0dB, R2=500kOhm for 20dB Gain)
188
CONFIDENTIAL
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Ver 2.04
CANTUS
ADC/DAC Signal Level
This signal has the voltage range of +1/-1 on the basis of Analog Virtual Ground (1.65V), and its
digital code is 14-bit 2‟s complement.
V
Vmax 2.65
0x1FFF
1.65
0x0000
0x3FFF
Vmin 0.65
0x2000
14-bit
2's complement
T
Figure 20-2 ADC/DAC Signal Level
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CONFIDENTIAL
189
CANTUS
Ver 2.04
20.1 Voice Codec Control Registers
Voice Codec Control Registers ( VOICECTRL )
Address: 0x8002_2400
Bit
R/W
Description
31 : 3
R
Reserved
2
R/W
Data Select
0 : CPU Data
1 : I2S Data
1
R/W
Interrupt Enable
0 : Disable
1 : Enable
0
R/W
Voice Codec Enable
0 : Disable
1 : Enable
Default Value
0
0
0
Voice Codec Power Registers ( VOICEPW )
Address: 0x8002_2404
Bit
R/W
Description
Default Value
31 : 8
R
Reserved
7:5
R/W
ADC Input Select bits
000
000 : VGA
001 : AIN1
010 : AIN2
011 : AIN3
1xx : Reserved
4
R/W
DAC Mute Control bit
0
0 : Mute On
1 : Mute Off
3
R/W
Reference Power Control bit
0
0 : Power Off
1 : Power On
2
R/W
DAC Power Control bit
0
0 : Power Off
1 : Power On
1
R/W
ADC Power Control bit
0
0 : Power Off
1 : Power On
0
R/W
Voice Codec Reset
0
0 : Reset
1 : Release
*** Power-On Sequence
- Reference Power On  Time interval  ADC Power On  DAC Power On
(After Reference Power On, a certain period of stabilization time (time interval) is needed.)
*** Power-Off Sequence
- ADC Power Off  DAC Power Off  Reference Power Off
*** DAC Mute Function
- If the MUTE Control bit is „On‟, DAC output is muted and go analog ground level. To
decrease the click and pop noise, forcing the zero data input during over 10Fs cycle before
MUTE on.
190
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Ver 2.04
CANTUS
Voice Codec DAC Data Registers ( VOICEDAC )
Address: 0x8002_2408
Bit
R/W
Description
31 : 14
R
Reserved
13 : 0
W
DAC 14-bit Data (2‟s Complement Format)
Default Value
-
Voice Codec ADC Data Registers ( VOICEADC )
Address: 0x8002_240C
Bit
R/W
Description
31 : 14
R
Reserved
13 : 0
R
ADC 14-bit Data (2‟s Complement Format)
Default Value
0x0000
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CONFIDENTIAL
191
CANTUS
Ver 2.04
21 ISP (IN SYSTEM PROGRAMMER)
ISP has compatibility between “SPI Mode 00” and “SPI Mode 11.” ISP_CLK period should be 8
times XIN or more. (Tcss/Tcsh/Tsck Period > 8 x XIN Period)
TCSS
TCSH
ISP_nCS
TSCK
ISP_CLK
(Mode 0)
ISP_CLK
(Mode 3)
ISP_IN
MSB
ISP_OUT
Figure 21-1 SPI Modes Supported
192
CONFIDENTIAL
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Ver 2.04
CANTUS
21.1 ISP Command Set
Internal NOR Flash Memory is accessible through ISP command. Therefore, NOR Flash Memory
can be erased or programmed using ISP‟ Read/Write commands. Auto Address Increment
Programming command automatically increases NOR Flash Memory address using hardware, in
order to increase the speed of NOR Flash Memory programming.
Table 21-1 ISP Command Set
Bus cycle
Cycle Type /
Operation
Read
Write
Chip ID
Status
Control
Auto Address
Increment
Programming
1 cycle
2 cycle
3 cycle
4 cycle
5 cycle
6 cycle
SI
SO
SI
SO
SI
SO
SI
SO
SI
SO
SI
SO
83h
84h
90h
93h
94h
Z
Z
Z
Z
Z
A2
A2
X
X
DI
Z
Z
ID
ST
Z
A1
A1
-
Z
Z
-
A0
A0
-
Z
Z
-
X
DI
-
X
Z
-
X
-
DO
-
A4h
Z
A2
Z
A1
Z
A0
Z
DI
Z
-
-
SI : Serial Input,
SO : Serial Output
X : Dummy cycles
- : Cycles are not necessary
A2 : Address[23:16]
A1 : Address[15:8]
A0 : Address[7:0]
DI : Data input [7:0]
DO
: Data output[7:0]
ID : Device Identification (0x22)
ST : Status
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CONFIDENTIAL
193
CANTUS
Ver 2.04
21.2 Read Command
This command is used for reading the built-in NOR Flash Memory. When NOR Flash Memory
address is entered after the Read command, NOR Flash data value are read after Dummy Cycle.
In order for read continuous NOR Flash Memory area, only the Start address is needed to be
entered. Then, the Flash Memory area is read continuously. When Read command is executed,
NOR Flash Memory address is automatically increased.
Start
SI
83h
SI
Address[23:16]
SI
Address[15:8]
SI
Address[7:0]
SO
Dummy Cycle
SO
Data Out
N
End?
Y
End
Figure 21-2 Read Command Flow chart
194
CONFIDENTIAL
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Ver 2.04
CANTUS
21.3 Write Command
To erase or program NOR Flash Memory or to read NOR Flash ID, a command defined by NOR
Flash Memory should be written. Write command should be executed referring to NOR Flash
Command Definitions Table and, before executing the Write command, Write Enable bit should be
activated with Control command.
Start
SI
84h
SI
Address[23:16]
SI
Address[15:8]
SI
Address[7:0]
SO
Data In
End
Figure 21-3 Write Command Flow chart
21.4 Device ID Command
With Device ID command, it is possible to check CANTUS power supply status and ISP cable
status. When “0x22” is read, it indicates that ISO connection has been normally established.
Start
SI
90h
SO
Chip ID
End
Figure 21-4 Device ID Command Flow chart
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CONFIDENTIAL
195
CANTUS
Ver 2.04
21.5 Status/Control Command
During ISP operation, ISP controller status can be checked with Status command and controlled
with Control command.
Bit
31 : 8
7
R/W
R
R
6
5
R
R
4
R/W
3
R/W
2
R/W
1
R/W
0
R/W
Table 21-2 ISP Status/Control Register
Description
Reserved
AAI Programming ready bit
0 : Busy
1 : Ready
Reserved
AAI Programming status bit
0 : Random program mode
1 : Auto address increment programming mode
AAI Programming enable bit
0 : AAI Programming disabled
1 : AAI Programming enabled
Write enable bit
0 : Write disabled
1 : Write enabled
System reset bit
0 : System reset
1 : System active
Processor reset bit
0 : Processor reset
1 : Processor active
ISP enable bit
0 : ISP enabled
1 : ISP disabled
Start
0
0
0
0
0
0
Start
SI
93h
SI
94h
SO
Status
SI
Control
End
Default Value
1
End
Figure 21-5 Status/Control Command Flow chart
196
CONFIDENTIAL
Advanced Digital Chips, Inc
Ver 2.04
CANTUS
21.6 AAI Programming Command
AAI Programming command is used for programming continuous NOR Flash Memory area,
which is automatically executed by ISP controller. Therefore, Start address needs to be entered
once and then only AAI Programming command and data are entered. At this time, AAI
Programming status bit is kept in Auto address increment programming mode until the command
execution is completed, and the Flash Memory address is automatically increased. While AAI
Programming command is executed, it is possible to check whether Flash Memory programming is
completed or not, through AAI Programming Ready bit in Status command. In order to execute AAI
Programming command, AAI Programming Enable bit should be activated with Control command.
Start
SI
A4h
SI
Address[23:16]
SI
Address[15:8]
SI
Address[7:0]
SO
Data In
End?
N
N
Y
End
Ready?
Y
SI
A4h
Figure 21-6 AAI Programming Command Flow chart
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CONFIDENTIAL
197
CANTUS
Ver 2.04
22 ELECTRICAL CHARACTERISTICS
22.1 DC Electrical Characteristics
Table 22-1 DC Electrical Characteristics
Parameter
Symbol
Conditions
Min
I/O Supply Voltage
DVDD
3.0
Junction Temperature
TJ
-40
Operation Temperature
TA
-40
Input Low Voltage
VIL
-0.5
Input High Voltage
VIH
2.0
Schmitt Trigger Hysteresis
VHYS
0.34
Input leakage current
II
VIN = VSS or
–10
3.6V
Input Current with Pull Down Resistor
IIL
VIN = DVDD
+25
Input Current with Pull Up Resistor
IIH
VIN = 0
-26
Output Low Voltage
VOL
0
Output High Voltage
VOH
2.4
MOSC Oscillator Frequency
fOSC
2
ROSC Oscillator Frequency
fRTC
Operating current
Normal
f HCLK =
mode
IDD
96MHz
Idle mode
Deep Idle mode current
IDD
fOSC = Stop
Sleep mode current
IDD
(Low Power Domain)
198
CONFIDENTIAL
Typ
3.3
25
25
0.38
+58
-46
32.768
70
500
50
Max
3.6
125
85
0.8
5.5
0.41
+10
Unit
V
ºC
ºC
V
V
V
uA
+109
-74
0.4
3.6
15
uA
uA
V
V
MHz
KHz
mA
100
mA
uA
uA
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Ver 2.04
CANTUS
22.2 LDO100 Voltage Regulator Electrical Characteristics
Table 22-2 LDO100 Electrical Characteristics
Parameter
Min
Typ
Supply Voltage
3.0
3.3
Voltage Output
1.65
1.8
Current Output
Current Consumption
30
Stop Current
Setup Time
Max
3.6
1.95
100
1.0
50
Unit
V
V
mA
uA
uA
usec
22.3 LDO50 Voltage Regulator Electrical Characteristics
Table 22-3 LDO50 Electrical Characteristics
Parameter
Min
Typ
Supply Voltage
3.0
3.3
Voltage Output
1.65
1.8
Current Output
Current Consumption
30
Stop Current
Setup Time
Max
3.6
1.95
50
1.0
50
Unit
V
V
mA
uA
uA
usec
Max
600
10
Unit
V
nsec
uA
22.4 POR Electrical Characteristics
Table 22-4 POR Electrical Characteristics
Parameter
Min
Typ
Start Voltage
1.6
Width of Reset
200
300
Current Consumption
5
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199
CANTUS
Ver 2.04
22.5 MOSC Electrical Characteristics
Table 22-5 MOSC Electrical Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Crystal Oscillator Frequency
2
15
MHz
(1)
Rfb
2
Mohm
(1)
RS
0
ohm
(1)
CL
Equivalent Load Capacitance
10
12.5
pF
Duty cycle
40
50
60
%
IOSC
Current Consumption
Active mode
500
uA
Standby mode
1
uA
Notes: 1. The values of Rfb, Rs, and CL may be further refined to meet the frequency requirements of
the system.
Symbol
22.6 ROSC Electrical Characteristics
Table 22-6 ROSC Electrical Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Crystal Oscillator Frequency
32.768
KHz
(1)
Rfb
2
5
Mohm
(1)
RS
0
ohm
(1)
CL
Equivalent Load Capacitance
10
12.5
pF
Duty cycle
40
50
60
%
IOSC
Current Consumption
Active mode
5
uA
Standby mode
1
uA
Notes: 1. The values of Rfb, Rs, and CL may be further refined to meet the frequency requirements of
the system.
Symbol
200
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CANTUS
22.7 PLL Electrical Characteristics
Symbol
Fext
Fout
Tr, Tf
Table 22-7 PLL Electrical Characteristics
Parameter
Conditions
Min
Typ
Input Frequency
2
Output Frequency
5
Output Clock Duty Cycle
40
50
Clock Jitter
Peak-Peak
-150
Frequency Change to Fout
Stable Time
Fout Rise and Fall Time
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CONFIDENTIAL
Max
40
96
60
150
100
Unit
MHz
MHz
%
psec
usec
0.8
nsec
201
CANTUS
Ver 2.04
22.8 Voice Codec Electrical Characteristics
Table 22-8 Voice Codec Electrical Characteristics
(VDDA=3.3V, VDDD=1.8V, Topr=25ºC, Fs=8kHz, 0dB 1kHz Sine Wave Input, Unless otherwise
specified)
Characteristic
Condition
Symbol
Min
Typ
Max
Unit
Resolution
Bit
14
Bits
Sampling Frequency
Fs
8
11.025
KHz
Reference Voltage
Vref
1.2
V
Analog Virtual Ground
Vavg
1.65
V
ADC
Signal to Noise Ratio
SNRadc
70
75
dB
Total Harmonic Distortion
THDadc
-85
-80
dB
Offset Voltage
Vos,adc
±5
mV
Maximum Input Range
Vain,max
2
Vpp
DAC
Signal to Noise Ratio
SNRadc
75
80
dB
Total Harmonic Distortion
THDadc
-88
-83
dB
Offset Voltage
Vos,dac
±5
mV
Maximum Output Range
Vaout,max
2
Vpp
Analog Output Load
Rload
10
KΩ
Power Supply
Supply Voltage
AVDD33
3.0
3.3
3.6
V
Operating Current
Analog
Ivdda
3.7
4.5
mA
Power
Power Down Current
Pass Band
Pass Band Rippler
-3dB
Stop Band Attenuation
Pass Band
Pass Band Ripple
-3dB
Stop Band Attenuation
202
All Power
Down
Ipwdn
Digital Filter - ADC
Fpb,adc
Rpb,adc
F3db,adc
Rsb,adc
Digital Filter -DAC
Fpb,dac
Rpb,dac
Fsb,dac
Rsb.dac
CONFIDENTIAL
10
uA
0.4
±0.44
0.44
-54
Fs
dB
Fs
dB
0.4
±0.3
0.464
-45
Fs
dB
Fs
dB
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Ver 2.04
CANTUS
22.9 Internal Register Electrical Characteristics
Table 22-9 Internal Resistance Electrical Characteristics
Parameter
Min
Typ
Max
Pull-Up Resistance
30
66
130
Pull-Down Resistance
44
71
126
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CONFIDENTIAL
Unit
K
K
203
CANTUS
Ver 2.04
23 PACKAGE DIMENSION
Unit: mm
Figure 23-1 Package Dimension
204
CONFIDENTIAL
Advanced Digital Chips, Inc