Programmable Frequency Scan Waveform Generator AD5932 FEATURES GENERAL DESCRIPTION Programmable frequency profile No external components necessary Output frequency up to 25 MHz Burst-and-listen capability Preprogrammable frequency profile minimizes number of DSP/microcontroller writes Sinusoidal/triangular/square wave outputs Automatic or single pin control of frequency stepping Power-down mode: 20 μA Power supply: 2.3 V to 5.5 V Automotive temperature range: −40°C to +125°C 16-lead, Pb-free TSSOP The AD59321 is a waveform generator offering a programmable frequency scan. Utilizing embedded digital processing that allows enhanced frequency control, the device generates synthesized analog or digital frequency-stepped waveforms. Because frequency profiles are preprogrammed, continuous write cycles are eliminated, thereby freeing up valuable DSP/microcontroller resources. Waveforms start from a known phase and are incremented phase-continuously, which allows phase shifts to be easily determined. Consuming only 6.7 mA, the AD5932 provides a convenient low power solution to waveform generation. The AD5932 outputs each frequency in the range of interest for a defined length of time and then steps to the next frequency in the scan range. The length of time the device outputs a particular frequency is preprogrammed, and the device increments the frequency automatically; or, alternatively, the frequency is incremented externally via the CTRL pin. At the end of the range, the AD5932 continues to output the last frequency until the device is reset. The AD5932 also offers a digital output via the MSBOUT pin. APPLICATIONS Frequency scanning/radar Network/impedance measurements Incremental frequency stimulus Sensory applications Proximity and motion (continued on Page 3) FUNCTIONAL BLOCK DIAGRAM DVDD CAP/2.5V DGND INTERRUPT STANDBY AGND AVDD AD5932 REGULATOR VCC 2.5V BUFFER SYNCOUT BUFFER MSBOUT MCLK SYNC INCREMENT CONTROLLER CTRL DATA 24-BIT PIPELINED DDS CORE INCR FREQUENCY CONTROLLER /24 10-BIT DAC VOUT DATA AND CONTROL FSYNC SCLK CONTROL REGISTER ON-BOARD REFERENCE FULL-SCALE CONTROL COMP 05416-001 SERIAL INTERFACE SDATA Figure 1. 1 Protected by U.S. patent number 6747583; other patents pending. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved. AD5932 TABLE OF CONTENTS Features .............................................................................................. 1 Serial Interface ............................................................................ 15 Applications....................................................................................... 1 Powering up the AD5932 .......................................................... 15 General Description ......................................................................... 1 Programming the AD5932........................................................ 16 Functional Block Diagram .............................................................. 1 Setting Up the Frequency Scan................................................. 17 Revision History ............................................................................... 2 Activating and Controlling the Scan ....................................... 18 Specifications..................................................................................... 4 Outputs from the AD5932 ........................................................ 19 Specifications Test Circuit ........................................................... 5 Applications..................................................................................... 20 Timing Specifications .................................................................. 6 Grounding and Layout .............................................................. 20 Master Clock and Timing Diagrams ......................................... 6 AD5932 to ADSP-21xx Interface ............................................. 20 Absolute Maximum Ratings............................................................ 8 AD5932 to 68HC11/68L11 Interface....................................... 21 ESD Caution.................................................................................. 8 AD5932 to 80C51/80L51 Interface .......................................... 21 Pin Configuration and Function Descriptions............................. 9 AD5932 to DSP56002 Interface ............................................... 21 Typical Performance Characteristics ........................................... 10 Evaluation Board ............................................................................ 22 Terminology .................................................................................... 14 Schematics................................................................................... 23 Theory of Operation ...................................................................... 15 Outline Dimensions ....................................................................... 25 Frequency Profile........................................................................ 15 Ordering Guide .......................................................................... 25 REVISION HISTORY 4/06—Revision 0: Initial Version Rev. 0 | Page 2 of 28 AD5932 GENERAL DESCRIPTION (continued from Page 1) To program the AD5932, the user enters the start frequency, the increment step size, the number of increments to be made, and the time interval that the part outputs each frequency. The frequency scan profile is initiated, started, and executed by toggling the CTRL pin. Note that the AVDD and DVDD are independent of each other and can be operated from different voltages. The AD5932 also has a standby function that allows sections of the device that are not in use to be powered down. The AD5932 is available in a 16-lead, Pb-free TSSOP. The AD5932 is written to via a 3-wire serial interface that operates at clock rates up to 40 MHz. The device operates with a power supply from 2.3 V to 5.5 V. Rev. 0 | Page 3 of 28 AD5932 SPECIFICATIONS AVDD = DVDD = 2.3 V to 5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Table 1. Parameter SIGNAL DAC SPECIFICATIONS Resolution Update Rate VOUT Peak-to-Peak VOUT Offset VMIDSCALE VOUT TC DC Accuracy Integral Nonlinearity (INL) Differential Nonlinearity (DNL) DDS SPECIFICATIONS Dynamic Specifications Signal-to-Noise Ratio Total Harmonic Distortion Spurious-Free Dynamic Range (SFDR) Wide Band (0 to Nyquist) Narrow Band (±200 kHz) Clock Feedthrough Wake-Up Time OUTPUT BUFFER VOUT Peak-to-Peak Output Rise/Fall Time2 VOLTAGE REFERENCE Internal Reference Reference TC2 LOGIC INPUTS 2 Input Current Input High Voltage, VINH Min Y Grade 1 Typ 10 53 0.58 56 0.32 200 ±1.5 ±0.75 LSB LSB 60 −60 Test Conditions/Comments Internal 200 Ω resistor to GND From 0 V to the trough of the waveform Voltage at midscale output dB dBc fMCLK = 50 MHz, fOUT = fMCLK/4096 fMCLK = 50 MHz, fOUT = fMCLK/4096 −52 −70 dBc dBc dBc ms fMCLK = 50 MHz, fOUT = fMCLK/50 fMCLK = 50 MHz, fOUT = fMCLK/50 Up to 16 MHz out From standby DVDD V ns Typically, square wave on MSBOUT and SYNCOUT 1.18 90 1.26 V ppm/°C 0.1 ±2 μA V V V V V V pF −56 −74 −50 1.7 0 −53 12 1.15 Unit Bits MSPS V mV V ppm/°C 50 1.7 2.0 2.8 Input Low Voltage, VINL Input Capacitance, CIN LOGIC OUTPUTS2 Output High Voltage, VOH Output Low Voltage, VOL Floating-State O/P Capacitance POWER REQUIREMENTS AVDD/DVDD IAA IDD IAA + IDD Max 0.6 0.7 0.8 3 DVDD − 0.4 V 0.4 V V pF 5.5 4 2.7 6.7 V mA mA mA 5 DVDD = 2.3 V to 2.7 V DVDD = 2.7 V to 3.6 V DVDD = 4.5 V to 5.5 V DVDD = 2.3 V to 2.7 V DVDD = 2.7 V to 3.6 V DVDD = 4.5 V to 5.5 V ISINK = 1 mA ISINK = 1 mA fMCLK = 50 MHz, fOUT = fMCLK/7 2.3 3.8 2.4 6.2 Rev. 0 | Page 4 of 28 AD5932 Parameter Low Power Sleep Mode 1 2 Y Grade 1 Typ Min Max Unit 20 85 μA 140 240 μA Test Conditions/Comments Device is reset before putting into standby All outputs powered down, MCLK = 0 V, serial interface active All outputs powered down, MCLK active, serial interface active Operating temperature range is as follows: Y version: −40°C to +125°C; typical specifications are at +25°C. Guaranteed by design, not production tested. SPECIFICATIONS TEST CIRCUIT 10nF AVDD 10nF CAP/2.5V COMP REGULATOR 12 SIN ROM 10-BIT DAC VOUT 20pF AD5932 Figure 2. Test Circuit Used to Test the Specifications Rev. 0 | Page 5 of 28 05416-002 100nF AD5932 TIMING SPECIFICATIONS All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and are timed from a voltage level of (VIL + VIH)/2 (see Figure 3 to Figure 6). DVDD = 2.3 V to 5.5 V; AGND = DGND = 0 V; all specifications TMIN to TMAX, unless otherwise noted. Table 2. Parameter 1 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 1 Limit at TMIN, TMAX 20 8 8 25 10 10 5 10 5 3 2 × t1 0 10 × t1 8 × t1 1 × t1 2 × t1 20 Unit ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns typ ns typ ns typ ns typ ns max Conditions/Comments MCLK period MCLK high duration MCLK low duration SCLK period SCLK high time SCLK low time FSYNC to SCLK falling edge setup time FSYNC to SCLK hold time Data setup time Data hold time Minimum CTRL pulse width CTRL rising edge to MCLK falling edge setup time CTRL rising edge to VOUT delay (initial pulse, includes initialization) CTRL rising edge to VOUT delay (initial pulse, includes initialization) Frequency change to SYNC output, each frequency increment Frequency change to SYNC output, end of scan MCLK falling edge to MSBOUT Guaranteed by design, not production tested. MASTER CLOCK AND TIMING DIAGRAMS t1 05416-003 MCLK t2 t3 Figure 3. Master Clock t5 t4 SCLK t7 t6 t8 FSYNC SDATA D15 D14 D2 D1 Figure 4. Serial Timing Rev. 0 | Page 6 of 28 D0 D15 D14 05416-004 t10 t9 AD5932 t12 MCLK CTRL 05416-005 t11 VOUT t13 Figure 5. CTRL Timing CTRL t13 VOUT t14 SYNCOUT (End of Scan) t15 Figure 6. SYNCOUT Timing Rev. 0 | Page 7 of 28 05416-006 SYNCOUT (Each Frequency Increment) AD5932 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to AGND DVDD to DGND AGND to DGND CAP/2.5 V to DGND Digital I/O Voltage to DGND Analog I/O Voltage to AGND Operating Temperature Range Automotive (Y Version) Storage Temperature Range Maximum Junction Temperature TSSOP (4-Layer Board) θJA Thermal Impedance θJC Thermal Impedance Reflow Soldering (Pb-Free) Peak Temperature Time at Peak Temperature Rating −0.3 V to +6.0 V −0.3 V to +6.0 V −0.3 V to +0.3 V −0.3 V to +2.75 V −0.3 V to DVDD + 0.3 V −0.3 V to AVDD + 0.3 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. −40°C to +125°C −65°C to +150°C +150°C 112°C/W 27.6°C/W 300°C 260(+0/−5)°C 10 sec to 40 sec ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 8 of 28 AD5932 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS COMP 1 16 VOUT AVDD 2 15 AGND DVDD 3 CAP/2.5V 4 DGND 5 MCLK 6 11 SDATA SYNCOUT 7 10 CTRL MSBOUT 8 TOP VIEW (Not to Scale) 14 STANDBY 13 FSYNC 12 SCLK 9 INTERRUPT 05416-007 AD5932 Figure 7. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 Mnemonic COMP AVDD 3 DVDD 4 CAP/2.5V 5 6 DGND MCLK 7 SYNCOUT 8 MSBOUT 9 INTERRUPT 10 CTRL 11 SDATA 12 13 SCLK FSYNC 14 STANDBY 15 16 AGND VOUT Description DAC Bias Pin. This pin is used for decoupling the DAC bias voltage to AVDD. Positive Power Supply for the Analog Section. AVDD can have a value from 2.3 V to 5.5 V. A 0.1 μF decoupling capacitor should be connected between AVDD and AGND. Positive Power Supply for the Digital Section. DVDD can have a value from 2.3 V to 5.5 V. A 0.1 μF decoupling capacitor should be connected between DVDD and DGND. Digital Circuitry. Operates from a 2.5 V power supply. This 2.5 V is generated from DVDD using an on-board regulator. The regulator requires a decoupling capacitor of typically 100 nF, which is connected from CAP/2.5V to DGND. If DVDD is equal to or less than 2.7 V, CAP/2.5V can be shorted to DVDD. Ground for All Digital Circuitry. Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The output frequency accuracy and phase noise are determined by this clock. Digital Output for Scan Status Information. User-selectable for end of scan (EOS) or frequency increments through the control register (SYNCOP bit). This pin must be enabled by setting the SYNCOUTEN bit in the control register to 1. Digital Output. The inverted MSB of the DAC data is available at this pin. This output pin must be enabled by setting the MSBOUTEN bit in the control register to 1. Digital Input. This pin acts as an interrupt during a frequency scan. A low-to-high transition is sampled by the internal MCLK, which resets internal state machines. This results in the DAC output going to midscale. Digital Input. Triple function pin for initialization, start, and external frequency increments. A low-to-high transition, sampled by the internal MCLK, is used to initialize and start internal state machines, which then execute the preprogrammed frequency scan sequence. When in auto-increment mode, a single pulse executes the entire scan sequence. When in external increment mode, each frequency increment is triggered by low-to-high transitions. Serial Data Input. The 16-bit serial data-word is applied to this input with the register address first, followed by the MSB to LSBs of the data. Serial Clock Input. Data is clocked into the AD5932 on each falling SCLK edge. Active Low Control Input. This is the frame synchronization signal for the serial data. When FSYNC is taken low, the internal logic is informed that a new word is being loaded into the device. Active High Digital Input. When this pin is high, the internal MCLK is disabled, and the reference DAC and regulator are powered down. For optimum power saving, it is recommended that the AD5932 be reset before it is put into standby, as this results in a shutdown current of typically 20 μA. Ground for All Analog Circuitry. Voltage Output. The analog outputs from the AD5932 are available here. An external resistive load is not required, because the device has a 200 Ω resistor on board. A 20 pF capacitor to AGND is recommended to act as a low-pass filter and to reduce clock feedthrough. Rev. 0 | Page 9 of 28 AD5932 TYPICAL PERFORMANCE CHARACTERISTICS –40 9 TA = 25°C AVDD = 5V MSBOUT, SYNCOUT ENABLED 8 –50 DVDD = 5V 7 SFDR (dBc) DVDD = 3V 4 –60 FOUT = MCLK/50 –65 –70 DVDD = 5V, FOUT = MCLK/7 3 –75 2 FOUT = MCLK/3 0 5 10 15 20 25 30 35 40 45 05416-008 DVDD = 3V, FOUT = MCLK/7 1 05416-011 –80 –85 –90 50 0 5 10 MCLK FREQUENCY (MHz) 20 25 30 35 40 45 50 MCLK FREQUENCY (MHz) Figure 8. Current Consumption (IDD) vs. MCLK Frequency Figure 11. Wide-Band SFDR vs. MCLK Frequency –60 7 TA = 25°C MCLK = 50MHz MSBOUT ON, SYNCOUT ON 5 MSBOUT OFF, SYNCOUT ON 3 MSBOUT OFF, SYNCOUT OFF 2 FOUT = MCLK/50 –70 MSBOUT ON, SYNCOUT OFF 4 AVDD = DVDD = 3V/5V MCLK = 50MHz CREG = 0111 1111 1111 TA = 25°C –65 SFDR (dBc) 6 IDD (mA) 15 FOUT = MCLK/3 –75 –80 –85 05416-009 1 –90 1kHz 100kHz 1MHz 5MHz 15MHz 25MHz 500kHz 10kHz 500kHz 2MHz 10MHz 20MHz FOUT = MCLK/7 0 5 10 15 20 25 30 35 40 45 05416-012 IDD (mA) 5 0 FOUT = MCLK/7 –55 6 0 AVDD = DVDD = 3V/5V MCLK = 50MHz CREG = 0111 1111 1111 TA = 25°C –45 50 MCLK FREQUENCY (MHz) FOUT (Hz) Figure 12. Narrow-Band SFDR vs. MCLK Frequency Figure 9. IDD vs. FOUT for Various Digital Output Conditions –30 3.5 AIDD 3.0 –40 AVDD = DVDD = 3V/5V CREG = 0111 1111 1111 TA = 25°C MCLK = 50MHz 2.5 –50 SFDR (dBc) 2.0 1.5 –60 MCLK = 10MHz –70 1.0 1 2 3 MCLK = 30MHz –80 4 –90 0.001 05416-013 0.5 0 MCLK = 1MHz LEGEND 1. SINE WAVE OUTPUT, INTERNALLY CONTROLLED SWEEP 2. TRIANGULAR OUTPUT, INTERNALLY CONTROLLED SWEEP 3. SINE WAVE OUTPUT, EXTERNALLY CONTROLLED SWEEP 4. TRIANGULAR OUTPUT, EXTERNALLY CONTROLLED SWEEP 05416-010 IDD (mA) DIDD 0.01 0.1 1 10 100 FOUT (MHz) CONTROL OPTION (See Legend) Figure 13. Wideband SFDR vs. FOUT for Various MCLK Frequencies Figure 10. IDD vs. Output Waveform Type and Control Rev. 0 | Page 10 of 28 AD5932 70 90 TA = 25°C AVDD = DVDD = 5V fOUT = FMCLK/4096 65 80 NUMBER OF DEVICES 70 SNR (dB) 60 55 50 60 50 40 30 20 0 10M 20M 30M 40M 05416-017 10 0 50M MCLK FREQUENCY (MHz) 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 40 05416-014 45 V p-p (mV) Figure 14. SNR vs. MCLK Frequency Figure 17. Histogram of VOUT Peak-to-Peak 80 1.25 AVDD = DVDD = 5V 70 60 NUMBER OF DEVICES VREF (V) 1.23 1.21 1.19 50 40 30 20 1.17 –20 0 20 40 60 80 100 05416-018 0 120 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 05416-015 VOFFSET (mV) TEMPERATURE (°C) Figure 15. VREF vs. Temperature Figure 18. Histogram of VOUT Offset 0 2.0 1.9 –10 AVDD = DVDD = 2.3V –20 ATTENUATION (dB) 1.7 AVDD = DVDD = 5V 1.6 1.5 –30 DVDD (on CAP/2.5V) –40 –50 –60 1.4 1.3 05416-016 WAKE-UP TIME (ms) 1.8 1.2 –40 TA = 25°C 100mV p-p RIPPLE NO DECOUPLING ON SUPPLIES AVDD = DVDD = 5V –20 0 20 40 60 80 100 120 AVDD (on VOUT) –70 –80 10 100 1k 10k MODULATING FREQUENCY (Hz) TEMPERATURE (°C) Figure 16. Wake-up Time vs. Temperature Figure 19. PSSR Rev. 0 | Page 11 of 28 100k 05416-019 1.15 –40 10 1M 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 –130 –140 –150 –160 –170 100 0 –10 –20 –30 (dB) –40 –50 –60 –70 1k 10k 05416-023 –80 05416-020 PHASE NOISE AD5932 –90 –100 100k 0 FREQUENCY (Hz) 5M RWB 1K VWB 300 ST 50 SEC FREQUENCY (Hz) Figure 23. fMCLK = 10 MHz, fOUT = 3.33 MHz = fMCLK/3, Frequency Word = 5555555 Figure 20. Output Phase Noise 0 0 –10 –10 –20 –20 –30 –30 –40 (dB) –50 –60 –60 –70 –70 –80 –80 –90 05416-021 –90 –100 –50 0 –100 100k RWB 100 VWB 30 05333-017 (dB) –40 0 160k RWB 100 ST 100 SEC Figure 24. fMCLK = 50 MHz, fOUT = 12 kHz, Frequency Word = 000FBA9 0 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 0 5M VWB 300 05416-025 (dB) 0 –10 05416-022 (dB) Figure 21. fMCLK = 10 MHz, fOUT = 2.4 kHz, Frequency Word = 000FBA9 RWB 1K ST 200 SEC FREQUENCY (Hz) FREQUENCY (Hz) –100 VWB 30 –90 –100 0 1.6M RWB 100 ST 50 SEC VWB 300 FREQUENCY (Hz) FREQUENCY (Hz) Figure 25. fMCLK = 50 MHz, fOUT = 120 kHz, Frequency Word = 009D496 Figure 22. fMCLK = 10 MHz, fOUT = 1.43 MHz = fMCLK/7, Frequency Word = 2492492 Rev. 0 | Page 12 of 28 ST 200 SEC 0 –10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –100 0 –90 –100 25M RWB 1K VWB 300 05416-028 (dB) 0 05416-026 (dB) AD5932 ST 200 SEC 0 RWB 1K FREQUENCY (Hz) 25M VWB 300 ST 200 SEC FREQUENCY (Hz) Figure 26. fMCLK = 50 MHz, fOUT = 1.2 MHz, Frequency Word = 0624DD3 Figure 28. fMCLK = 50 MHz, fOUT = 7.143 MHz = fMCLK/7, Frequency Word = 2492492 0 0 –10 –10 –20 –20 –30 –30 –40 (dB) –50 –50 –60 –60 –70 –70 –80 –90 –100 0 25M RWB 1K VWB 300 ST 200 SEC 05416-029 –80 05416-027 (dB) –40 –90 –100 0 RWB 1K FREQUENCY (Hz) 25M VWB 300 ST 200 SEC FREQUENCY (Hz) Figure 29. fMCLK = 50 MHz, fOUT = 16.667 MHz = fMCLK/3, Frequency Word = 5555555 Figure 27. fMCLK = 50 MHz, fOUT = 4.8 MHz, Frequency Word = 189374C Rev. 0 | Page 13 of 28 AD5932 TERMINOLOGY Integral Nonlinearity (INL) Integral nonlinearity is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale and full scale. The error is expressed in LSBs. Total Harmonic Distortion (THD) Total harmonic distortion is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD5932, THD is defined as: Differential Nonlinearity (DNL) Differential nonlinearity is the difference between the measured and ideal 1 LSB change between two adjacent codes in the DAC. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. Spurious-Free Dynamic Range (SFDR) Along with the frequency of interest, harmonics of the fundamental frequency and images of these frequencies are present at the output of a DDS device. The SFDR refers to the largest spur or harmonic that is present in the band of interest. The wideband SFDR gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the 0 to Nyquist bandwidth. The narrow-band SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of ±200 kHz about the fundamental frequency. THD(dB) = 20 log V 2 2 + V 3 2 + V 4 2 + V 5 2 + V6 2 V1 where: V1 is the rms amplitude of the fundamental. V2, V3, V4, V5, and V6 are the rms amplitudes of the second through the sixth harmonic. Signal-to-Noise Ratio (SNR) The signal-to-noise ratio is the ratio of the rms value of the measured output signal to the rms sum of all other spectral components below the Nyquist frequency. The value for SNR is expressed in dB. Clock Feedthrough There is feedthrough from the MCLK input to the analog output. Clock feedthrough refers to the magnitude of the MCLK signal relative to the fundamental frequency in the AD5932 output spectrum. Rev. 0 | Page 14 of 28 AD5932 THEORY OF OPERATION The AD5932 is a general-purpose, synthesized waveform generator capable of providing digitally programmable waveform sequences in both the frequency and time domain. The device contains embedded digital processing to provide a scan of a user-programmable frequency profile allowing enhanced frequency control. Because the device is preprogrammable, it eliminates continuous write cycles from a DSP/microcontroller in generating a particular waveform. FINAL FREQUENCY OUT 05416-031 FSTART MIDSCALE FREQUENCY PROFILE Figure 31. Frequency Scan The frequency profile is defined by the start frequency (FSTART), the frequency increment (Δf) and the number of increments per scan (NINCR). The increment interval between frequency increments, tINT, is either user-programmable with the interval automatically determined by the device (auto-increment mode), or externally controlled via a hardware pin (external increment mode). For automatic update, the interval profile can be for either a fixed number of clock periods or a fixed number of output waveform cycles. In the auto-increment mode, a single pulse at the CTRL pin starts and executes the frequency scan. In the external-increment mode, the CTRL pin also starts the scan, but the frequency increment interval is determined by the time interval between sequential 0/1 transitions on the CTRL pin. 1 2 NUMBER OF STEP CHANGES Figure 30. Operation of the AD5932 When the AD5932 completes the frequency scan from frequency start to frequency end, that is, from FSTART incrementally to (FSTART + NINCR × Δf), it continues to output the last frequency in the scan (see Figure 31). Note that the frequency scan time is given by (NINCR + 1) × tINT. 05416-030 An example of a 2-step frequency scan is shown in Figure 30. Note the frequency swept output signal is continuously available and is, therefore, phase continuous at all frequency increments. SERIAL INTERFACE The AD5932 has a standard 3-wire serial interface that is compatible with SPI®, QSPI™, MICROWIRE™, and DSP interface standards. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK. The timing diagram for this operation is shown in Figure 4. The FSYNC input is a level-triggered input that acts as a frame synchronization and chip enable. Data can be transferred into the device only when FSYNC is low. To start the serial data transfer, FSYNC should be taken low, observing the minimum FSYNC to SCLK falling edge setup time, t7. After FSYNC goes low, serial data is shifted into the device's input shift register on the falling edges of SCLK for 16 clock pulses. FSYNC may be taken high after the 16th falling edge of SCLK, observing the minimum SCLK falling edge to FSYNC rising edge time, t8. Alternatively, FSYNC can be kept low for a multiple of 16 SCLK pulses and then brought high at the end of the data transfer. In this way, a continuous stream of 16-bit words can be loaded while FSYNC is held low. FSYNC should only go high after the 16th SCLK falling edge of the last word is loaded. The SCLK can be continuous, or, alternatively, the SCLK can idle high or low between write operations. POWERING UP THE AD5932 When the AD5932 is powered up, the part is in an undefined state and, therefore, must be reset before use. The seven registers (control and frequency) contain invalid data and need to be set to a known value by the user. The control register should be the first register to be programmed, as this sets up the part. Note that a write to the control register automatically resets the internal state machines and provides an analog output of midscale, because it performs the same function as the INTERRUPT pin. Typically, this is followed by a serial loading of all the required scan parameters. The DAC output remains at midscale until a frequency scan is started using the CTRL pin. Rev. 0 | Page 15 of 28 AD5932 Table 5. Register Addresses PROGRAMMING THE AD5932 The AD5932 is designed to provide automatic frequency scans when the CTRL pin is triggered. The scan is controlled by a set of registers, the addresses of which are given in Table 5. The function of each register is described in more detail in the Setting Up the Frequency Scan section. The Control Register The AD5932 contains a 12-bit control register that sets up the operating modes, as shown in the following bit map. D15 0 D14 0 D13 0 D12 0 D11 to D0 Control bits This register controls the different functions and the various output options from the AD5932. Table 6 describes the individual bits of the control register. Register Address D15 D14 D13 0 0 0 0 0 0 0 0 1 D12 0 1 0 Mnemonic CREG NINCR Δf 0 0 1 Δf 0 1 1 1 0 1 0 0 FSTART 1 1 0 1 FSTART 1 1 1 1 1 1 0 1 1 tINT Name Control bits Number of increments Lower 12 bits of delta frequency Higher 12 bits of delta frequency Increment interval Reserved Lower 12 bits of start frequency Higher 12 bits of start frequency Reserved Reserved To address the control register, D15 to D12 of the 16-bit serial word must be set to 0. Table 6. Description of Bits in the Control Register Bit D15 to D12 D11 Name ADDR B24 D10 DAC ENABLE D9 SINE/TRI D8 MSBOUTEN D7 D6 D5 Reserved Reserved INT/EXT INCR D4 D3 Reserved SYNCSEL D2 SYNCOUTEN D1 D0 Reserved Reserved Function Register address bits. Two write operations are required to load a complete word into the FSTART register and the Δf register. When B24 = 1, a complete word is loaded into a frequency register in two consecutive writes. The first write contains the 12 LSBs of the frequency word and the next write contains the 12 MSBs. Refer to Table 5 for the appropriate addresses. The write to the destination register occurs after both words have been loaded, so the register never holds an intermediate value. When B24 = 0, the 24-bit FSTART /Δf register operates as two 12-bit registers, one containing the 12 MSBs and the other containing the 12 LSBs. This means that the 12 MSBs of the frequency word can be altered independently of the 12 LSBs and vice versa. This is useful if the complete 24-bit update is not required. To alter the 12 MSBs or the 12 LSBs, a single write is made to the appropriate register address. Refer to Table 5 for the appropriate addresses. When DAC ENABLE = 1, the DAC is enabled. When DAC ENABLE = 0, the DAC is powered down. This saves power and is beneficial when using only the MSB of the DAC input data (available at the MSBOUT pin). The function of this bit is to control what is available at the VOUT pin. When SINE/TRI = 1, the SIN ROM is used to convert the phase information into amplitude information, resulting in a sinusoidal signal at the output. When SINE/TRI = 0, the SIN ROM is bypassed, resulting in a triangular (up-down) output from the DAC. When MSBOUTEN = 1, the MSBOUT pin is enabled. When MSBOUTEN = 0, the MSBOUT is disabled (three-state). This bit must be set to 1. This bit must be set to 1. When INT/EXT INCR = 1, the frequency increments are triggered externally through the CTRL pin. When INT/EXT INCR = 0, the frequency increments are triggered automatically. This bit must be set to 1. This bit is active when D2 = 1. It is user-selectable to pulse at end of scan (EOS) or at each frequency increment. When SYNCSEL = 1, the SYNCOUT pin outputs a high level at end of scan and returns to 0 at the start of the subsequent scan. When SYNCSEL= 0, the SYNCOUT outputs a pulse of 4 × TCLOCK only at each frequency increment. When SYNCOUTEN = 1, the SYNC output is available at the SYNCOUT pin. When SYNCOUTEN = 0, the SYNCOP pin is disabled (three-state). This bit must be set to 1. This bit must be set to 1. Rev. 0 | Page 16 of 28 AD5932 SETTING UP THE FREQUENCY SCAN Number of Increments (NINCR) As stated in the Frequency Profile section, the AD5932 requires certain registers to be programmed to enable a frequency scan. The Setting Up the Frequency Scan section discusses these registers in more detail. An end frequency is not required on the AD5932. Instead, this end frequency is calculated by multiplying the frequency increment value (Δf) by the number of frequency steps (NINCR) and adding it to/subtracting it from the start frequency (FSTART); that is, FSTART + NINCR × Δ f. The NINCR register is a 12-bit register, with the address shown in the following bit map. Start Frequency (FSTART) To start a frequency scan, the user needs to tell the AD5932 what frequency to start scanning from. This frequency is stored in a 24-bit register called FSTART. If the user wishes to alter the entire contents of the FSTART register, two consecutive writes must be performed: one to the LSBs and the other to the MSBs. Note that for an entire write to this register, Control Bit B24 (D11) should be set to 1, with the LSBs programmed first. In some applications, the user does not need to alter all 24 bits of the FSTART register. By setting Control Bit B24 (D11) to 0, the 24-bit register operates as two 12-bit registers, one containing the 12 MSBs and the other containing the 12 LSBs. This means that the 12 MSBs of the FSTART word can be altered independently of the 12 LSBs and vice versa. The addresses of both the LSBs and the MSBs of this register are shown in the following bit map. D15 1 1 D14 1 1 D13 0 0 D12 0 1 D11 to D0 12 LSBs of FSTART <11…0> 12 MSBs of FSTART <23…12> Frequency Increments (Δf) The value in the Δf register sets the increment frequency for the scan and is added incrementally to the current output frequency. Note that the increment frequency can be positive or negative, thereby giving an increasing or decreasing frequency scan. At the start of a scan, the frequency contained in the FSTART register is output. Next, the frequency (FSTART + Δf ) is output. This is followed by (FSTART + Δf + Δf), and so on. Multiplying the Δf value by the number of increments (NINCR) and adding it to the start frequency (FSTART) give the final frequency in the scan. Mathematically, this final frequency/stop frequency is represented by FSTART + (NINCR × Δf) The Δf register is a 23-bit register that requires two 16-bit writes to be programmed. Table 7 gives the addresses associated with both the MSB and LSB registers of the Δf word. Table 7. Δf Register Bits D15 0 D14 0 D13 1 D12 0 0 0 1 1 0 0 1 1 D11 D10 to D0 12 LSBs of Δf <11…0> 0 11 MSBs of Δf <22…12> 1 11 MSBs of Δf <22…12> Scan Direction N/A Positive Δf (FSTART + Δf ) D15 0 D14 0 D13 0 D12 1 D11 12 bits of NINCR D0 <11…0> The number of increments is programmed in binary fashion, with 000000000010 representing the minimum number of frequency increments (two increments) and 111111111111 representing the maximum number of increments (4095). Table 8. NINCR Data Bits D11 0000 … 0000 D0 0010 0000 0000 … 1111 1111 0000 0000 … 1111 1111 0011 0100 … 1110 1111 Number of Increments Two frequency increments. This is the minimum number of frequency increments. Three frequency increments. Four frequency increments. … 4094 frequency increments. 4095 frequency increments. Increment Interval (tINT) The increment interval dictates the duration of the DAC output signal for each individual frequency of the frequency scan. The AD5932 offers the user two choices: • The duration is a multiple of cycles of the output frequency. • The duration is a multiple of MCLK periods. The desired choice is selected by Bit D13 in the tINT register as shown in the following bit map. D15 0 D14 1 D13 0 D12 x D11 x 0 1 1 x x D10 to D0 11 bits <10…0> Fixed number of output waveform cycles. 11 bits <10…0> Fixed number of clock periods. Programming of this register is in binary form, with the minimum number being decimal 2. Note that 11 bits, D10 to D0, of the register are available to program the time interval. As an example, if MCLK = 50 MHz, then each clock period/base interval is (1/50 MHz) = 20 ns. If each frequency must be output for 100 ns, then <00000000101> or decimal 5 must be programmed to this register. Note that the AD5930 can output each frequency for a maximum duration of 211 − 1 (or 2047) times the increment interval. Negative Δf (FSTART − Δf ) Rev. 0 | Page 17 of 28 AD5932 Therefore, in this example, a time interval of 20 ns × 2047 = 40 μs is the maximum, with the minimum being 40 ns. For some applications, this maximum time of 40 μs may be insufficient. Therefore, to allow for sweeps that need a longer increment interval, time-base multipliers are provided. D12 and D11 are dedicated to the time-base multipliers, as shown in the bit map above. A more detailed table of the multiplier options is given in Table 9. Table 9. Time-Base Multiplier Values D12 0 0 1 1 D11 0 1 0 1 The above example shows a fixed number of clock periods. Note that the same equally applies to fixed numbers of clock cycles. The length of time to complete a user-programmed frequency scan is given by the following equation: TSCAN = (1 + NINCR) × TBASE ACTIVATING AND CONTROLLING THE SCAN After the registers have been programmed, a 0 to 1 transition on the CTRL pin starts the scan. The scan always starts from the frequency programmed into the FSTART register. It changes by the value in the Δf register and increases by the number of steps in the NINCR register. However, the time interval of each frequency can be internally controlled using the tINT register or externally controlled using the CTRL pin. The available options are External increment To set up the AD5932 to this mode, INT/EXT INCR (Bit D5) must be set to 1. INTERRUPT Pin This function is used as an interrupt during a frequency scan. A low-to-high transition on this pin is sampled by the internal MCLK, thereby resetting internal state machines, which results in the output going to midscale. STANDBY Pin Length of Scan Time • To set up the AD5932 to this mode, INT/EXT INCR (Bit D5) must be set to 0. In this case, the time interval, tINT, is set by the pulse rate on the CTRL pin. The first 0 to 1 transition on the pin starts the scan. Each subsequent 0 to 1 transition on the CTRL pin increments the output frequency by the value programmed into the Δf register. If MCLK = 50 MHz and a multiplier of 500 is used, then the base interval (TBASE) is now (1/(50 MHz) x 500)) = 10 μs. Using a multiplier of 500, the maximum increment interval is 10 μs × 211 − 1 = 20.5 ms. Therefore, the option of time-base multipliers gives the user enhanced flexibility when programming the length of the frequency window, because any frequency can be output for a minimum of 40 ns up to a maximum of 20.5 ms. Auto-increment The value in the tINT register is used to control the scan. The AD5932 outputs each frequency for the length of time programmed in the TINT register, before moving on to the next frequency. External Increment Control Multiplier Value Multiply (1/MCLK) by 1 Multiply (1/MCLK) by 5 Multiply (1/MCLK) by 100 Multiply (1/MCLK) by 500 • Auto-Increment Control Sections of the AD5932 that are not in use can be powered down to minimize power consumption. This is done by using the STANDBY pin. For optimum power savings, it is recommended to reset the AD5932 before entering standby. Doing so reduces the power-down current to 20 μA. When this pin is high, the internal MCLK is disabled, and the reference, DAC, and regulator are powered down. When in this state, the DAC output of the AD5932 remains at its present value, because the NCO is no longer accumulating. When the device is taken back out of standby mode, the MCLK is reactivated, and the scan continues. To ensure correct operation for new data, it is recommended that the device be internally reset, using a control register write or using the INTERRUPT pin, and then restarted. Rev. 0 | Page 18 of 28 AD5932 The AD5932 offers a variety of outputs from the chip. The analog outputs are available from the VOUT pin and include a sine wave and a triangle output. The digital outputs are available from the MSBOUT pin and the SYNCOUT pin. Analog Outputs Sinusoidal Output The SIN ROM is used to convert the phase information from the frequency register into amplitude information, resulting in a sinusoidal signal at the output. The AD5932 includes a 10-bit, high impedance, current source DAC that is configured for single-ended operation. An external load resistor is not required because the device has a 200 Ω resistor on board. To have a sinusoidal output from the VOUT pin, set SINE/TRI (Bit D9) in the control register to 1. Triangle Output The SIN ROM can be bypassed so that the truncated digital output from the NCO is sent to the DAC. In this case, the output is no longer sinusoidal. The DAC produces a 10-bit linear triangular function. To have a triangle output from the VOUT pin, set SINE/TRI (Bit D9) to 0. Note that DAC ENABLE (Bit D10) must be set to 1 (that is, the DAC is enabled) when using this pin. p/2 5p/2 9p/2 VOUT MIN 3p/2 7p/2 11p/2 05416-032 VOUT MAX Figure 32. Triangle Output Digital Outputs Square-Wave Output from MSBOUT The inverse of the MSB from the NCO can be output from the AD5932. By setting MSBOUTEN (Bit D8) to 1, the inverted MSB of the DAC data is available at the MSBOUT pin. This is useful as a digital clock source. DVDD 05416-040 OUTPUTS FROM THE AD5932 DGND Figure 33. MSB Output SYNCOUT Pin The SYNCOUT pin can be used to give the status of the scan. It is user-selectable for the end of scan or to output a 4 × TCLOCK pulse at frequency increments. The timing information for both of these modes is shown in Figure 6. The SYNCOUT pin must be enabled before use. This is done using Bit D2 in the control register. The output available from this pin is then controlled by Bit D3 in the control register. See Table 6 for more information. Rev. 0 | Page 19 of 28 AD5932 APPLICATIONS GROUNDING AND LAYOUT Interfacing to Microprocessors The printed circuit board that houses the AD5932 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes that can be easily separated. A minimum etch technique is generally best for ground planes because it gives the best shielding. Digital and analog ground planes should be joined in only one place. If the AD5932 is the only device requiring an AGND-to-DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD5932. If the AD5932 is in a system where multiple devices require AGND-to-DGND connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the AD5932. The AD5932 has a standard serial interface that allows the part to interface directly with several microprocessors. The device uses an external serial clock to write the data/control information into the device. The serial clock can have a frequency of 40 MHz maximum. The serial clock can be continuous, or it can idle high or low between write operations. When data/control information is being written to the AD5932, FSYNC is taken low and is held low while the 16 bits of data are being written into the AD5932. The FSYNC signal frames the 16 bits of information being loaded into the AD5932. Good decoupling is important. The analog and digital supplies to the AD5932 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. All analog and digital supplies should be decoupled to AGND and DGND, respectively, with 0.1 μF ceramic capacitors in parallel with 10 μF tantalum capacitors. To achieve the best from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. In systems where a common supply is used to drive both the AVDD and DVDD of the AD5932, it is recommended that the system’s AVDD supply be used. This supply should have the recommended analog supply decoupling between the AVDD pin of the AD5932 and AGND and the recommended digital supply decoupling capacitors between the DVDD pin and DGND. Figure 34 shows the serial interface between the AD5932 and the ADSP-21xx. The ADSP-21xx should be set up to operate in the SPORT transmit alternate framing mode (TFSW = 1). The ADSP-21xx are programmed through the SPORT control register and should be configured as follows: • Internal clock operation (ISCLK = 1) • Active low framing (INVTFS = 1) • 16-bit word length (SLEN = 15) • Internal frame sync signal (ITFS = 1) • Generation of a frame sync for each write (TFSR = 1) Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. The data is clocked out on each rising edge of the serial clock and clocked into the AD5932 on the SCLK falling edge. Rev. 0 | Page 20 of 28 ADSP-2101/ ADSP-21031 AD59321 TFS FSYNC DT SDATA SCLK SCLK 05416-034 Avoid running digital lines under the device because these couple noise onto the die. The analog ground plane should run under the AD5932 to avoid noise coupling. The power supply lines to the AD5932 should use as large a track as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other, reducing the effects of feedthrough. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes, while signals are placed on the other side. AD5932 TO ADSP-21XX INTERFACE 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 34. ADSP-2101/ADSP-2103 to AD5932 Interface AD5932 AD5932 TO 68HC11/68L11 INTERFACE Figure 35 shows the serial interface between the AD5932 and the 68HC11/68L11 microcontroller. The microcontroller is configured as the master by setting Bit MSTR in the SPCR to 1, which provides a serial clock on SCK while the MOSI output drives the serial data line, SDATA. Because the microcontroller does not have a dedicated frame sync pin, the FSYNC signal is derived from a port line (PC7). The set-up conditions for correct operation of the interface are as follows: • SCK idles high between write operations (CPOL = 0). • Data is valid on the SCK falling edge (CPHA = 1). To load the remaining eight bits to the AD5932, P3.3 is held low after the first eight bits have been transmitted, and a second write operation is initiated to transmit the second byte of data. P3.3 is taken high following completion of the second write operation. SCLK should idle high between the two write operations. The 80C51/80L51 outputs the serial data in an LSBfirst format. The AD5932 accepts the MSB first (the four MSBs being the control information, the next four bits being the address, while the eight LSBs contain the data when writing to a destination register). Therefore, the transmit routine of the 80C51/80L51 must consider this and rearrange the bits so that the MSB is output first. 80C51/80L511 AD59321 FSYNC MOSI SDATA SCK SCLK FSYNC RxD SDATA TxD SCLK 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 36. 80C51/80L51 to AD5932 Interface AD5932 TO DSP56002 INTERFACE Figure 37 shows the interface between the AD5932 and the DSP56002. The DSP56002 is configured for normal mode, asynchronous operation with a gated internal clock (SYN = 0, GCK = 1, SCKD = 1). The frame sync pin is generated internally (SC2 = 1), the transfers are 16 bits wide (WL1 = 1, WL0 = 0), and the frame sync signal frames the 16 bits (FSL = 0). The frame sync signal is available on Pin SC2, but it must be inverted before being applied to the AD5932. The interface to the DSP56000/DSP56001 is similar to that of the DSP56002. 05416-035 PC7 P3.3 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 35. 68HC11/68L11 to AD5932 Interface AD5932 TO 80C51/80L51 INTERFACE Figure 36 shows the serial interface between the AD5932 and the 80C51/80L51 microcontroller. The microcontroller is operated in Mode 0 so that TxD of the 80C51/80L51 drives SCLK of the AD5932, while RxD drives the serial data line SDATA. The FSYNC signal is again derived from a bit programmable pin on the port (P3.3 being used in the diagram). When data is to be transmitted to the AD5932, P3.3 is taken low. The 80C51/80L51 transmits data in 8-bit bytes; thus, only eight falling SCLK edges occur in each cycle. Rev. 0 | Page 21 of 28 DSP560021 AD59321 SC2 FSYNC STD SDATA SCK SCLK 05416-032 68HC11/68L111 AD59321 05416-036 When data is being transmitted to the AD5932, the FSYNC line is taken low (PC7). Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. In order to load data into the AD5932, PC7 is held low after the first eight bits are transferred and a second serial write operation is performed to the AD5932. Only after the second eight bits have been transferred should FSYNC be taken high again. 1ADDITIONAL PINS OMITTED FOR CLARITY. Figure 37. DSP56002 to AD5932 Interface AD5932 EVALUATION BOARD The AD5932 evaluation board allows designers to evaluate the high performance AD5932 DDS modulator with minimum effort. The evaluation board interfaces to the USB port of a PC. It is possible to power the entire board from the USB port. All that is needed to complete the evaluation of the chip is either a spectrum analyzer or a scope. The DDS evaluation kit includes a populated and tested AD5932 printed circuit board. The EVAL-AD5932EB kit is shipped with a CD-ROM that includes self-installing software. The PC is connected to the evaluation board using the supplied cable. The software is compatible with Microsoft® Windows® 2000 and Windows XP. A schematic of the evaluation board is shown in Figure 38 and Figure 39. Using the AD5932 Evaluation Board The AD5932 evaluation kit is a test system designed to simplify the evaluation of the AD5932. An application note is also available with the evaluation board that gives full information on operating the evaluation board. Prototyping Area An area is available on the evaluation board for the user to add additional circuits to the evaluation test set. Users may want to build custom analog filters for the output or add buffers and operational amplifiers to be used in the final application. XO vs. External Clock The AD5932 can operate with master clocks up to 50 MHz. A 50 MHz oscillator is included on the evaluation board. However, this oscillator can be removed and, if required, an external CMOS clock can be connected to the part. Rev. 0 | Page 22 of 28 AD5932 05416-038 SCHEMATICS Figure 38. Page 1 of EVAL-AD5932EB Schematic Rev. 0 | Page 23 of 28 05416-039 AD5932 Figure 39. Page 2 of EVAL-AD5932EB Schematic Rev. 0 | Page 24 of 28 AD5932 OUTLINE DIMENSIONS 0.201 (5.10) 0.193 (4.90) 0.256 (6.50) 0.246 (6.25) 0.177 (4.50) 9 0.169 (4.30) 16 1 8 PIN 1 0.006 (0.15) 0.002 (0.05) SEATING PLANE 0.0433 (1.10) MAX 0.0256 (0.65) BSC 0.0118 (0.30) 0.0075 (0.19) 0.0079 (0.20) 8° 0° 0.028 (0.70) 0.020 (0.50) 0.0035 (0.090) Figure 40. 16-Lead Thin Shrink Small Outline Package (TSSOP) (RU-16) Dimensions shown in millimeters ORDERING GUIDE Model AD5932YRUZ 1 AD5932YRUZ-REEL71 EVAL-AD5932EB 1 Temperature Range −40°C to +125°C −40°C to +125°C Package Description 16-Lead Thin Shrink Small Outline Package [TSSOP] 16-Lead Thin Shrink Small Outline Package [TSSOP] Evaluation Board Z = Pb-free part. Rev. 0 | Page 25 of 28 Package Option RU-16 RU-16 AD5932 NOTES Rev. 0 | Page 26 of 28 AD5932 NOTES Rev. 0 | Page 27 of 28 AD5932 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05416-0-4/06(0) Rev. 0 | Page 28 of 28