TFDU5107 Vishay Semiconductors Integrated Low Profile Transceiver Module for Telecom Applications 9.6 kbit/s to 1.152 Mbit/s Data Transmission Rate Description The miniaturized TFDU5107 in the well-known Baby Face package is an ideal transceiver for applications in telecommunications like mobile phones, pagers, and PDAs of all kinds. The devices are designed for optimum performance and minimum package size. The device covers the IrDA physical layer specification with SIR specification and 1.152 Mbit/s IrDA mode. The new features A current limiter is implemented to operate the device whitout external resistor in an IrDA compliant mode (> 1 m). For reduced current as for the “Low Power” mode a current limiting resistor might be added. The device covers the supply voltage from 3.6 V down to 2.4 V and with its low power consumption it is optimum suited for battery powered applications. Double eye safety protection by pulse duration and current limitation is integrated. As additional feature the logic voltage swing Vlogic can be set externally. Features Package: – TFDU5107 Universal (Baby Face) – SMD Side and Top View Solderability Internal IRED current limition to operate without external resistor. With external resistor adaptable to power reduced operation as IrDA “Low Power” Standard Tri – State – Receiver Output Lowest Power Consumption, typically 500 µA in Receive Mode, <1 µA Shutdown, only typical 5 mA Average Current Consumption in SIR and 1.152 Mbit/s Transmit Mode in Low Power IrDA mode Fewest External Components Wide Supply Voltage Range (2.4 V to 3.6 V) High EMI Immunity Operational down to 2.0 V Eye Safety Protection Integrated Logic Input and Output Voltage 1.5 V to 5.5 V set by external control pin Pin Assignment Backward Compatible to Legacy Baby Face Package Applications Mobile Phones, Pagers, Hand–held Battery Operated Equipment Digital Still and Video Cameras Computers (WinCE, PalmPC, PDAs) Medical and Industrial Data Collection Extended IR Adapters Package TFDU5107 Baby Face (Universal) Document Number 82534 Rev. A1.4, 01-Nov-02 www.vishay.com 1 (13) TFDU5107 Vishay Semiconductors Ordering Information Part Number TFDU5107–TR3 TFDU5107–TT3 Qty / Reel 1000 pcs 1000 pcs Description Oriented in carrier tape for side view surface mounting Oriented in carrier tape for top view surface mounting Functional Block Diagram VCC Vlogic Driver Amplifier Comparator Rxd IRED Anode SD AGC Logic Current controlled driver Txd IRED Cathode GND Figure 1. Functional Block Diagram Pin Description Pin Number 1 2 3 4 5 6 7 8 Function IRED Anode Description I/O IRED Anode to be externally connected to directly to VCC. Alternatively the current can be decreased by an external resistor.This pin is allowed to be supplied from an uncontrolled power supply separated from the controlled VCC supply IRED Cathode IRED Cathode, internally connected to driver transistor Txd Transmit Data Input I Rxd Received Data Output, push–pull CMOS driver output capable O of driving a standard CMOS or TTL load. No external pull–up or pull–down resistor is required. Pin is floating with a weak pull up to VCC, when device is in shutdown mode. Rxd output is quiet during transmission. SD Shutdown, will switch the device into shutdown after a delay I of 1 ms VCC Supply Voltage Vlogic Defines the input and output logic swing voltage I GND Ground Active HIGH LOW HIGH Baby Face (Universal) Figure 2. Pinning www.vishay.com 2 (13) Document Number 82534 Rev. A1.4, 01-Nov-02 TFDU5107 Vishay Semiconductors Absolute Maximum Ratings Reference Point Ground, Pin 8, unless otherwise noted Parameters Supplyy Voltage g Range g Input Current Output Sink Current, Rxd Rep. Pulsed IRED Current Average IRED Current Power Dissipation Junction Temperature Ambient Temperature Range (Operating) Storage Temperature Range Soldering Temperature Transmitter Data and Shutdown Input Voltage Receiver Data Output Voltage Virtual Source Size Test Conditions Symbol Min. 0 V < Vdd2 < 6 V 0 V < Vdd1 < 6 V 0 V < Vdd2 < 6 V 0 V < Vdd1 < 6 V All Pins (Pin 1 excluded) Pin 4 Pin 1, ton< 20%, < 20 µs Vdd1 Vdd2 Vlogic t = 20 s @215°C 2.4 V < Vdd1 < 5.5 V Method: (1–1/e) encircled energy Maximum Intensity for Class 1 IEC60825–1 or EN60825–1, edition Jan.2001 *) **) Typ. Max. Unit –0.5 –0.5 –0.5 6 6 6 V V V IIRED(RP) IIRED(DC) Ptot TJ Tamb –25 10 25 500 125 450 125 85 mA mA mA mA mW °C °C Tstg –25 VTxd, VSD –0.5 85 240 6 °C °C V VRxd d –0.5 2.5 Vlogic+0.5 V mm *) (500) **) mW/sr 215 Ie 2.8 Due to the internal limitation measures the device is a “class 1” device IrDA specifies the max. intensity with 500 mW/sr Document Number 82534 Rev. A1.4, 01-Nov-02 www.vishay.com 3 (13) TFDU5107 Vishay Semiconductors Optoelectronic Characteristics Tamb = 25°C, Vdd1 = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameters Test Conditions Symbol Min. Typ. Max. Unit Transceiver Supported Data Rates Rxd pulse duration 400 ns Base band SIR mode 9.6 115.2 kbit/s Base band 1.152 Mbit/s 9.6 1152 kbit/s Supply Voltage Range specified operation Vdd1 2.4 3.6 V Supply Voltage Vdd2 = 2.4 V to 3.6 V Vdd2 2.4 3.6 V Supply Current receive mode Vdd1 = 2.4 V to 3.6 V IS 500 900 µA Supply Current shutdown mode Vdd1 = 2.4 V to 3.6 V ISSD 0.1 1 µA Average Supply Current *) Standart MIR transmit mode Ie > 100 mW/ sr Vdd1 = 2.4 V to 3.6 V, above Vdd1 =3.3 V a serial resistor for reducing the internal power dissipation should be implemented, e.g. RL = 2.7 Ω IS 60 110 mA Logic Voltage Range Vdd2 = 2.4 V to 3.6 V Vlogic 1.5 3.6 V Shutdown / Mode clock pulse duration tprog 0.2 20 µs Shutdown delay ”Receive off” tprog 1 1.5 ms Shutdown Delay ”Receive on” tprog 40 100 µs 50 µs Transceiver “Power On“ Settling Time *) Time from switching on Vdd1 to established specified operation Maximum data is for 20% (25%) duty cycle for SIR (MIR 1.152 Mbit/s) Low power mode. The typical value is given for the case of normal operation with statistical and equal ”0” and ”1” – distribution. www.vishay.com 4 (13) Document Number 82534 Rev. A1.4, 01-Nov-02 TFDU5107 Vishay Semiconductors Optoelectronic Characteristics Tamb = 25°C, Vdd1 = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameters Test Conditions Symbol Min. Typ. Max. Unit Receiver Minimum Detection Threshold Irradiance SIR 9.6 kbit/s to 115.2 kbit/s *) |α| ≤ ±15° Vdd1 = 2.4 V to 3.6 V Ee, min 20 35 mW/m 2 Minimum Detection Threshold Irradiance 9.6 kbit/s to 1.152 Mbit/s *) |α| ≤ ±15° Vdd1 = 2.4 V to 3.6 V Ee, min 50 80 mW/m 2 Maximum Detection Threshold Irradiance |α| ≤ ±90° Vdd1 = 5 V Ee, max 3300 5000 W/m 2 |α| ≤ ±90° Vdd1 = 3 V Ee, max 8000 15000 W/m 2 Ee,max,low 4 Logic Low Receiver Input Irradiance Output Voltage Rxd Active C = 15 pF, R = 2.2 kΩ VOL Non active C = 15 pF, R = 2.2 kΩ VOH mW/m 2 0.5 0.8 Vlogic–0.5 V V Output Current Rxd VOL < 0.8 V 4 mA Rise Time @Load: C = 15 pF, R = 2.2 kΩ 1.5 V ≤ Vlogic ≤ 5.5 V tr 20 70 ns Fall Time @Load: C = 15 pF, R = 2.2 kΩ 1.5 V ≤ Vlogic ≤ 5.5 V tf 20 70 ns Rxd Signal Electrical Output Pulse Width 1.5 V ≤ Vlogic ≤ 5.5 V tp 300 400 500 ns 100 200 µs Latency *) tL Rxd output pulse duration 400 ns Document Number 82534 Rev. A1.4, 01-Nov-02 www.vishay.com 5 (13) TFDU5107 Vishay Semiconductors Optoelectronic Characteristics Tamb = 25°C, Vdd1 = 2.4 V to 3.6 V unless otherwise noted. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Parameters Test Conditions Symbol Min. Typ. Max. Unit Transmitter Logic CMOS High/Low Decision Threshold VIL(Txd) Logic Low Transmitter Input Voltage VIL(Txd) Logic High Transmitter Input Voltage 1.5 V < Vlogic < 3.6 V VIH(Txd) 1/2xVlogic V 0 0.2*) Vlogic V 0.8*) Vlogic Vlogic +0.5 V 320 mW/sr Current Limitation Vdd1 = 3.3 V IF Output Radiant Intensity, |α| ≤ ±15° Standard MIR level IF6 = 400 mA resistor limited Ie 110 Maximum Output Pulse width (eye safety protection) PWI > 23 µs PWOmin 23 80 µs Optical Pulse width PWI = 1.6 µs PWO 1.45 1.75 µs PWI = 217 ns PWO 210 226 ns 40 ns 880 900 nm Optical Rise/Falltime λp Spectral Optical Radiation Bandwidth ∆λ Txd logic low level Overshoot, Optical Rising Edge Peak to Peak Jitter *) 250 tr, tf Peak Wavelength of Emission Output Radiant Intensity 400 tj mA 45 nm 0.04 µW/sr 25 % 0.2 µs Switch, current can be defined by external resistor, internal current limitation to 500 mA peak www.vishay.com 6 (13) Document Number 82534 Rev. A1.4, 01-Nov-02 TFDU5107 Vishay Semiconductors Recommended SMD Pad Layout The leads of the device should be soldered in the center position of the pads. 7x1=7 0.6 (≤ 0.7) 2.5 (≥ 2.0) 1 8 1 16524 Figure 3. TFDU5107 Baby Face (Universal) Recommended Solder Profile 10 s max. @ 230°C 210 2 - 4°C/s 180 150 120 120 - 180 s 90 60 90 s max. 2 - 4°C/s 30 Peak Operating Current ( mA ) 600 240 Temperature ( °C ) Current Derating Diagram 0 0 50 100 14874 150 200 250 Time ( s ) 300 Document Number 82534 Rev. A1.4, 01-Nov-02 400 300 200 Current derating as a function of the maximum forward current of IRED. Maximum duty cycle: 25%. 100 0 –40 –20 0 350 Figure 4. Recommended Solder Profile 500 14875 20 40 60 80 100 120 140 Temperature ( °C ) Figure 5. Current Derating Diagram www.vishay.com 7 (13) TFDU5107 Vishay Semiconductors Identification The identification of the device can be recalled by setting the SD active followed by activating Txd for a short period. With the low going edge of Txd a single pulse is generated at Rxd. The SD is intendet to activate the shutdown function after a delay of 1 ms. Therefore the full sequence should be run with that 1 ms time limitation, see drawing. tSD: > 5 s for “real” shutdown > 1 ms SD tTxd: > 0.5 s to 2 s Txd tdelTxd: ≥ 1 s tdelRxd: ≥ 10 ns Rxd tRxd = 400 ns Figure 6. Vlogic Setting The logic voltage swing is set by applying an external voltage to the Vlogic pin. Table 1. Truth table Inputs Outputs SD Txd Optical input Irradiance mW/ m2 Rxd LED drive current resulting intensity Ie in mW/ sr high < 1 ms pulse x low going Txd triggers monostable to edit a 400 ns low pulse 0 high > 1 ms x x floating (500 kΩ to Vdd) 0 low high x high 10 < Ie < 300 defined by an external resistor low high > 80 µs x high 0 low low <4 high 0 low low > 40 low, pulse of 400 ns edge triggered 0 www.vishay.com 8 (13) Document Number 82534 Rev. A1.4, 01-Nov-02 TFDU5107 Vishay Semiconductors TFDU5107 – Baby Face (Universal) Package (Mechanical Dimensions) 12249 Document Number 82534 Rev. A1.4, 01-Nov-02 www.vishay.com 9 (13) TFDU5107 Vishay Semiconductors Appendix Application Hints The inputs TXD and SD are high impedance CMOS inputs. Therefore, the lines from the I/O to those inputs should be carefully designed not to pick up ambient noise. If long lines are used, loads at the Txd input of the TFDx5x07 and at the Rxd input of the controller (!) are recommended. At the IRED Anode voltage supply line an additional capacitor might be necessary when inductive wiring is used. However, a low impedance layout is the better and more cost efficient solution. For adjusting the intensity depending on the application, see the diagrams. 500 5.25V 5.0V min. Rdson, min. VF 300 5.0V 200 max.Rdson, max.VF 100 Vcc=4.75V min. intensity in emission cone 15° 0 0 2 4 6 8 10 12 14 Current Control Resistor ( ) 15186 700 max. intensity in emission cone 15° VCC1 C2 TFDU5107 C1 6 GND Vdd1 8 GND 4 Rxd VCC2 1 Vdd2, IRED Anode Txd 3 Txd SD 5 SD Vlog 7 Vlogic Rxd Intensity (mW/sr) Recommended Circuit Diagram R1 min. Rdson, min. VF 500 3.6V min. intensity in emission cone 15° 400 3.3V 300 max. Rdson, max. VF 200 3.3V 100 C3 R2 16 Figure 8. Intensity Ie vs. Current Control Resistor R2 5 V Applications 600 C1, (C3): 4.7 µF, see text C2: 470 nF max. intensity in emission cone 15° 400 Intensity (mW/sr) The TFDU5107 do not need any external components when operated at a ”clean” power supply. In a more power supply noisy ambient it is recommended to add a combination of a resistor and capacitor (R1, C1, C2) for noise suppression as shown in the figure below. A combination of a electrolytic for the low frequency range and a ceramic capacitor for suppressing the high frequency disturbance will be most effective. The capacitor C3 is only necessary when inductive wiring is used or the power supply cannot deliver the operating peak pulse current. Vcc=3.0V 0 0 15187 2 4 6 8 10 Current Control Resistor ( ) 12 Figure 9. Intensity Ie vs. Current Control Resistor R1, 3 V Applications Latency Figure 7. Recommended Application Circuit Shut Down To shut down the TFDx5x07 into a standby mode the SD pin has to be set active. After a delay of < 1 ms it will switch to the standby mode. www.vishay.com 10 (13) The receiver is in specified conditions after the defined latency. In a UART related application after that time (typically 50 µs) the receiver buffer of the UART must be cleared. Therefore, the transceiver has to wait at least the specified latency after receiving the last bit before starting the transmission to be sure that the corresponding receiver is in a defined state. Document Number 82534 Rev. A1.4, 01-Nov-02 TFDU5107 Vishay Semiconductors Table 1. Recommended Application Circuit Components Component Recommended Value Vishay Part Number 4.7 F, 16 V 0.1 µF, Ceramic 293D 475X9 016B 2T VJ 1206 Y 104 J XXMT R1 47 Ω, 0.125 W CRCW–1206–47R0–F–RT1 R2 5 V supply voltage: 14 Ω, 0.25 W (recommend using two 6.8 , 0.125 W resistors in series) 3.0 V supply voltage: 4.5 Ω, 0.25 W (recommend using two 2.3 , 0.125 W resistors in series) CRCW–1206–6R80–F–RT2 C1, C3 C2 Document Number 82534 Rev. A1.4, 01-Nov-02 CRCW–1206–2R26–F–RT1 www.vishay.com 11 (13) TFDU5107 Vishay Semiconductors Revision History: A1.1a, 19/12/1999:Slightly changed feature description. The pins 6 and 7 are exchanged by customer demand. A1.2, 12/07/2000: Rxd Rise time and Fall time reduced typos corrected A1.3, 13/10/2000: Typos corrected A1.4, 01/11/2002: Eye safety statement adapted to the latest standard version www.vishay.com 12 (13) Document Number 82534 Rev. A1.4, 01-Nov-02 TFDU5107 Vishay Semiconductors Ozone Depleting Substances Policy Statement It is the policy of Vishay Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances (ODSs). The Montreal Protocol (1987) and its London Amendments (1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. Vishay Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2. Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency (EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C (transitional substances) respectively. Vishay Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use Vishay Telefunken products for any unintended or unauthorized application, the buyer shall indemnify Vishay Telefunken against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. Vishay Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 (0)7131 67 2831, Fax number: 49 (0)7131 67 2423 Document Number 82534 Rev. A1.4, 01-Nov-02 www.vishay.com 13 (13)