Obsolescence Notice This product is obsolete. This information is available for your convenience only. For more information on Zarlink’s obsolete products and replacement product lists, please visit http://products.zarlink.com/obsolete_products/ KESTX01 400MHz - 460MHz ASK Transmitter Preliminary Information Supersedes September 1996 version, DS4548 - 2.0 DS3969 - 3.8 August 1998 The KESTX01 is a single chip ASK (Amplitude Shift Key) transmitter IC. It is designed to operate in a variety of low power radio applications including keyless entry, general domestic and industrial remote control, RF tagging and local paging systems. The transmitter offers a high level of integration and performance, which enables the harmonic rejection and fundamental power requirements of the ESTI 300 220, and other governing bodies, to be met. The basic architecture utilises a crystal reference oscillator, an integrated frequency multiplying PLL and a power output stage. The design is centred around the popular 433.92MHz operating frequency and particular emphasis has been placed on low current drain, including a power–down feature which greatly increases battery life. XTAL1 1. 41 KESTX01 KESTX01 VEE1 LF LF1 DATA OUTB OUT VCCPA TXEN VCC XTAL2 PWRC VCOTST 7 8 VEE2 MP14 Figure.1 Pin connections - top view ABSOLUTE MAXIMUM RATINGS FEATURES Junction temperature -55 to +150°C Storage temperature -55 to +150°C Supply voltage VEE-0.5 to +8.0V Voltage on any pin VEE -0.5 to VCC+0.5V Notes: 1. The voltage on pin OUT and OUTB (open collector outputs) can support a higher voltage than this (+14V) ■ Low supply Current ■ Power down feature ■ Adjustable output power level ■ Low external part count ■ Fully integrated VCO, PLL and Power Amplifier ORDERING INFORMATION KESTX01/IG/MPAD (Tape and Reel) KESTX01/IG/MPAS (Tubes) VCC VCC TXEN PLL POWER SUPPLY VCCPA PWRC 1 64 DATA PHASE DETECTOR OUT OUT B VEE2 VCO XTAL OSCILLATOR VEE1 XTAL1 XTAL2 LF LF1 VCOTST Figure.2 block diagram KESTX01 ELECTRICAL CHARACTERISTICS Operating conditions T amb = –40°C to + 85°C, VCC = 3.5V to 6.5V. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Parameter Symbol Min Power supply voltage Ambient temperature VCC Ta Value Typ 3.5 –40 Units Conditions Max 6.5 +85 V °C Electro static discharge 2kV all pins – human body model ELECTRICAL CHARACTERISTICS D.C. T amb = –40°C to + 85°C, VCC = 3.5V to 6.5V. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Parameter Symbol Min Value Typ Units Condition Max 0.7 µA V TXEN =0V; V DATA =0V;Ta=25°C VCC = 7V 2.8 4 mA I mod =0 µA; VCC =V TXEN 3.5V V DATA =LOW; 434MHz 6.4 8.5 10.1 mA I mod =150 µA; VCC =V TXEN =3.5V V DATA =HIGH; 434MHz I CC 4 1.6 3.17 5.0 mA I mod =0 µA; VCC =V TXEN =6.5V V DATA =LOW; 434MHz Supply current PLL enable/transmit mark see note 1 I CC 5 6.4 9.8 12.5 mA I mod =150µA; VCC =V TXEN =6.5V V DATA =HIGH; 434MHz TXEN – transmit enable Ven 3.5 VCC +0.2 V TXEN – transmit disable/stand by V VEE –0.2 0.5 V Input bias current TXEN I 150 µA 1.5 V 0.7VCC V CC +0.5 V V EE –0.5 0.3VCC V Supply current stand by mode I CC1 Supply current PLL enable/transmit space I CC 2 1.6 Supply current PLL enable/transmit mark I CC 3 Supply current PLL enable/transmit space dis txen Bias voltage pin PWRC 1.0 Data pin input logic high V Data pin input logic low V il Data pin input current – logic low I Data pin input current – logic high I inh ih inl 1.20 –100 +100 TXEN = VCC transmit enable I mod =150 A V µA VCC = 7V VDATA = 2.1V µA VCC = 7V VDATA = 4.9V CC = 3.5V Notes:– 1. The maximum supply current is directly related to Imod and hence the output power level. (Figure 4) 2 KESTX01 ELECTRICAL CHARACTERISTICS A.C. T amb = –40°C to + 85°C, V CC = 3.5V to 6.5V. These characteristics are guaranteed by either production test, characterisation or design. They apply within the specified ambient temperature and supply voltage ranges unless otherwise stated. Parameter Symbol Min Value Typ Max Units Conditions Output current at fundamental, VCC=3.5V IF75 1.4 2.1 2.8 pk–pk mA I mod =75µA, F o =434MHz Output current at Fundamental, VCC = 3.5V IF150 2.4 3.8 4.9 pk-pk mA I IF150(6V5) 3.0 4.6 5.6 pk–pk mA I mod =150µA, F o =434MHz Output level at 2 x fundamental see note 1 –32 dBc I mod =150µA, F o =434MHz (1) Output level at 3 x fundamental and all other spurii see note 1 –11 dBc I mod =150µA, Fo=434MHz (1) 9.5 µA/rad Output current fundamental VCC = 6.5V Phase detector gain Extinction ratio see note 2 PDG 4.7 ER 40 8 =150µA, Fo =434MHz VCC = 3.5V dB VCO gain G VCO 110 MHz/V TXEN settling time see note 3 Txe 5.0 ms Output sidebands due to reference frequency see note 4 SB –40 dBc I mod =150µA, F o =434MHz (1, 4) 30dB rise timeRF envelope of Data pulse T30R 380 ns 30dB fall timeRF envelope of Data pulse T30F 430 ns VCO operating frequency mod 400 434 460 MHz VCC = 3.5 Notes: 1. The spurii are specified relative to the fundamental, measured in a 300KHz resolution bandwidth. 2. Extinction ratio is defined as the ratio of the output power SPACE to output power MARK measured at the output operating fequency. 3. Regulatory issues demand that transmission does not take place until the PLL has acquired lock and the VCO is operating at its final output frequency. This requirement demands that pin TXEN is set high at least Txe ms prior to the transmission of any data. This value is dependent on the PLL loop bandwidth and hence on the value of the external loop filter component values. The specification value above is for the loop filter components shown in the applications diagram (Figure. 6) 4. Sidebands on the output due to the PLL reference are a function of the PLL loop bandwidth and the application. Reducing the closed loop bandwidth of the PLL loop will aid in reducing the level of the PLL reference spurii. 3 KESTX01 PIN LISTING Signal Description XTAL1 XTAL2 Crystal oscillator Crystal oscillator DATA TXEN Input data Transmit enable/stand by OUT OUTB Power amplifier output/antenna interface Power amplifier output/antenna interface (complementary output) LF Description VCO control input PWRC VCCPA Output power control Power amplifier positive supply VEE2 VEE1 Power amplifier ground PLL ground VCC VCOTST Positive supply VCO test control input Phase detector output FUNCTION When the IC is enabled (TXEN high) a phase locked loop locks the output of the VCO to a multiple of a crystal defined reference input. The output of the VCO operates at the final output frequency and is the input to a power amplifier stage. The power amplifier directly drives the antenna. Phase locked loop Dividers A divide by 64 prescaler is present in the PLL feedback loop. The final output frequency is then Fo = 64xFref. Phase detector The phase detector used is a phase frequency detector (PFD) with a current (charge pump) output. This phase detector has a triangular characteristic for an input phase error in the range –2π <θe < 2π. The charge pump provides an output current in the range ± 50µA and hence gives a phase detector gain of (50/2π ) µA/rad (≈8µA/rad). The advantage of the PFD over a pure phase detector is that it is also a frequency discriminator and will always lock the loop irrespective of the initial frequency offset. The PLL loop characteristics such as lock–up time, capture range, loop bandwidth and VCO reference sideband suppression are controlled by the external loop filter. For certain applications spurious sidebands at the reference frequency must be adequately suppressed and a 3rd order loop is recommended. VCO To minimize external component cost,s the VCO is fully integrated. The frequency of the VCO is controlled by the voltage on pin LF. Reference crystal oscillator A single transistor Collpits crystal oscillator provides a reference clock for the PLL. The oscillator is configured for parallel resonant operation in the fundamental mode (typical operating frequency of 3–7MHz). The crystal is connected between pins XTAL2 and VEE1 with external components as shown in Figure 6. Alternatively, a reference clock can be provided by an external source connected to pin XTAL2 Figure 7. 4 Signal LF1 Output stage (PA) The input signal at pin DATA produces amplitude shift key (ASK) modulation of the VCO output. This is achieved by on–off keying of the bias current in the output power amplifier stage. The output of the PA is a balanced output (pin OUT and OUTB) and is current source driven (open collector outputs). The outputs of which should be D.C. referenced to a positive supply voltage (anticipated to be VCC in most applications). The current source outputs can drive a PCB antenna directly (Figure 6) or if a higher output power is required on limited supply headroom via a simple impedance transforming network. A balanced output stage is used as it automatically suppresses the even order harmonics of the fundamental. In order to obtain the benefits of this output stage it is essential to use a balanced antenna. Power up In the intended application, it is expected that the transmitter will spend a large proportion of time in ‘‘stand by” not transmitting data. To maximise battery life it is important that very little quiescent current is taken in this mode. The ‘‘stand by mode” is selected by setting pin TXEN low and similarly the transmitter is enabled by setting TXEN high. To minimize stand–by current TXEN is used to bias an on– chip npn transistor connected in a common collector configuration (Figure 3 below). This transistor is used to provide the supply to large portions of the IC. Collapsing the supply when TXEN is set low results in a very low stand by current. The voltage on TXEN should not exceed VCC by more than 0.2Volts. From an application standpoint the TXEN pin must be able to source the bias current for the input transistor and should also be decoupled if possible to prevent high frequency noise directly coupling into the IC power supply. The value of the decoupling capacitors and the drive capability of the TXEN source will affect power up delay. Since TXEN enables the PLL it is therefore essential that it is set high prior to any data transmission and that it remains high during the transmission.Therefore three different power drain modes are possible (i) Stand by (TXEN low, DATA low) (ii) PLL Mode/Transmit SPACE (TXEN high, DATA low) (iii) Transmit MARK (TXEN high, DATA high) KESTX01 v CC v CC TXEN v EE power dn power up ACTIVE CIRCUITS v EE 3 Figure 3 TXENFig. power-up operation APPLICATIONS INFORMATION Power control The bias current for the power amplifier directly controls the output current (and hence the output power). The bias current is set by the external resistor connected between PWRC and ground. The bias voltage on pin PWRC is nominally 1.20V and hence the modulation current Imod is given by 1.20/R. To a first order neither the linearity (harmonic spurii relative to fundamental) nor the amplifier efficiency are affected by Imod. The graph below shows typical simulation results for the amplifier current output with Imod variation. OUTPUT CURRENT VS Imod 9 OUTPUT CURRENT (mA) 8 7 6 5 4 3 2 1 37 100 200 300 400 500 600 MODULATION CURRENT Imod (uA) Figure 4 PWRC power output control Frequency accuracy Antenna interface The stability of the output frequency is equal to that of the crystal referenced oscillator and shift in the VCO frequency during data modulation. To operate with a final output accuracy of ± 66KHz at 433.92MHz (as required for use with the receiver KESRX01) would require a crystal with a tolerance specification of ± 150ppm. This tolerance should encompass e.g. initial accuracy, temperature stability and ageing. Operation at a final output frequency of 433.92MHz requires a crystal specified for operation at 6.78MHz. The IC is capable of directly interfacing to a PCB loop antenna as shown in the applications diagram. Figure 4 is an equivalent circuit for a PCB loop antenna. The inductance of the loop is Lant and this is in series with two resistors. These represent Rr the radiation resistance and Rs the series resistance of the antenna. The Q of the antenna is defined as (ωo*Lant/(Rs+Rr) where ωo is the resonant frequency (rad/s) of the antenna. At resonance the antenna can be transformed to the equivalent circuit on the right hand side. Here the equivalent parallel resistance Rp is given by 5 KESTX01 Rp = (Rs+ Rr)(Q 2 + 1) If it is necessary to drive more power into the antenna a possible way to accomplish this is to perform an impedance transformation to the antenna. The antenna also acts as a filter for unwanted, out of band, harmonic spurii. The use of a balanced output suppresses the 2nd harmonic (and other even order harmonics). The 3rd harmonic of the fundamental is not automatically suppressed. However even a Q as low as 10 will reduce the 3rd harmonic by a further 32dB relative to the fundamental. For example, Ls=40nH, fo=433MHz, (Rs+Rr)=2.2Ω, Q=50, gives an equivalent parallel resistance of 5.4kΩ. Typically the antenna will be d.c. referenced to VCC as shown in the applications diagram. The maximum voltage swing across the antenna is therefore limited by the RF saturation voltage of the output PA stage. This is of the order of 0.5V and hence the peak to peak voltage across the antenna will be 2*(VCC–0.5V) e.g. 9V for VCC=5V. This means that the maximum current that can be driven into the load is 1.7mA (peak–peak at the fundamental) and the external power control resistor should be set accordingly. Rr Ct Rs Rp Lant Ct Lant Figure 5 Loop antenna VCC C4 X1 C5 VEE1 VEE1 C2 1 14 2 13 R1 3 12 4 11 5 10 6 9 7 8 ANTENNA L1 L2 ASK MODULATION C1 R2 C3 POWER UP VCC VCCPA VEE2 Figure 6 Application diagram Note: The above application diagram is provided to assist the customer in using the IC and no guarantee can be made as to its correctness. 6 KESTX01 COMPONENT LIST at 433.92MHz COMPONENTS FUNCTION VALUE UNITS R1 OUTPUT POWER CONTROL 2.0 kΩ R2 PLL LOOP FILTER 4.7 kΩ C1 ANTENNA TUNING APPLICATION pF DEPENDENT L1 and L2 ANTENNA TUNING APPLICATION nH C2 PLL LOOP FILTER 220 pF C3 PLL LOOP FILTER 10 nF X1 PARALLEL RESONANT CRYSTAL 6.78 MHz C4 CRYSTAL OSCILLATOR 18 pF C5 CRYSTAL OSCILLATOR 18 pF DEPENDENT Note: The value of C1 is split between two capacitors to aid in balancing the antenna loop reducing the level of the second harmonic TESTABILITY REQUIREMENTS This section is a summary of the observability and controllability requirements identified to simplify the production test requirements of the device. y ) 1. Ability to directly drive the XTAL oscillator from the tester (no crystal). The XTAL2 pin allows direct drive of the oscillator with an external clock source as shown in Figure 7. Typically a 200mVpk clock signal is AC coupled to produce differential output on OP and OPb. (C=10nF, R s (Source) <5kΩ) p C OP CLK Rs XTAL2 OPb XTAL1 Figure 7 Direct drive of crystal oscillator 2. Control of the VCO frequency is obtained via the LF1 signal pin. The output of the dividers is tested by measuring the DC current output of the charge pump (with XTAL2 held at VCC ). 3. DC operation of the power amplifier is observed by measuring the current through the open collector outputs OUT and OUTB. The VCO input to the power amplifier is disabled with VCOTST tied to VCC and the bias current being measured with DATA tied to VCC . Toggling DATA input will modulate the bias current in the power amplifier. 7 Package Code c Zarlink Semiconductor 2003 All rights reserved. ISSUE ACN DATE APPRD. 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