FAIRCHILD MM74HC165MX

Revised February 1999
MM74HC165
Parallel-in/Serial-out 8-Bit Shift Register
General Description
The MM74HC165 high speed PARALLEL-IN/SERIAL-OUT
SHIFT REGISTER utilizes advanced silicon-gate CMOS
technology. It has the low power consumption and high
noise immunity of standard CMOS integrated circuits,
along with the ability to drive 10 LS-TTL loads.
This 8-bit serial shift register shifts data from QA to QH
when clocked. Parallel inputs to each stage are enabled by
a low level at the SHIFT/LOAD input. Also included is a
gated CLOCK input and a complementary output from the
eighth bit.
Clocking is accomplished through a 2-input NOR gate permitting one input to be used as a CLOCK INHIBIT function.
Holding either of the CLOCK inputs high inhibits clocking,
and holding either CLOCK input low with the SHIFT/LOAD
input high enables the other CLOCK input. Data transfer
occurs on the positive going edge of the clock. Parallel
loading is inhibited as long as the SHIFT/LOAD input is
HIGH. When taken LOW, data at the parallel inputs is
loaded directly into the register independent of the state of
the clock.
The 74HC logic family is functionally as well as pin-out
compatible with the standard 74LS logic family. All inputs
are protected from damage due to static discharge by internal diode clamps to VCC and ground.
Features
■ Typical propagation delay: 20 ns (clock to Q)
■ Wide operating supply voltage range: 2–6V
■ Low input current: 1 µA maximum
■ Low quiescent supply current: 80 µA maximum (74HC
Series)
■ Fanout of 10 LS-TTL loads
Ordering Code:
Order Number
MM74HC165M
MM74HC165SJ
MM74HC165MTC
MM74HC165
Package Number
Package Description
M16A
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
M16D
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MTC16
N16E
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
Pin Assignments for DIP, SOIC, SOP and TSSOP
Internal Output
Shift/ Clock Clock Serial Parallel Outputs
A. . .H QA
Load Inhibit
a
QH
QB
L
X
X
X
a. . .h
H
L
L
X
X
b
H
L
↑
H
X
H
QAN
QGN
H
L
↑
L
X
L
QAN
QGN
H
H
X
X
X
QA0 QB0
QH0
QA0 QB0
h
QH0
H = HIGH Level (steady state), L = LOW Level (steady state)
X = Irrelevant (any input, including transitions)
↑ = Transition from LOW-to-HIGH level
QA0, QB0, QH0 = The level of QA, QB, or QH, respectively, before the indicated steady-state input conditions were established.
QAN, QGN = The level of QA or QG before the most recent ↑ transition of the
clock; indicates a one-bit shift.
Top View
© 1999 Fairchild Semiconductor Corporation
DS005316.prf
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MM74HC165 Parallel-in/Serial-out 8-Bit Shift Register
September 1983
MM74HC165
Logic Diagrams
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2
Recommended Operating
Conditions
−0.5 to +7.0V
Supply Voltage (VCC)
DC Input Voltage (VIN)
−1.5 to VCC +1.5V
DC Output Voltage (VOUT)
−0.5 to VCC +0.5V
Clamp Diode Current (IIK, IOK)
±20 mA
DC Output Current, per pin (IOUT)
±25 mA
Max
Units
2
6
V
0
VCC
V
−40
+85
°C
(tr, tf) VCC = 2.0V
1000
ns
VCC = 4.5V
500
ns
VCC = 6.0V
400
ns
DC Input or Output Voltage
(VIN, VOUT)
Operating Temperature Range (TA)
±50 mA
DC VCC or GND Current, per pin (ICC)
Storage Temperature Range (TSTG)
Min
Supply Voltage (VCC)
Input Rise or Fall Times
−65°C to +150°C
Power Dissipation (PD)
(Note 3)
600 mW
S.O. Package only
500 mW
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
Lead Temperature (TL)
(Soldering 10 seconds)
DC Electrical Characteristics
Symbol
VIH
VIL
VOH
Parameter
Note 2: Unless otherwise specified all voltages are referenced to ground.
260°C
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
(Note 4)
Conditions
VCC
TA = 25°C
Typ
TA = −40 to 85°C TA = −55 to 125°C
Guaranteed Limits
Units
Minimum HIGH Level
2.0V
1.5
1.5
1.5
V
Input Voltage
4.5V
3.15
3.15
3.15
V
6.0V
4.2
4.2
4.2
V
Maximum LOW Level
2.0V
0.5
0.5
0.5
V
Input Voltage
4.5V
1.35
1.35
1.35
V
6.0V
1.8
1.8
1.8
V
Minimum HIGH Level
VIN = VIH or VIL
Output Voltage
|IOUT| ≤ 20 µA
2.0V
2.0
1.9
1.9
1.9
V
4.5V
4.5
4.4
4.4
4.4
V
6.0V
6.0
5.9
5.9
5.9
V
|IOUT| ≤ 4.0 mA
4.5V
4.2
3.98
3.84
3.7
V
|IOUT| ≤ 5.2 mA
6.0V
5.7
5.48
5.34
5.2
V
VIN = VIH or VIL
VOL
Maximum LOW Level
VIN = VIH or VIL
Output Voltage
|IOUT| ≤ 20 µA
2.0V
0
0.1
0.1
0.1
V
4.5V
0
0.1
0.1
0.1
V
6.0V
0
0.1
0.1
0.1
V
|IOUT| ≤ 4.0 mA
4.5V
0.2
0.26
0.33
0.4
V
|IOUT| ≤ 5.2 mA
6.0V
0.2
0.26
0.33
0.4
V
VIN = VCC or GND
6.0V
±0.1
±1.0
±1.0
µA
6.0V
8.0
80
160
µA
VIN = VIH or VIL
IIN
ICC
Maximum Input
Current
VCC = 2−6V
Maximum Quiescent
VIN = VCC or GND
Supply Current
IOUT = 0 µA
VCC = 2−6V
Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occur for HC at 4.5V. Thus the 4.5V values should be used when
designing with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current (IIN, ICC, and IOZ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
3
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MM74HC165
Absolute Maximum Ratings(Note 1)
(Note 2)
MM74HC165
AC Electrical Characteristics
VCC = 5V, TA = 25°C, CL = 15 pF, tr = tf = 6 ns
Symbol
Parameter
Conditions
Typ
Guaranteed
Limit
Units
fMAX
Maximum Operating Frequency
50
30
MHz
tPHL, tPLH
Maximum Propagation Delay H to QH or Q H
15
25
ns
tPHL, tPLH
Maximum Propagation Delay
13
25
ns
15
25
ns
10
20
ns
Serial Shift/Parallel Load to QH
tPHL, tPLH
Maximum Propagation Delay
Clock to Output
tS
Minimum Setup Time Serial Input
to Clock, Parallel or Data to Shift/Load
tS
Minimum Setup Time Shift/Load to Clock
11
20
ns
tS
Minimum Setup Time Clock Inhibit to Clock
10
20
ns
tH
Minimum Hold Time Serial
0
ns
16
ns
Input to Clock or
Parallel Data to Shift/Load
tW
Minimum Pulse Width Clock
AC Electrical Characteristics
CL = 50 pF, tr = tf = 6 ns (unless otherwise specified)
Symbol
fMAX
tPHL, tPLH
tPHL, tPLH
tPHL, tPLH
tS
tS
tS
tH
tW
tTHL, tTLH
tr, tf
Parameter
Conditions
VCC
TA = 25°C
TA = −40 to 85°C TA = −55 to 125°C
Typ
Units
Guaranteed Limits
Maximum Operating
2.0V
10
5
4
4
MHz
Frequency
4.5V
45
27
21
18
MHz
6.0V
50
32
25
21
MHz
Maximum Propagation
2.0V
70
150
189
225
ns
Delay H to QH or Q H
4.5V
21
30
38
45
ns
6.0V
18
26
33
39
ns
2.0V
70
175
220
260
ns
Maximum Propagation
Delay Serial Shift/
4.5V
21
35
44
52
ns
Parallel Load to QH
6.0V
18
30
37
44
ns
Maximum Propagation
2.0V
70
150
189
225
ns
Delay Clock to Output
4.5V
21
30
38
45
ns
6.0V
18
26
33
39
ns
Minimum Setup Time
2.0V
35
100
125
150
ns
Serial Input to Clock,
4.5V
11
20
25
30
ns
or Parallel Data to Shift/Load
6.0V
9
17
21
25
ns
Minimum Setup Time
2.0V
38
100
125
150
ns
Shift/Load to Clock
4.5V
12
20
25
30
ns
6.0V
9
17
21
25
ns
Minimum Setup Time
2.0V
35
100
125
150
ns
Clock Inhibit to Clock
4.5V
11
20
25
30
ns
6.0V
9
17
21
25
ns
Minimum Hold Time Serial
2.0V
0
0
0
ns
Input to Clock or
4.5V
0
0
0
ns
Parallel Data to Shift/Load
6.0V
0
0
0
ns
Minimum Pulse Width,
2.0V
80
100
120
ns
Clock
4.5V
9
16
20
24
ns
6.0V
8
14
18
20
ns
Maximum Output
2.0V
30
75
95
110
ns
Rise and Fall Time
4.5V
9
15
19
22
ns
6.0V
8
13
16
19
ns
30
Maximum Input Rise and
2.0V
1000
1000
1000
ns
Fall Time
4.5V
500
500
500
ns
6.0V
400
400
400
ns
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4
Symbol
CPD
Parameter
Power Dissipation
(Continued)
Conditions
VCC
(per package)
TA = 25°C
Typ
TA = −40 to 85°C TA = −55 to 125°C
Units
Guaranteed Limits
100
pF
Capacitance (Note 5)
CIN
Maximum Input Capacitance
5
10
10
10
pF
Note 5: CPD determines the no load dynamic power consumption, PD = CPD VCC2f + ICC VCC, and the no load dynamic current consumption,
IS = CPD VCC f + ICC.
5
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MM74HC165
AC Electrical Characteristics
MM74HC165
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow
Package Number M16A
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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6
MM74HC165
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
7
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MM74HC165 Parallel-in/Serial-out 8-Bit Shift Register
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), MS-001, 0.300” Wide
Package N16E
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
2. A critical component in any component of a life support
1. Life support devices or systems are devices or systems
device or system whose failure to perform can be reawhich, (a) are intended for surgical implant into the
sonably expected to cause the failure of the life support
body, or (b) support or sustain life, and (c) whose failure
device or system, or to affect its safety or effectiveness.
to perform when properly used in accordance with
instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the
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user.
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.