R I Q U I N T S E M I C O N D U C T O R, I N C . TQ2060 VDD TESTIN REFCLK GND NC NC 11 NC GND Figure 1. Pinout Diagram 10 9 8 7 6 5 High-Frequency Clock Generator 4 NC 12 Phase Detector ÷10 VCO NC 13 TEST1 14 TEST2 15 NC 16 NC 17 27 NC GND 18 26 AVDD MUX ÷2 3 NC 2 NC 1 NC MUX Control 19 20 21 22 23 24 25 EVDD PDR2 QN Q PDR1 GND AGND 28 NC TriQuint’s TQ2060 is a high-frequency clock generator. It utilizes a 35 MHz to 50 MHz TTL input to generate a 350 MHz to 500 MHz PECL output. The TQ2060 has a completely self-contained Phase-Locked Loop (PLL) running at 700 MHz to 1000 MHz. This stable PLL allows for a low period-to-period output jitter of 70 ps (max), and enables tight duty cycle control of 55% to 45% (worst case). The TQ2060 provides optional 200 ohm on-chip pull-down resistors which are useful if the output is AC-coupled to the device being driven. In order to use these resistors, pin 20 (PDR2) should be connected to pin 21 (QN), and pin 23 (PDR1) should be connected to pin 22 (Q). Features • Output frequency range: 350 MHz to 500 MHz • One differential PECL output: 600 mV (min) swing • Common-mode voltage: VDD –1.2 V (max), VDD –1.6 V (min) • Period-to-period output jitter: 25 ps peak-to-peak (typ) 70 ps peak-to-peak (max) SYSTEM TIMING PRODUCTS T • Reference clock input: 35 MHz to 50 MHz TTL-level crystal oscillator • Self-contained loop filter • Optional 200-ohm pull-down resistors for AC-coupled outputs • +5 V power supply • 28-pin J-lead surface-mount package • Ideal for designs based on DEC Alpha AXP™ processors Various test modes on the chip simplify debug and testing of systems by slowing the clock output or by bypassing the PLL. For additional information and latest specifications, see our website: www.triquint.com 1 TQ2060 Figure 2. Simplified Block Diagram Phase Detector REFCLK (35MHz to 50 MHz) ÷ 10 VCO MUX ÷2 MUX QN (350 MHz to Q 500 MHz) TESTIN TEST1 Control TEST2 Table 1. Mode Selection TEST1 TEST2 TESTIN 1 REFCLK Q, QN 1(Test) 2 (Test) 3 (Test) 4 (Bypass) 0 0 1 1 0 1 0 1 fTESTCLK “don’t care” fTESTCLK 0 “don’t care” “don't care” “don't care” fREFCLK fREFCLK2 ÷ 20 0, 1 fTESTCLK ÷ 2 fREFCLK 5 (Normal 1 1 1 fREFCLK 10 x fREFCLK3 Mode Notes: 1. In modes 1 and 3, TESTIN may be used to bypass the PLL. A clock input at TESTIN will be divided as shown. 2. REFCLK = 35 MHz to 50 MHz. 3. Q, QN = 350 MHz to 500 MHz. Figure 3. Recommended Layout (Not to scale) Pin 1 VDD 0.1 µF GND GND Q 50 OHMS QN REFCLK (from TTLoscillator) VDD GND 0.1 µF VDD 0.1 µF (From TTL Oscillator) GND 2 For additional information and latest specifications, see our website: www.triquint.com TQ2060 Table 2. Absolute Maximum Ratings Storage Temperature –65°C to +150°C Ambient temperature with power applied –55°C to +110°C Supply voltage to ground potential DC input voltage –0.5 V to +7.0 V –0.5 V to (VDD + 0.5) V DC input current Package thermal resistance (MQuad) –30 mA to +5 mA θJA = 45°C/W Die junction temperature TJ = 150°C Note: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. The device should be operated only under the DC and AC conditions shown below. Symbol Description Test Conditions Min VOH VOL VCMO ∆ VOUT VIH2 Output HIGH voltage Output LOW voltage Output common mode voltage Output differential voltage Input HIGH level VIL2 Input LOW level IIL IIH Input LOW current Input HIGH current VCC = Min PECL load VCC–1.20 VCC = Min PECL load VCC–2.00 PECL VCC–1.60 PECL 0.6 Guaranteed input logical 2.0 HIGH Voltage for all inputs Guaranteed input logical LOW Voltage for all inputs VDD = Max VIN = 0.40 V VDD = Max VIN = 2.7 V II IDDS3 Input HIGH current Power supply current VDD = Max VIN = 5.3 V VDD = Max VI Input clamp voltage VDD = Min IIN = –18 mA Typ Max Unit VCC–0.50 VCC–1.60 VCC–1.20 1.2 V V V V V 0.8 V –150 0 –400 25 2 85 1000 120 µA µA µA mA –0.70 –1.2 V Typ Max Unit SYSTEM TIMING PRODUCTS Table 3. DC Characteristics (VDD = +5 V + 5%, TA = 0 °C to +70 °C) 1 Table 4. Capacitance Symbol CIN COUT Description Test Conditions Input Capacitance Output Capacitance VIN = 2.0 V at f = 1 MHz VOUT = 2.0 V at f = 1 MHz Min 6 9 pF pF Notes: 1. Typical limits are at VDD = 5.0 V and TA = 25˚C. 2. These are absolute values with respect to device ground and include all overshoots due to system or tester noise. 3. This parameter is measured with device not switching and unloaded. For additional information and latest specifications, see our website: www.triquint.com 3 TQ2060 Table 5. AC Characteristics (VDD = +5 V + 5%, TA = 0 °C to +70 °C) Symbol Input Clock (REFCLK) Test Conditions (Figure 5) Min Typ Max Unit tCPWH CLK pulse width HIGH Figure 5 4 — — ns tCPWL tIR CLK pulse width LOW Input rise time (0.8 V – 2.0 V) Figure 5 4 — — — — 2.0 ns ns Symbol Output Clock (Q, QN) Test Conditions (Figures 4 & 5)1 Min Typ Max Unit tOR, tOF Rise/fall time (20% – 80%) Figure 5 100 220 350 ps tCYC tJP2 tSYNC3 Duty-cycle Period-to-Period Jitter Synchronization Time Figure 5 45 — — 50 25 10 55 70 500 % ps µs Notes: 1. All measurements are tested with a REFCLK having a rise time of 0.5 ns (0.8 V to 2.0 V). 2. Jitter specification is peak to peak. Period-to-Period jitter is the jitter on the output with respect to the output's previous crossing. 3. tSYNC is the time required for the PLL to synchronize and assumes the presence of a CLK signal. Figure 4. PECL Test Load 4 Figure 5. REFCLK and Q-QN Timing For additional information and latest specifications, see our website: www.triquint.com TQ2060 Figure 6. 28-Pin MQuad J-Leaded Package Mechanical Specification .172 ±.005 .490 ±.005 .132 ±.005 .445 ±.005 .045 X 45°° .040 MIN PIN 1 8 .490 ±.005 22 .445 .028 ±.005 .445 ±.005 .018 .050 TYP. 0.125 VENT PLUG 15 .015 X 45°° .410 ±.015 .060 .104 ±.005 .050 TYP. NON-ACCUM. (All dimensions in inches) Pin # Pin Name Description I/O Pin # Pin Name Description I/O 1 2 3 NC NC NC No Connect No Connect No Connect — — — 15 16 17 TEST2 NC NC Test Control 2 No Connect No Connect I — O 4 5 6 7 8 9 10 11 12 13 14 NC NC NC GND REFCLK TESTIN NC GND VDD NC TEST1 No Connect No Connect No Connect Ground Reference Clock Test Input No Connect Logic Ground Logic VDD (+5 V) No Connect Test Control 1 — — — — I I — — — — I 18 19 20 21 22 23 24 25 26 27 28 GND EVDD PDR2 QN Q PDR1 GND AGND AVDD NC NC Ground VDD for ECL Output (+5 V) Pull-down Resistor 2 (200 Ω) Differential PECL Output (–) Differential PECL Output (+) Pull-down Resistor 1 (200 Ω) Ground Analog Ground Analog VDD (+5 V) No Connect No Connect — — I O O I — — — — — For additional information and latest specifications, see our website: www.triquint.com SYSTEM TIMING PRODUCTS Table 6. 28-Pin MQuad Pin Description 5 TQ2060 Ordering Information To order, please specify as shown below: TQ2060-MC High-Frequency Clock Generator Temperature range: 0°C to 70°C (Commercial) Package: 28-Pin MQuad Additional Information For latest specifications, additional product information, worldwide sales and distribution locations, and information about TriQuint: Web: www.triquint.com Email: [email protected] Tel: (503) 615-9000 Fax: (503) 615-8900 For technical questions and additional information on specific applications: Email: [email protected] The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or omissions. TriQuint assumes no responsibility for the use of this information, and all such information shall be entirely at the user's own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems. Copyright © 1997 TriQuint Semiconductor, Inc. All rights reserved. Revision 1.0.A October 1997 6 For additional information and latest specifications, see our website: www.triquint.com