T
R
I
Q
U
BLANK
I
N
T
A5
A4
A0
B0
S E M I C O N D U C T O R, I N C .
B4
B5
TQ6122
A7 (MSB)
A6
B6
B7
ECL INPUT
BUFFERS
MULTIPLEXER
V SS
(-5 V)
D
DGND
CLK
CLK
BLANKING
LOGIC
Q
BLANK D0
D4
D5
D6
D7
QBLANK Q0
Q4
Q5
Q6
Q7
+
–
MASTER
LATCH
Features
BINARY-TO-N-OF-7
SEGMENT ENCODER
(EXT. CONTROL LOOP)
BLANK D0
D4
S1 S2 S3 S4 S5 S6 S7
QBLANK Q0
Q4
QS1
SLAVE
LATCH
QS7
VOUT
FULL-SCALE ADJUST
VOUT
+
–
BANDGAP
REFERENCE
V REF
I BLANK I0
I4
IS1
IS7
50
50
CURRENT-SOURCE ARRAY
VSENSE
A GND
BLANK DISABLE
IREF
V AA (-5V)
1 Gigasample/sec,
8-bit Digital-to-Analog
Converter
VAA
TriQuint's TQ6122 GIGADAC™ is a monolithic, 8-bit digital-to-analog
converter capable of conversion rates to at least 1000 Megasamples/
second. The TQ6122 DAC may be used for display generation, waveform
and signal synthesis, and video signal reconstruction. The TQ6122 features
a 2:1 data MUX at the input for ease of interface and offers synchronous
blanking capability for maximum ease of use in video applications. It drives
complementary 1 V peak-to-peak swings into 50-ohm loads; on-chip 50ohm reverse terminations provide extremely fast settling time.
Due to the inherently high speed of TriQuint's one-micron gate
Enhancement / Depletion-mode gallium arsenide process, the TQ6122
offers guaranteed operation at clock rates of 1000 MHz, with typical room
temperature conversion rates of 1.5 Gs/s without multiplexing and 1.3 Gs/s
when using multiplexed inputs. The TQ6122 features output rise and fall
times of 500 ps (10% – 90%), symmetric complementary output transitions,
and glitch impulse values less than 10 pV/sec. When used for sine wave
synthesis, typical spurious and harmonic free dynamic range is ≥45 dBc.
• 1 Gs/s conversion rate
• 8-bit resolution
• DC differential non-linearity
1/ LSB (0.2%)
2
• DC integral non-linearity
1 LSB (0.4%)
• Settling time 2 ns to 0.4% (est.)
MIXED SIGNAL
PRODUCTS
SELA
• Spurious-free dynamic range
(SFDR) 45 dBc typical
• ECL-compatible inputs
• Synchronous blanking input
• 1.3 W power dissipation
• 44-pin multilayer ceramic
package or unpackaged die
Applications
• Display generation
• Waveform and signal synthesis
• Video signal reconstruction
The TQ6122 may be retrofitted into designs which currently use TriQuint's
TQ6111, 2, 3, 4M DACs with minimal changes to power supply levels and
input and output connections. The part is available in a 44-pin ceramic
package or as unpackaged die.
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1
TQ6122
Specifications
Table 1. Absolute Maximum Ratings (1,2)
Symbol
Description
Min
Typ
Max
Units
AGND, DGND
VSS
Analog and digital ground
Digital power
–2
–7
+2
V
V
VAA
VO, VO (MAX)
Analog power
Analog output (1 V F.S.)
–10
–2.5
+2.5
VI (MAX)
Digital input levels
VSS –0.5
+0.5
V
II (MAX)
PD
Digital input currents
Power dissipation
–1
+1
3.0
mA
W
TC
TS
Case backside temperature
Storage temperature
–65
–65
+135
+150
°C
°C
V
V
Notes: 1. Unless otherwise specified: AGND = DGND = 0 V, VSS = VAA = –5 V, VFS = 1 V pk–pk, case temperature = 27 °C.
2. Exceeding the absolute maximum ratings may damage the device. The value shown for a particular
parameter is determined with all other parameters at their nominal values.
Table 2. DC Characteristics (1)
Symbol
Description
Test Conditions
Min.
VAA
IAA
VSS
ISS
Analog supply
VAA current
Digital supply
VSS current
Note 2
VFS = 1 V pk–pk
Note 2
–5.25
50
–5.5
145
PD
VECLREF
IECLREF
RECLREF
CECLREF
VIH(DC)
VIL(DC)
VCLKH (DC),
VCLKH (DC)
VCLKL (DC),
VCLKL (DC)
IIN
CIN
VOUT (MAX),
VOUT (MAX)
VOUT (MIN),
VOUT (MIN)
Power dissipation
ECL reference level
ECL ref. input bias current
ECL ref. input resistance
ECL ref. input capacitance
Data input HIGH (ECL)
Data input LOW (ECL)
Clock HIGH input
0.9
Note 3, Figure 1
–1.5
Note 3, Figure 1 ∆VECLREF = ±0.2 V –5
Figure 1
Clock LOW input
Differential clock, Note 4
DC value (VECLREF = –1.3 V)
DC value (VECLREF = –1.3 V)
Differential clock, Note 4
200
–4.75
80
–4.5
265
V
mA
V
mA
1.85
–1.1
+5
–500
–1500
–0.7
VTT
VECLREF –0.3
V
+25
uA
pF
V
–25
Minimum absolute output level
–1.5
1.3
–1.3
0
50
2
Unit
–1100
VTT
VECLREF +0.3
0.5
+1
(Continued on next page)
2
62
Max.
W
V
mA
Ω
pF
mV
mV
V
Data, clock input bias current
VIH = –800 mV, VIL = –1800 mV
Data, clock input capacitance
In multilayer ceramic package
Maximum absolute output level Note 5
Note 5
Typ.
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V
TQ6122
Table 2. DC Characteristics (1) (continued)
Description
Full-scale output swing
VZS
Zero-scale offset
∆DVBLANK
Blanking interval
VBLANK_DISABLE Blank current disable control
VREF
VREF input voltage
VSENSE
IVREF
VSENSE output
VREF input current
IREF
VIREF
ROUT, ROUT
COUT
DNL
INL
Ext. reference current output
IREF terminal voltage
VOUT, VOUT output resistance
Matching of ROUT, ROUT
VOUT, VOUT output capacitance
Test Conditions
Min
Data bits only, 0–0/1–1 input step
0
RL = 50 Ω load
VFS = 1 V, no external offset,
VBLANK_DISABLE = 0 V
Blank input = 1, Notes 6, 7
9
Blank current ON
Blank current OFF
VFS = 1 V peak-to-peak
VAA +0.7
VFS = 0 V peak-to-peak
VAA –1
VFS = 1 V peak-to-peak
VREF = VAA +0.65
VREF = VAA +1.1
VFS = 1 V peak-to-peak
2
–1.5
44
Resolution
Monotonicity
Differential non-linearity
Integral non-linearity
Full-scale symmetry
(± 1/2 LSB)
(± 1 LSB)
VFS = 1 V peak-to-peak, Note 8
VFS temperature coefficient
Note 9
Typ
1
Max
1.125
Unit
V pk–pk
–35
mV
12
%VFS
–5 (VAA)
0 (AGND)
VAA +1.0
10.4
VAA +1.4
V
V
V
VAA +0.8
VAA +1.1
V
V
10
2.5
50
0.2
0.3
8
8
–4
uA
mA
mA
V
Ω
%
pF
1
5
+1
57
2.5
0.2
0.4
+4
Bits
Bits
% F.S.
% F.S.
mV
Notes: 1. Unless otherwise specified: VAA = –5V ± 5%, VSS = –5 V ±10%, VTT = –2V ± 5%, VFS = 1 V pk–pk, TCASE = 0 to +85 °C
2. See the "Power Supplies, Ground and Bypassing" section later in this datasheet for discussion of power supplies.
3. The ECL reference input establishes the switching point for the ECL line receivers used at the DATA, BLANK, and
SELECT inputs. (See Figure 1.) IECLREF is the current required to change the internal ECLREF value by about ±200 mV.
4. Values shown are for differential clock drive, and apply to both CLOCK and CLOCK inputs. For single-ended drive,
the HIGH level should be at least (VECLREF +0.5) volts, but must not exceed –700 mV. The LOW level should be
(VECLREF –0.5) volts, but must not go below VTT, where VTT is the ECL termination voltage (nominal VTT = –2 V).
5. VOUT(MAX), VOUT(MAX), VOUT(MIN), VOUT(MIN) represent the limits on the absolute output levels, including offset.
6. Blanking interval is the voltage change (as a percentage of the full-scale output swing) added to VFS when BLANK is asserted.
7. The BLANK DISABLE input turns OFF the blank current (DVBLANK = 0) when held at AGND, and turns it ON when pulled to VAA.
8. Full-scale symmetry is a measure of the balance between VOUT and VOUT. For a full-scale input change (00000000 –> 1111111),
␣ ␣ ␣ ␣ the change in VOUT will match the change in VOUT to within ± 4 mV (1 LSB @ 1 V peak-to-peak).
9. The VFS temperature coefficient is determined primarily by the external reference and loop control op amp.
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3
MIXED SIGNAL
PRODUCTS
Symbol
VFS
TQ6122
Table 3. AC Characteristics (1,2)
Symbol
Description
Test Conditions
Min
Typ
Max
FCLK (MAX)
Maximum clock frequency
Unmuxed operation
Muxed operation
1000
1000
1500
1300
MHz
MHz
TRCLK,DATA
TFCLK,DATA
Clock, data input rise time
Clock, data input fall time
20% to 80%
20% to 80%
300
300
ps
ps
TWH
Duration of clock HIGH
Percentage of clock period
40
50
60
%
TWL
TSETUP
Duration of clock LOW
Data, control setup time
Percentage of clock period
See Figure 7
40
50
60
%
ps
THOLD
Data, control hold time
See Figure 7
TROUT
TFOUT
TSETTLE
Output rise time
Output fall time
Output settling time
Glitch impulse
10% to 90%
10% to 90%
Within ±0.4% of final value
ps
300
300
2
10
Notes: 1. Unless otherwise specified: VAA = –5V ± 5%, VSS = –5 V + 10% , VFS = 1 V p–p, TCASE = 0 to +85 °C,
VECL = –1.3 V, VIH = –0.8 V, VIL = –1.8 V
2. Applies to packaged parts only.
Figure 1. ECL Reference Input Equivalent Circuit
SELA
BLANK
A7, B7
50 Ω
I ECLREF
50 Ω
-1.3V
(Nominal,
internal)
RECLREF,
CECLREF
ECL INPUT BUFFERS
2 pF
EXTERNAL ECL
REFERENCE
INPUT
50 Ω
A0, B0
+
–
–
+
VSS
-5 V
Figure 2. Definition of VIH, VIL for Data and BLANK Inputs
VIH (MAX)
V IH
VIH (MIN)
V ECL (-1.3 V NOMINAL)
VIL (MAX)
V IL
VIH (MIN)
4
Unit
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ps
ps
ns
pV/sec
TQ6122
Figure 3. Typical Digital Input Circuit (Including CLOCK Inputs)
R
MICROSTRIP
DAC
INPUT PROTECTION
NETWORK
500
IN,
C IN
50
TO INPUT
BUFFER
INPUT
50
50
V TT
–2 V
500
VSS
–5 V
Figure 4. VOUT, VOUT, and Input Code Relationships for (A) Typical Instrumentation and (B) Video Configurations
Input Code
VOUT (1)
VOUT (1)
Full Scale
Full Scale – 1 LSB
Half Scale + 1 LSB
Half Scale
Half Scale –1 LSB
11111111
11111110
10000001
10000000
01111111
–0.996 V
–0.992 V
–0.504 V
–0.500 V
–0.496 V
␣ 0.000 V
–0.004 V
–0.492 V
–0.496 V
–0.500 V
Zero Scale + 1 LSB
Zero Scale
00000001
00000000
–0.004 V
␣ 0.000 V
–0.992 V
–0.996 V
MIXED SIGNAL
PRODUCTS
(A) TQ6122 Instrumentation DAC operation (1 V Full-Scale)
Blanking current is shunted to ground by tying BLANK DISABLE to AGND and forcing BLANK = 0.
(B) TQ6122 Video DAC Operation (0.679 V Full-Scale)
Blanking current is enabled by connecting BLANK DISABLE to VAA.
Full Scale
Full Scale – 1 LSB
Half Scale + 1 LSB
Half Scale
Half Scale – 1 LSB
Zero Scale + 1 LSB
Zero Scale
BLANK = HIGH
Input Code
VOUT (1)
VOUT (1)
11111111
11111110
10000001
10000000
01111111
00000001
00000000
X.....X
–0.679 V
–0.676 V
–0.343 V
–0.341 V
–0.338 V
–0.003 V
␣ 0.000 V
–0.750 V
–0.071 V
–0.074 V
–0.407 V
–0.409 V
–0.412 V
–0.747 V
–0.750 V
␣ 0.000 V
Notes: 1. All values shown for VOUT and VOUT assume identical load resistors (RL1 and RL2 in Figure 5),
and no externally imposed output offset voltage (VOS in Figure 5). Zero-scale offset is ignored.
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5
TQ6122
Figure 5. Output Equivalent Circuit, Showing Terminated 50-ohm Transmission Line Loads
R OUT, C OUT
IOUT
Z 0 = 50
NON-INVERTING OUTPUT (VOUT )
1000 pF
50
RL1
50
R T1
V OS (SEE FIG. 18)
(–3V TO +4V)
0.1uF
100 pF
DIGITAL
INPUT
50
R T2
AGND
50
RL2
(FOR NO OUTPUT OFFSET)
INVERTING OUTPUT (VOUT )
I OUT
Z 0 = 50
"FAR-END" TERMINATIONS
BOUNDARY
OF DAC
Figure 6. Definition of TWH and TWL
T WL(CLK)
50%
T WH(CLK)
6
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TQ6122
Figure 7. TQ6122 Data and Control Timing
CLOCK
TDS
TDH
DATA
TSS
TSH
Symbol
TDS
TDH
TSS
TSH
Description
(1)
Data setup time
Data hold time (2)
SELA setup time (1,3)
SELA hold time (2,3)
Typical @ 25 °C
Unit
0
+325
+350
–100
␣ ps
␣ ps
␣ ps
␣ ps
MIXED SIGNAL
PRODUCTS
SELA
Notes: 1. Setup time is defined to be positive for data or control transitions occurring before the negative-going edge of the clock.
2. Hold time is defined to be positive for data or control transitions occurring after the negative-going edge of the clock.
3. While SELA does not strictly have a setup and hold time, it is convenient to express its allowed transition
region limits in these terms.
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7
TQ6122
VAA
IREF
ECL REF
A0
A1
DGND
A2
A3
A4
A5
VSS
VSENSE
BLANK DISABLE
AGND
VOUT
VOUT
AGND
AGND
AGND
VSS
12
11
23
TQ6122AM
TOP VIEW
OF MLC-44 PACKAGE
AS IT SITS ON
CIRCUIT BOARD
(CAVITY IS DOWN)
PIN 1
34
VSS
CLOCK
CLOCK
N/C
SELA
DGND
BLANK
B7
B6
B5
VSS
A7
DGND
B0
B1
DGND
B2
B3
B4
VSS
Since the TQ6122 dissipates on the order of 1.3 W,
adequate heat sinking is essential for proper operation
of the device. Figure 12 shows one possible heat sink
arrangement based on a multi-finned “Top Hat” heat
sink available from Thermalloy. An environment with a
minimum of 100 fpm (feet per minute) of forced air
cooling is assumed; >200 fpm is preferred.
VAA
VREF
The TQ6122 DAC is packaged in a proprietary 44-pin
multilayer ceramic package which provides high-speed,
controlled-impedance interconnects and integral power
supply bypassing. The leads are set on 0.050” centers,
and are formed for gull-wing surface mounting. Figure
8 shows the pinout diagram of the packaged IC as seen
from the top, opposite the cavity side; Figure 9 lists pin
numbers, names and I/O levels. Figure 10 illustrates
the pertinent dimensions of the package and Figure 11
shows the mounting footprint.
Figure 8. TQ6122 Pinout
VSS
A6
Mechanical Characteristics
Notes: 1. A7, B7 = MSB inputs
2. N/C = no internal connection
Figure 9. TQ6122 Pin Descriptions
Pin
Signal
Interface Level (Typ.)
Pin
Signal
Interface Level (Typ.)
1, 11, 12,
VSS
–5 V
21
VREF
VAA +1, for VFS = 1V pk–pk
22, 23
VAA
–5 V
2
B5
600 mV pk–pk centered at –1.3 V @ DC
24
IREF
2.5 mA for VFS = 1V pk–pk
3
B6
600 mV pk–pk centered at –1.3 V @ DC
25
ECL REF
–1.3 V
4
B7 (MSB)
600 mV pk–pk centered at –1.3 V @ DC
26
A0 (LSB)
600 mV pk–pk centered at –1.3 V @ DC
5
BLANK
600 mV pk–pk centered at –1.3 V @ DC
27
A1
600 mV pk–pk centered at –1.3 V @ DC
6, 28,
37, 40
DGND
0V
29
A2
600 mV pk–pk centered at –1.3 V @ DC
7
SELA
600 mV pk–pk centered at –1.3 V @ DC
30
A3
600 mV pk–pk centered at –1.3 V @ DC
8
—
No connection
31
A4
600 mV pk–pk centered at –1.3 V @ DC
9
10
CLOCK
CLOCK
1V pk–pk centered at –1.3 V @ AC
1V pk–pk centered at –1.3 V @ AC
32
A5
600 mV pk–pk centered at –1.3 V @ DC
35
A6
600 mV pk–pk centered at –1.3 V @ DC
13–15, 18
AGND
0V
36
A7 (MSB)
600 mV pk–pk centered at –1.3 V @ DC
16
17
VOUT
VOUT
0 V to –1 V
–1 V to 0 V
38
B0 (LSB)
600 mV pk–pk centered at –1.3 V @ DC
39
B1
600 mV pk–pk centered at –1.3 V @ DC
19
BLANK
DISABLE
Enable = VAA
(IBLANK = ON)
Disable = AGND (IBLANK = OFF)
41
B2
600 mV pk–pk centered at –1.3 V @ DC
42
B3
600 mV pk–pk centered at –1.3 V @ DC
20
VSENSE
VAA + 0.8, for VFS = 1 V pk–pk
43
B4
600 mV pk–pk centered at –1.3 V @ DC
33, 34, 44
8
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TQ6122
Figure 10. Package Dimensions
0.050
0.015
0.035
0.125
PIN 12
0.65
SQUARE
TOP VIEW
0.805
NOMINAL
PIN 1
0.060
All Dimensions in Inches
0.005
Figure 11. Mounting Footprint
PIN 12
MIXED SIGNAL
PRODUCTS
PIN 23
0.425
0.025
0.350
0.050
Package Outline
(For Reference Only)
SOLDER PAD
PIN 1
All Dimensions in Inches
PIN 34
Figure 12. Heat-Sink Mounting Arrangement (heat sink not included)
THERMALLOY TYPE 2291C TOP
Use Loctite “Output” Thermal
Conductive Adhesive (Loctite item
number 00241) or equivalent to
attach heat sink base to IC.
THERMAL
ADHESIVE
THERMALLOY
TYPE 2291C
BASE
DAC IC
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9
TQ6122
Circuit Description
The TQ6122 DAC is based on a current-steering architecture in which weighted currents are switched by an
array of differential-pair switches into either the VOUT
or VOUT output, depending on the state of the input data
and blanking bits. Essentially, the DAC is comprised of
six circuit blocks: the input buffer, the data multiplexer,
blanking logic, master/slave latch array with segment
encode logic, differential-pair switches, and the current
source array. (See figure on page 1.)
Input Buffers
The input buffers compare the ECL data and control
input signals with the ECLREF level, amplify the difference, and translate this signal to the logic levels used
within the IC. By default, the ECL reference is set by an
internal generator; however, for best performance and
maximum noise margin over temperature, power supply,
and device-to-device variations, the user should provide
an external level. For general-purpose applications, a
simple resistive divider between DGND and VTT will
suffice. For extreme environments or for maximum
performance, the ECLREF level should be slaved to the
centerpoint of the incoming data. Refer to the “Digital
Inputs and Terminations” discussion later in this
document for additional information.
Note that the data inputs are complemented to indicate
that an increasing input value results in the VOUT level
moving more negative.
Data Multiplexer
The DAC makes provision for accepting data from
either of two sources: from a single 8-bit-wide word at
the full conversion rate, or from two 8-bit-wide halfspeed words which are multiplexed together inside the
DAC under the control of the SELA input. In use, the
SELA input is set HIGH to select the A-Word data and
10
LOW to select the B-Word. It is generally best to use
the A-Word input when operating the DAC unmultiplexed,
although the B-Word supports full-rate transfers.
Blanking Logic
A separate BLANK input is included to allow the DAC to
be used in video display applications. When asserted
LOW, the BLANK input has no effect on the operation of
the DAC, and the state of the input data words controls
the positions of the current switches. When BLANK is
asserted HIGH, however, all internal data bits and the
internal blanking bit are synchronously forced HIGH at
the next negative-going clock transition, causing the
VOUT output to go to its most negative level. This level
is the sum of the normal level associated with an input
code of 11111111 plus the increment due to the
blanking current being steered away from the VOUT
output to VOUT. See Figure 4 (B).
In order to provide more latitude in the timing of the
BLANK signal, the BLANK input is sampled only when
the A-Word is selected. When the B-Word is selected,
the state of the BLANK input at the time the SELA
control line goes LOW is held stable until SELA again
goes HIGH. In situations where blanking is not used,
it is important that the BLANK input be tied to a solid
logic LOW to prevent accidental assertion of BLANK =
HIGH. Note also that when the DAC is used in the
unmultiplexed mode, the data should be brought in on
the A-Word inputs, since with SELA = LOW (as would
be the case for B-Word operation), a transient HIGH
level at the BLANK input would never be cleared and
the DAC would lock up.
The BLANK_DISABLE pin is normally tied to the VAA
rail, allowing IBLANK to flow to the differential-pair
switch and then to the selected output. For applications
which do not use blanking, however, the standing
offset in the VOUT output due to the unswitched
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blanking current would be undesirable. For cases such
as these, the blanking current may be completely
turned off by connecting the BLANK_DISABLE pin to
AGND.
with effective binary weightings from 1/16 of full scale
down to 1/128 of full scale. The blanking bit steers a
current which is nominally 10.4% of the full-scale
amplitude.
Master/Slave Latch With Encode Logic
Current-Source Array
A nine-wide master latch registers the data coming from
the multiplexer and blanking logic. The latch outputs are
then split into two groups. The top three bits are translated into a seven-level thermometer code by a binaryto-N-of-seven encoder, while the lower five data bits
and the blanking bit are simply delayed. The seven
encoder outputs and the six delayed data and blanking
bits are re-registered in a slave latch to minimize skew,
which, in turn, reduces the glitch impulse. Latch timing
is set up such that the slave latch is in the “sample” mode
when the input clock is LOW, meaning that the analog
output is updated at the falling edge of the clock.
The current-source array is the heart of the DAC from
an analog standpoint, and is responsible for generating
the segment, bit, and blanking currents. The maximum
full-scale current IFS (less IBLANK) is about 45 mA,
providing a 1.125 volt maximum swing into the 50ohm external load. The blanking current is nominally
10.4% of IFS, corresponding to a 10-unit IRE blanking
interval of 71 mV when the full-scale output is set to
0.679 volt. The IREF current tracks IFS, with a nominal
value of 2.5 mA for IFS = 40 mA (i.e., 6.25% of IFS).
Current Switches
The thermometer code outputs of the slave latch array
drive seven switches, each of which steers a current
equal to 1/8 of the full-scale step amplitude. The five
encoded data bits, on the other hand, switch currents
Figure 13 (A) illustrates the basic circuit of the currentsource array, which consists of a set of current sources
ranging from the 5 mA segment currents to the binaryweighted current sources for the lower-order bits. The
circuit design utilizes source degeneration, averaging,
and linear gradient cancellation techniques to obtain
matching consistent with up to 10-bit linearity.
Figure 13 (A). Current-Source Array Circuit — VSENSE -Based Control Method
VOUT
VOUT
BLANK
BLANK
DIFF-PAIR SWITCH
(TYPICAL, 15 PLACES)
IREF
I BLANK
2.5 mA
(NOM)
I SEG 1
I SEG 7
I B4
I B3
I B0
V BIAS
CASCODES
+
–
VREF
(INTERNAL)
2W
3.56W
4W
4W
2W
W
RS
RS
1.77
RS
2
RS
2
RS
2RS
EXT
REF.
0.8 V NOM,
FOR 1 V F.S. OUT
VSENSE
RLSB
VAA
– 5V
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11
MIXED SIGNAL
PRODUCTS
TQ6122
TQ6122
The absolute value of the current-source array output is
determined using an off-chip (silicon) reference
generator and op amp in a feedback-loop arrangement.
In Figure 13 (A), the drop across the source
degeneration resistors is compared with the level set
by the external reference. Under conditions of 1 V
peak-to-peak full-scale output swing, the voltage
between the VSENSE and VAA pins of the DAC will be in
the range of 0.8 V to 1.1 V, with VREF being in the range
of 0.7 V to 1.4 V (i.e., VREF may lie above or below
VSENSE by several hundred millivolts). Note that, for this
control method, the IREF terminal must be connected to
ground.
An alternative means of controlling the current-source
array output is shown in Figure 13(B), with the
advantage that now the reference current is being
sensed after flowing through a path identical to that of
the bit and segment currents. Thus, any error which
may have occurred due to leakage will be directly
corrected. Here, the VSENSE pin is left disconnected and
the IREF current flows to ground through a stable
resistor. The value of the resistor should be chosen to
drop about 1 volt under the desired operating
conditions, but under no circumstances should the
voltage at the IREF pin be allowed to drop below
–1.5 V, or the linear relationship between IREF and IFS
will be degraded.
The primary limitation on the maximum output current
is the adjustment range of VSENSE: if the value of
{VSENSE – VAA} exceeds about 1.2 V, the bottom currentsource FETs begin to lose “headroom” by running up
against the sources of the cascode transistors, causing
the total current to begin limiting, as well as degrading,
the linearity. If the designer is willing to accept
somewhat degraded linearity and/or slightly higher
power dissipation, VAA may be taken down to –6 volts
or so, allowing VREF to be adjusted to give {VSENSE –
VAA} a maximum value of about 1.5 V. This translates to
an output current of about 50 mA or 1.25 V peak-topeak into the load. Note that under these conditions,
the device will not sustain any damage, but full-spec
operation of the DAC is not guaranteed.
Figure 13 (B). Current-Source Array Circuit — IREF -Based Control Method
VOUT
VOUT
BLANK
BLANK
IREF
2.5 mA
(NOM)
EXT
REF.
I BLANK
V BIAS
(INTERNAL)
< 1.5 V
+
–
VREF
VSENSE
(N/C)
VAA
– 5V
12
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TQ6122
Application Information
Figure 14 illustrates the basic connection of the DAC,
showing details for power supplies, data and clock
inputs, and outputs terminated in 50-ohm transmission
line loads. Some issues relating to circuit board layout
are also addressed.
Figure 14. Basic DAC Setup
u
u
50
.01µF
1000 pF
50
VSS
DGND
NOTE 5
DGND
NOTE 5
B2
B3
B4
1000 pF
u
u
u
V AA
(VAA +1 V)
VAA
620
ZO = 50
(I BLANK = ON)
VOUT
VOUT
Short microstrip or
buried stripline
AGND
DGND
VSS
DGND DGND
Adjust for desired
full-scale output
(IBLANK = OFF)
VOUT
AGND
VSS
VSS
VTT PLANE
+
–
VEE
VAA
AGND
VOUT
u
1K
1K
BLK.DIS.
u
B0
B1
2.5 K
2.5 K
IREF
VAA
ECL
VREF
REF.
VSENSE
u
u
A7
MC33071
1000 pF
DGND
VAA
VOUT (VAA + 2.5 V)
VCC
.01µF
–
.01µF
VSS PLANE
A6
+
1uF
VTT PLANE
1µF
MC1403A
VAA PLANE
MIXED SIGNAL
PRODUCTS
A4
1000 pF
A1
A2
A0
.01µF
u u
u u
A3
A5
u = Microstrip or other
transmission line
Split power supply planes here to minimize noise
coupling into analog circuitry.
Use a common plane for analog and digital grounds.
EXT.
ECL
REF.
VSS PLANE
VSS PLANE
1µF .01µF
1000 pF .01µF
1000 pF
1uF
50
VTT PLANE
L1
-5 V
SUPPLY
L2
VSS PLANE
VAA PLANE
L1 , L2 = Fair-Rite 2743001111
u
u
u
u
u
u
u
.01µF
1000
pF
SELA CLK CLK
B5 B6 B7
NOTE 5 BLANK NOTE 5
A7, B7 = MSB
VSS = -5 +0.5 V
VAA = -5 +0.25 V
VTT = -2 V
Notes: 1. All resistors to VTT are 50-ohm, 1/8 Watt, surface-mount, mounted as close to the IC as possible.
2. All VSS and VTT capacitors are rated ≥15 V. All VAA capacitors are rated ≥ 25 V.
3. Use either surface-mount components or keep minimum-length leads on all resistors and capacitors.
4. For best noise isolation, the analog supply (VAA) and digital supply (VSS) should connect at
only one point, via decoupling networks such as ferrite beads.
5. The input circuitry for B0–B7, BLANK, and SELA are the same as for A0–A7.
6. For questions regarding board layout, please contact the factory.
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13
TQ6122
Power Supplies, Ground and Bypassing
Digital Inputs and Terminations
To minimize noise coupling, the digital and analog
power supplies should be returned to a single-point
ground, and power supply buses to the IC should have
minimum impedance (power planes are best).
The TQ6122 DAC is designed to accept ECL logic levels
at all data and control inputs. All ECL inputs, with the
exception of the clock (see below), are single-ended
and are compared to the ECL threshold reference of
–1.3␣ Volts (nominal) in the input buffers of the DAC.
The supplies themselves should be well bypassed at high
and low frequencies, which requires the use of several
different parallel capacitors as shown. The values are not
particularly critical; however, due to the fact that a
capacitor looks inductive above its self-resonant
frequency, one needs to use several different values in
parallel, ranging from microfarads to nanofarads, in
order to provide adequate wideband bypassing.
For best results, use leadless ceramic chip capacitors
for bypassing, although leaded components will work
satisfactorily if higher noise can be tolerated. A common
ground plane has been found to give the best performance.
For best results and minimum noise, the digital and
analog supplies should be physically separated on the
circuit board. When using a common –5␣ V feed, the
VSS and VAA planes should be isolated by ferrite beads
(Fair-Rite P/N 2743001111 or equivalent) as shown in
Figure 14. Using separate LM337MT regulators downstream of the ferrite beads will provide better isolation.
Figure 15. External ECL Reference Generator
(A)
14
A good way to settle ECLREF is to slave the ECL reference level to the center (switching) point of the input
data signal. This may be accomplished in two ways:
either use the VBB generator output of the device which
is generating the ECL signals supplied to the DAC, or
use an inverter with input and output connected
together to generate a level equal to the switching
threshold. See Figure␣ 15 (B). Note that the ECLREF
generator should be able to source and sink up to
approximately 5␣ mA, since the input resistance is about
50␣ ohms, against an internal –1.3␣ V (nominal) voltage
source. An additional op amp may be used to give
more flexibility or more robust drive. See Figure␣ 15 (C).
(B)
(C)
EXTERNAL ECL
INVERTER
200
50
The ECL reference input equivalent circuit is shown in
Figure 1. Several options are available to the user for
externally setting the ECL reference level. The simplest
option is that of a voltage divider between DGND and
VTT, setting the ECL termination voltage as shown in
Figure␣ 15 (A). The nominal value for ECLREF is –1.3␣ V;
however, due to input offset variations among the input
buffers or variations in VTT, some adjustment above or
below –1.3 V may give the best results.
ECL Reference
input or unused
clock (CLK) input
ECLREF
+
–
50
V TT
V TT
-2 V
-2 V
(OPTIONAL OP AMP)
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DAC
INPUT
TQ6122
In order to realize the full speed potential of the DAC, a
clock with an input swing of at least 1 V peak-to-peak,
nominally centered on –1.3 V, is required. The clock
may be applied in either single-ended or differential
fashion. Because a differential clock provides maximum
speed and best control of the relationship between clock
and output transitions, as well as minimum noise, it is
the preferred solution. For single-ended clock drive, the
customer must drive the unused CLOCK input with an
external ECL reference level, which may be generated
using a resistive divider or, for best results, an external
inverter tied back on itself. See Figure 15.
Input Line Termination
As shown in Figure 14, data, control, and clock inputs
should be terminated in 50 ohms to VTT, consistent
with good ECL practice. For best results, keep
terminations physically small — surface-mount “chip”
resistors work very well — and locate them as close to
the IC as possible. The VTT bus should also be locally
bypassed to digital ground, using chip capacitors
placed close to the terminations. The DAC offers good
performance for –2.5 V < VTT < –2 V, where the use of
VTT < –2 V may allow the designer to eke out the last
bit of performance in a noisy or marginal drive-level
environment.
reference will have to be divided down before being
applied to the control op amp, and some means should
be provided to trim the output to compensate for VOUT
load resistor variations.
The op amp must have input common-mode and
output drive ranges which extend down to within at
least 0.5 Volt of the negative rail for maximum control
range. For best noise immunity, both the reference
generator and the op amp should share a point
connection to the VAA rail, close to the DAC. The
Motorola MC33071 op amp is suitable for this
application. Standard linear design techniques should
be used to minimize thermal drift and offset. Note that
the temperature coefficient of the nichrome resistors
used in the DAC is on the order of +6 ppm/°C. Figure 16
shows a typical reference control loop circuit.
Fig. 16. Typical External Current-Source Control Loop
MC1403A
VAA PLANE
+
1uF
–
VOUT (VAA + 2.5 V)
0.01
MC33071
1000
VCC
IREF
VAA
VREF
2.5 K
2.5 K
VEE
1K
1K
+
–
V AA
(V AA +1 V)
VAA
620
VSENSE
BLK.DIS.
V AA
AGND
Current-Source Control Loop
VOUT
As illustrated previously in Figure 13, and shown in
detail in Figure 16, the bit current sources are
controlled by placing them in a feedback loop which
compares the drop across a current-sensing resistor
with a stable reference. For nominal 1 Volt full-scale
output swing, the VREF-to-VAA voltage will be in the 0.8
to 1 V range, and may be derived from a zener or,
better still, a bandgap reference such as the 2.5 V
Motorola MC1403A. The output of the bandgap
VAA
VOUT
(I BLANK = ON)
(I BLANK = OFF)
V OUT
V OUT
AGND
AGND
DGND
Figure 17 illustrates the relationship between control
input VREF and the full-scale output swing. Note that the
full-scale swing may be reduced below 0.25 V peak-topeak by pulling VREF below VAA. However, this
necessitates a separate negative supply for the control
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15
MIXED SIGNAL
PRODUCTS
Clock Input
TQ6122
op amp and reference generator, which may decrease
the VAA supply rejection. In circuits which use different
negative rails for the DAC VAA supply and the op amp,
VREF should be clamped to no more than two diode
drops below VAA, and a current-limiting resistor should
be included at either the op amp output or between its
negative supply input and supply input. In the event of
turn-on transients and large excursions in the op amp
supply before VAA has settled out, these precautions
will help prevent breakdown of circuitry within the DAC.
Figure 17. Typical VREF-to-VAA Transfer Characteristics
1.25
(Maximum recommended)
1.125
1.00
VOUT
(Volts p-p)
0.50
0.75
0.25
-1.0
0
0.5
V REF to VAA
1.0
The blanking current (IBLANK in Figure 13) is turned off
by connecting the BLANK_DISABLE pin to AGND to
divert the current away from the blank switch and the
output of the DAC, and turned on by connecting
BLANK_DISABLE to VAA.
Output Equivalent Circuit
Figure 5 illustrates the equivalent circuit of the two DAC
outputs. Each of the bit current sources is switched
into either the VOUT or the VOUT output, depending on
the data stored in the slave latches. A pair of internal
50-ohm resistors are connected from VOUT and VOUT to
analog ground (AGND), and provide reverse termination
for the analog output transmission lines. Although in
principle there is no restriction on the load impedance
applied at the outputs, in practice, the best
performance will be obtained when driving a 50-ohm
terminated transmission line. This is very important
from a settling standpoint, since reflections from non50-ohm loads will superimpose with new transitions
and interfere with settling. The general rule for
terminating the outputs is “the cleaner, the better.”
1.25
Output Zero-Scale Adjust
(Volts)
Full-Scale Output Adjust
The procedure for setting the full-scale output range is
quite straightforward, and involves monitoring the
output level(s) using a DVM. With the DAC connected
to its actual VOUT and VOUT load(s), the output is
alternately switched between steady state zero- and
full-scale levels, and the reference is adjusted until the
desired full-scale transition amplitude is obtained. The
clock must be running and the BLANK input set to “0”.
Alternatively, for a DDS application, a spectrum
analyzer or a power meter may be used to monitor the
full-scale output power.
16
Blanking Current Programming
The output baseline, or “zero-scale” level, may be
adjusted by returning the far-end termination resistors
to a well-bypassed supply level other than ground. For
this general situation, reference Figure 5, the instantaneous output voltages VOUT and VOUT are given by:
VOUT = VOS (
VOUT = VOS (
RT1
RL1 + RT1
) – | IOUT | (RL1 || RT1)
RT2
) – | IOUT | (RL2 || RT2)
RL2 + RT2
IOUT =
( Digital Input ) IFS
IOUT = (1 –
255
Digital Input
255
) IFS
IFS = Summation of all individual bit currents
Digital Input = Decimal equivalent of the binary input word
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TQ6122
An alternative method of offsetting the output involves
injecting an offset current at the output. This may be
done using a current source in the form of either a
resistor or a transistor as shown in Figure 18(A). The
resistor has the advantage of minimizing perturbation
of the transmission line impedance, with the
Figure 18(A). Alternate Output Offset Current Generators
VT
VOS
1000 pF
R1
RE
R2
High-F T
Low C JE
Device
0.01 uF
500 – 1 K
1/8 – 1/4W
Carbon Comp.
Short
Lead
Short
Lead
R3
50 Ohm
50 Ohm
disadvantage of requiring a large supply voltage. In
general, a 1/8 to 1/4 W carbon-composition resistor
with a value of 500 to 1000 ohms will give good
performance. Keep the lead lengths short when attaching to the circuit board and bypass the driven terminal
of the resistors with a 1000 pF to 0.01 µF SMT (surfacemount) capacitor network to the ground plane.
A transistor current source, on the other hand, requires
much less power supply overhead, but adds more
capacitance to the transmission line. If a transistor is
used, it should be a high-FT device with low CCB or CDG
(≤ 0.5 pF, if possible) and installed with short leads.
Capacitive coupling provides a means of obtaining an
output centered on 0 volts. However, simply adding a
coupling capacitor at one (or both) of the outputs will
cause the DC output level to exceed the –1.5 V output
compliance limit. The way to circumvent this problem
is to add an offset current between the DAC output and
the coupling capacitor (as discussed above), or to add
a low-loss 50-ohm pad between the DAC and the
capacitor, as shown in Figure 18(B). A “T” or “π”
attenuator topology is acceptable, having 1␣ dB to 3 dB
of attenuation. The characteristic impedance must be
consistent with the overall system impedance, typically
50 ohms. This approach works, although the lower
limit on the output level tends to be very close to the
–1.5 V compliance limit for ≥1 V full-scale output
swings, so some care and verification will be required.
Figure 18(B). AC Coupling of Outputs
0 VOLT
0 VOLT
MIMIMUM-LOSS PAD (1–3 dB)
VMIN
DAC
50
Note: VMIN must not exceed the lower output
compliance limit of –1.5 V for proper
operation. If VMIN < –1.5 V, decrease
the DAC output swing by adjusting the
VREF drive to the control op amp.
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17
MIXED SIGNAL
PRODUCTS
For the case of RL1 = RL2 = RT1 = RT2 = 50 ohms, VOS is
attenuated by 50%. An overriding factor in setting the
output offset is the requirement that VOUT and VOUT
always remain within the device’s output compliance
range of –1.5 V to +1 V. Note also that in the case of
the video application of the DAC, the value of the
blanking current IBLANK and the state of the BLANK
input must be included in the expressions for VOUT and
VOUT.
TQ6122
Typical AC Performance
Figure 19 (A). Unmuxed Ramp at 1000 Ms/s with
Blanking (Guaranteed, 0 to +85 °C)
Figures 19 through 23 show typical AC performance
of the TQ6122. Figures␣ 19A and 19B illustrate the
response of the DAC to an unmultiplexed counter
input at 1 Gs/s and 1.5␣ Gs/s, respectively.
Blanking is enabled in both cases.
The small glitches appearing at 1/8 of full-scale
intervals are shown in more detail in Figure 22.
Figure 19(B). Unmuxed Ramp at 1500 Ms/s with
Blanking (Typical, +25 °C)
18
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TQ6122
Figure 20(A). Muxed Ramp at 1000 Ms/s with Blanking
Multiplexed behavior is shown in Figure 20A and 20B,
with a counter input muxed against fixed levels at
1000 Ms/s and at 1350 Ms/s, respectively.
In Figure 20A, the ramp is muxed against a steady
state mid-scale value, while in Figure 20B, the steady
state input is 11111111. The apparent droop in the top
level in Figure 20B is an artifact of the sampler.
Figures 19A, 19B, and 20A show the effects of blanking,
while in Figure 20B, the BLANK input is held LOW,
demonstrating the repetitive nature of the waveform.
MIXED SIGNAL
PRODUCTS
Note: In Figure 20(A), A0–A7 are switched, B0–B6 are LOW,
B7is HIGH and BLANK is switched. In Figure 20(B),
A0–A7 are switched, B0–B7 are HIGH, and BLANK is LOW.
Figure 20(B). Muxed Ramp at 1350 Ms/s with
Blanking Disabled
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19
TQ6122
Figure 21. Typical Full-Scale Transitions
at VOUT and VOUT (fCLK = 1000 MHz)
Figure 21 illustrates the symmetry of complementary
full-scale transitions at VOUT and VOUT, while Figure 22
depicts a typical worst-case glitch of 6 pV/sec.
Figure 22. Typical Worst-Case Glitch Impulse
(fCLK = 1000 MHz)
20
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TQ6122
Figure 23(A). Synthesized Sine Wave Output
Figure 23(A) shows a 1 Gs/s, 58.6 MHz sine wave, and
Figure 23B shows its corresponding spectrum. The
spurious-free dynamic range is 46␣ dBc, a typical value
for the device.
MIXED SIGNAL
PRODUCTS
In Figure 23(B), the DAC output is attenuated by 6 dB
going into a spectrum analyzer.
Figure 23(B). Spectrum of a 58.5 MHz Sine Wave
at 1 Gs/s
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21
TQ6122
Figure 24. Complex Modulated Sine Wave Pattern
at 1000 Mb/s
Figure 24 shows a modulated sine wave as an example
of a more complex waveform.
VSS
VSS
A4
A5
A3
DGND
A2
DGND
DGND
A0 (LSB)
A1
ECL REF
VAA
IREF
VAA
Figure 25. Chip Dimensions, Topography, and Padout
VAA
VSS
VAA
VSS
VREF
A6
VSENSE
A7 (MSB)
BLANK DISABLE
DGND
AGND
DGND
AGND
B0 (LSB)
AGND
B1
VOUT
DGND
VOUT
DGND
AGND
B2
VOUT
B3
VOUT
B4
Notes:
AGND
AGND
1. Dimensional limits unless otherwise
specified: +2 mils (+51 µM).
2. Pins labeled N/C are not
connected internally.
VSS
VSS
VSS
VSS
B5
B6
BLANK
B7 (MSB)
DGND
DGND
SELA
DGND
N/C
CLOCK
CLOCK
VSS
VSS
VSS
DIE SIZE: 129 Mils x 111 Mils (3110 µM x 2660 µM)
22
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TQ6122
Figure 26. Package Labelling (44-pin packaged version)
See Figures 10, 11 and 12 for package dimensions and heat-sink mounting information.
BEVELED
CORNER
1 TQS USA
TQ6122-M
Component
Material
YYWW XXXX
Lead
Lead Plating
Kovar
Lead/tin alloy
YYWW – Date Code
XXXX - Lot Number
TQ6122-M
TQ6122-D
ETF6122
MIXED SIGNAL
PRODUCTS
Ordering Information
8-bit, 1 Gs/s DAC in 44-pin package
8-bit, 1 Gs/s DAC, die only
Engineering Test Fixture with 6122 device
Additional Information
For latest specifications, additional product information,
worldwide sales and distribution locations, and information about TriQuint:
Web: www.triquint.com
Email: [email protected]
Tel: (503) 615-9000
Fax: (503) 615-8900
For technical questions and additional information on specific applications:
Email: [email protected]
The information provided herein is believed to be reliable; TriQuint assumes no liability for inaccuracies or
omissions. TriQuint assumes no responsibility for the use of this information, and all such information
shall be entirely at the user's own risk. Prices and specifications are subject to change without notice.
No patent rights or licenses to any of the circuits described herein are implied or granted to any third party.
TriQuint does not authorize or warrant any TriQuint product for use in life-support devices and/or systems.
Copyright © 1997 TriQuint Semiconductor, Inc. All rights reserved.
Revision 1.0.A
October 1997
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23