RFF70N06
Data Sheet
March 1999
25A, 60V, 0.025 Ohm, N-Channel Power
MOSFET
File Number
4073.2
Features
• 25A†, 60V
The RFF70N06 N-Channel power MOSFET is manufactured
using the MegaFET process. This process, which uses
feature sizes approaching those of LSI circuits gives
optimum utilization of silicon, resulting in outstanding
performance. It was designed for use in applications such as
switching regulators, switching converters, motor drivers,
and relay drivers. These transistors can be operated directly
from integrated circuits.
Reliability screening is available as either commercial or
TX/TXV equivalent of MIL-S-19500. Contact Intersil
Corporation High-Reliability Marketing group for any desired
deviations from the data sheet.
• rDS(ON) = 0.025Ω
• Temperature Compensating PSPICE™ Model
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• 150oC Operating Temperature
• Reliability Screened
† Current is limited by the package capability.
Symbol
D
Formerly developmental type TA49007.
Ordering Information
PART NUMBER
RFF70N06
G
PACKAGE
TO-254AA
BRAND
S
RFF70N06
NOTE: When ordering, use the entire part number.
Commercial Version: RFG70N06.
Packaging
JEDEC TO-254AA
PACKAGE TAB
(ISOLATED)
GATE
SOURCE
DRAIN
CAUTION: Berylia Warning per MIL-S-19500.
Refer to package specifications.
4-442
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
PSPICE™ is a trademark of MicroSim Corporation.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
RFF70N06
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Continuous Drain Current (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current (Note 4) (Figure 5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
Single Pulse Avalanche Rating (Figure 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .EAS
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .PD
Linear Derating Factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
RFF70N06
60
60
±20
25 (Note 2)
Refer to Peak Current Curve
Refer to UIS Curve
100
0.80
-55 to 150
UNITS
V
V
V
A
260
oC
W
W/oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to 125oC.
2. Current is limited by the package capability.
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Drain to Source Breakdown Voltage
BVDSS
ID = 250µA, VGS = 0V
60
-
-
V
Gate Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA
2.0
3.0
4.5
V
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
Drain to Source On Resistance (Note 3)
Turn-On Time
VDS = Rated BVDSS, VGS = 0V
-
-
25
µA
VDS = 0.8 x Rated BVDSS, VGS = 0V, TC = 125oC
-
-
250
µA
VGS = ±20V, TC = 125oC
-
-
±100
µΑ
ID = 25A, VGS = 10V
-
-
0.025
Ω
VDD = 30V, ID ≈ 25A, RL = 1.2Ω,
VGS = 10V, RGS = 2.35Ω
(Figures 13, 16, 17)
-
-
240
ns
-
25
70
ns
tr
-
70
170
ns
td(OFF)
-
60
150
ns
tf
-
25
65
ns
tOFF
-
-
215
ns
-
-
260
nC
-
-
145
nC
IDSS
IGSS
rDS(ON)
tON
Turn-On Delay Time
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
Total Gate Charge
Qg(TOT)
VGS = 0 to 20V
Gate Charge at 10V
Qg(10)
VGS = 0 to 10V
Threshold Gate Charge
Qg(TH)
VGS = 0 to 2V
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDD = 30V, ID = 25A,
RL = 1.2Ω
IG(REF) = 1.0mA
(Figures 18, 19)
VDS = 25V, VGS = 0V, f = 1MHz
(Figure 12)
-
-
7
nC
-
3100
-
pF
-
900
-
pF
-
300
-
pF
Thermal Resistance Junction to Case
RθJC
-
-
1.25
oC/W
Thermal Resistance Junction to Ambient
RθJA
-
-
48
oC/W
MIN
TYP
MAX
UNITS
ISD = 25A
-
1.1
1.5
V
ISD = 25A, dISD/dt = 100A/µs
-
190
300
ns
Source to Drain Diode Specifications
PARAMETER
SYMBOL
Source to Drain Diode Voltage
VSD
Diode Reverse Recovery Time
trr
TEST CONDITIONS
NOTES:
3. Pulse test: pulse width ≤ 300ms, duty cycle ≤ 2%.
4. Repetitive rating: pulse width is limited by maximum junction temperature. See Transient Thermal Impedance curve Figure 3).
4-443
RFF70N06
Unless Otherwise Specified
30
1.0
25
ID , DRAIN CURRENT (A)
1.2
0.8
0.6
0.4
0.2
20
15
10
5
0
POWER DISSIPATION MULTIPLIER
Typical Performance Curves
0
0
25
50
75
100
TC , CASE TEMPERATURE (oC)
125
25
150
50
75
125
100
150
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
THERMAL IMPEDANCE
ZθJC, NORMALIZED
1
0.5
0.2
0.1
PDM
0.1
t1
t2
0.05
0.02
0.01
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-1
10-2
101
100
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
103
500
100
100µs
1ms
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10ms
VDSS MAX = 60V
100ms
DC
1
1
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA
4-444
100
IDM , PEAK CURRENT (A)
ID , DRAIN CURRENT (A)
TC = 25oC
FOR TEMPERATURES ABOVE 25oC
DERATE PEAK CURRENT
CAPABILITY AS FOLLOWS:
150 – T C
I = I 25 ----------------------
125
102
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
VGS = 10V
TC = 25oC
101
10-5
10-4
10-3
10-2
10-1
t, PULSE WIDTH (s)
100
FIGURE 5. PEAK CURRENT CAPABILITY
101
RFF70N06
Typical Performance Curves
Unless Otherwise Specified
(Continued)
150
100
75
STARTING TJ = 150oC
STARTING TJ = 25oC
10
If R = 0
tAV = (L) (IAS) / (1.3 RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R) ln [(IAS*R) / (1.3 RATED BVDSS - VDD) + 1]
1
0.01
0.1
VGS = 10V
VGS = 20V
125
ID , DRAIN CURRENT (A)
IAS , AVALANCHE CURRENT (A)
300
1
10
100
tAV, TIME IN AVALANCHE (ms)
250µs PULSE TEST
TC = 25oC
100
VGS = 6V
75
50
1000
0
0
2
4
6
8
VDS , DRAIN TO SOURCE VOLTAGE (V)
125
2.5
-55oC
25oC
100
150oC
75
50
25
2
4
6
PULSE DURATION = 250µs
VGS = 10V,
ID = 25A
2.0
1.5
0
0
1.0
0.5
0
-80
8
FIGURE 8. TRANSFER CHARACTERISTICS
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
1.0
0.5
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
4-445
40
80
120
160
2.0
VGS = VDS, ID = 250µA
-40
0
FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
1.5
0
-80
-40
TJ , JUNCTION TEMPERATURE (oC)
VGS, GATE TO SOURCE VOLTAGE (V)
2.0
10
FIGURE 7. SATURATION CHARACTERISTICS
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
IDS(ON), DRAIN TO SOURCE CURRENT (A)
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
VDD = 15V
PULSE DURATION = 250µs
DUTY CYCLE = 0.5% MAX
VGS = 5V
VGS = 4.5V
25
NOTE: Refer to Intersil Application Notes AN9321 and AN9322.
150
VGS = 7V
ID = 250µA
1.5
1.0
0.5
0
-80
-40
0
40
80
120
160
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
RFF70N06
Unless Otherwise Specified
60
VDS , DRAIN TO SOURCE VOLTAGE (V)
5000
C, CAPACITANCE (pF)
(Continued)
VGS = 0V, f = 0.1MHz
CISS = CGS + CGD
CRSS = CGD
COSS ≈ CDS + CGS
4000
3000
2000
1000
10.0
7.5
RL = 1.2Ω
IG(REF) = 1.0mA
VGS = 10V
0.75 BVDSS
0.75 BVDSS
30
15
0
0
0
5
10
15
20
VDD = BVDSS
VDD = BVDSS
45
25
20
VDS , DRAIN TO SOURCE VOLTAGE (V)
0.50 BVDSS
0.50 BVDSS
0.25 BVDSS
0.25 BVDSS
IG(REF)
t, TIME (µs)
IG(ACT)
80
5.0
2.5
VGS , GATE TO SOURCE VOLTAGE (V)
Typical Performance Curves
0
IG(REF)
IG(ACT)
NOTE: Refer to Intersil Application Notes AN7254 and AN7260.
FIGURE 12. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 13. NORMALIZED SWITCHING WAVEFORMS FOR
CONSTANT GATE CURRENT
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 14. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 15. UNCLAMPED ENERGY WAVEFORMS
tON
tOFF
td(ON)
VDS
td(OFF)
tf
tr
VDS
90%
90%
RL
VGS
+
DUT
RGS
VGS
-
VDD
90%
VGS
0
FIGURE 16. SWITCHING TIME TEST CIRCUIT
4-446
10%
10%
0
10%
50%
50%
PULSE WIDTH
FIGURE 17. RESISTIVE SWITCHING WAVEFORMS
RFF70N06
Test Circuits and Waveforms
(Continued)
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 20V
VGS
Qg(10)
+
VDD
DUT
Ig(REF)
VGS = 10V
VGS
-
VGS = 2V
0
Qg(TH)
Ig(REF)
0
FIGURE 18. GATE CHARGE TEST CIRCUIT
Data Packages - Intersil Power Transistors
TX and TXV Equivalents
1. TX/TXV Equivalent - Standard Data Package
A. Certificate of Compliance
B. Assembly Flow Chart
C. Preconditioning - Attributes Data Sheet
D. Group A
- Attributes Data Sheet
E. Group B
F. Group C
- Attributes Data Sheet
- Attributes Data Sheet
2. TX/TXV Equivalent - Optional Data Package
A. Certificate of Compliance
B. Assembly Flow Chart
C. Preconditioning - Attributes Data Sheet
- Precondition Lot Traveler
- Pre and Post Burn-In Read and Record Data
D. Group A
- Attributes Data Sheet
- Group A Lot Traveler
E. Group B
- Attributes Data Sheet
- Group B Lot Traveler
- Pre and Post Read and Record Data for Intermittent
Operating Life (Subgroup B3)
- Bond Strength Data (Subgroup B3)
- Pre and Post High Temperature Operating Life
Read and Record Data (Subgroup B6)
F. Group C
- Attributes Data Sheet
- Group C Lot Traveler
- Pre and Post Read and Record Data for Intermittent
Operating Life (Subgroup C6)
- Bond Strength Data (Subgroup C6)
4-447
FIGURE 19. GATE CHARGE WAVEFORMS
RFF70N06
PSPICE Electrical Model
SUBCKT RFF70N06 2 1 3 ;
rev 5/29/95
CA 12 8 5.20e-9
CB 15 14 5.20e-9
CIN 6 8 2.80e-9
LDRAIN
DPLCAP
5
DRAIN
2
10
DBODY 7 5 DBDMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
RLDRAIN
RSCL1
51
+
5
ESCL
51
RSCL2
EBREAK 11 7 17 18 68.7
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRESH 6 21 19 8 1
EZTEMPCO 20 6 18 22 1
DBREAK
50
RDRAIN
6
8
ESG
16
EVTHRESH
+
19
8
+
IT 8 17 1
LGATE
GATE
LDRAIN 2 5 1e-9
LGATE 1 9 6.04e-9
LSOURCE 3 7 2.24e-9
EZTEMPCO
9
1
20 +
18
22
RGATE
21
+
17
EBREAK
18
DBODY
MOS2
6
MOS1
RLGATE
RIN
CIN
LSOURCE
MOS1 16 6 8 8 MSTRONG M = 0.99
MOS2 16 21 8 8 MWEAK M = 0.01
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 8.03e-3
RGATE 9 20 1
RIN 6 8 1e9
RLDRAIN 2 5 10
RLGATE 1 9 60.4
RLSOURCE 3 7 22.4
RSCL1 5 51 RSCLMOD 1e-6
RSCL2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 7.20e-3
RTHRESH 22 8 RTHRESMOD 1
RZTEMPCO 18 19 RZTEMPCOMOD 1
11
8
RSOURCE
7
3
SOURCE
RLSOURCE
S2A
S1A
12
13
8
S1B
RBREAK
15
14
13
S2B
13
RZTEMPCO
CB
CA
+
EGS
14
+
6
8
18
17
EDS
IT
VBAT
+
5
8
22
RTHRESH
S1A
S1B
S2A
S2B
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
VBAT 22 19 DC 1
ESCL 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*250),3))}
.MODEL DBDMOD D (IS = 1e-12 RS = 11.01e-3 TRS1 = 1.75e-3 TRS2 = -0.06e-6 CJO = 2.70e-9 TT = 7.82e-8 M = 0.45)
.MODEL DBREAKMOD D (RS = 88e-3 TRS1 = 1.50e-3 TRS2 = 0)
.MODEL DPLCAPMOD D (CJO = 2.60e-9 IS = 1e-30 N = 10 M=0.7)
.MODEL MSTRONG NMOS (VTO = 3.85 KP = 47.2 IS = 1e-30 N = 10 TOX = 1L = 1u W = 1u)
.MODEL MWEAK NMOS (VTO = 3.09 KP = 47.2 IS = 1e-30 N = 10 TOX = 1L = 1u W = 1u)
.MODEL RBREAKMOD RES (TC1 = 1e-3 TC2 = 0)
.MODEL RDRAINMOD RES (TC1 = 7e-3 TC2 = 1.90e-5)
.MODEL RDSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RSCLMOD RES (TC1 = 0 TC2 = 0)
.MODEL RTHRESHMOD RES (TC1 = -3.10e-3 TC2 = -1e-5)
.MODEL RZTEMPCOMOD RES (TC1 = -2.25e-3 TC2 = -5.75e-7)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -6.0 VOFF= -4.0)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.0 VOFF= -6.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF= 2.0)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 2.0 VOFF= -2.0)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991.
4-448
19
RFF70N06
Screening Information
Screening is performed in accordance with the latest revision in effect of MIL-S-19500, (Screening Information Table)
.
Delta Tests and Limits (JANTX/JANTXV Equivalent)
PARAMETER
SYMBOL
Gate to Source Leakage Current
Gate Threshold Voltage
MAX
UNITS
IGSS
VGS = ±20V, TC = 25oC
±20 (Note 5)
nA
IDSS
VDS = 80% Rated Value, TC = 25oC
±25 (Note 5)
µA
rDS(ON)
TC = 125oC at Rated ID
±20% (Note 6)
Ω
VGS(TH)
ID = 1.0mA, TC = 25oC
±20% (Note 6)
V
Zero Gate Voltage Drain Current
On Resistance
TEST CONDITIONS
NOTES:
5. Or 100% of Initial Reading (whichever is greater).
6. Of Initial Reading.
Screening Information
TEST
JANTX/JANTXV EQUIVALENT
Gate Stress
VGS = 30V, t = 250µs
Pind
Optional
PDA
10%
Pre Burn-In Test (Note 7)
MIL-S-19500 Group A, Subgroup 2 (All Static Tests at 25oC)
Steady State Gate Bias (Gate Stress)
MIL-STD-750, Method 1042, Condition B
VGS = 80% of Rated Value,
TA = 150oC, Time = 48 hours
Interim Electrical Tests (Note 7)
All Delta Parameters Listed in the Delta Tests and Limits Table
Steady State Reverse Bias (Drain Stress)
MIL-STD-750, Method 1042, Condition A
VDS = 80% of Rated Value,
TA = 150oC, Time = 168 hours
Final Electrical Tests (Note 7)
MIL-S-19500, Group A, Subgroup 2
NOTE:
7. Test limits are identical pre and post burn-in.
Additional Screening Tests
PARAMETER
SYMBOL
SOA
Safe Operating Area
IAS
Unclamped Inductive Switching
TEST CONDITIONS
MAX
UNITS
VDS = 48V, t = 10ms
4.8
A
VGS(PEAK) = 15V, L = 0.1mH
75
A
Thermal Response
∆VSD
tH = 100ms; VH = 25V, IH = 4A
220
mV
Thermal Impedance
∆VSD
tH = 500ms; VH = 25V, IH = 4A
330
mV
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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4-449
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