BUF602 SBOS339 – OCTOBER 2005 High-Speed, Closed-Loop Buffer FEATURES • • • • • • • • DESCRIPTION Wide Bandwidth: 1000MHz High Slew Rate: 8000V/µs Flexible Supply Range: ±1.4V to ±6.3V Dual Supplies +2.8V to +12.6V Single Supply Output Current: 60mA (continuous) Peak Output Current: 350mA Low Quiescent Current: 5.8mA Standard Buffer Pinout Optional Mid-Supply Reference Buffer The BUF602 is a closed-loop buffer recommended for a wide range of applications. Its wide bandwidth (1000MHz) and high slew rate (8000V/µs) make it ideal for buffering very high-frequency signals. For AC-coupled applications, an optional mid-point reference (VREF) is provided, reducing the number of external components required and the necessary supply current to provide that reference. The BUF602 is available in a standard SO-8 surface-mount package and in an SOT23-5 where a smaller footprint is needed. APPLICATIONS • • • • • • Low Impedance Reference Buffers Clock Distribution Circuits Video/Broadcast Equipment Communications Equipment High-Speed Data Acquisition Test Equipment and Instrumentation +VCC ≈ 2kΩ Input Z VIN ZO < 2Ω to 20MHz VOUT x1 2kΩ 200Ω x1 VCC/2 1µF Self-Referenced, AC-Coupled, Single-Supply Buffer Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005, Texas Instruments Incorporated BUF602 www.ti.com SBOS339 – OCTOBER 2005 This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) (1) SPECIFIED TEMPERATURE RANGE PACKAGE MARKING PRODUCT PACKAGE PACKAGE DESIGNATOR BUF602 SO-8 D –45°C to +85°C BUF602 BUF602 SOT23-5 DBV –45°C to +85°C AWO ORDERING NUMBER TRANSPORT MEDIA, QUANTITY BUF602ID Rails, 75 BUF602IDR Tape and Reel, 2500 BUF602IDBVT Tape and Reel, 250 BUF602IDBVR Tape and Reel, 3000 For the most current package and ordering information, see the Package Option Addendum at the end of this document or see the TI web site at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) ±6.5VDC Power Supply Internal Power Dissipation See Thermal Information ±VS Input Common-Mode Voltage Range Storage Temperature Range: D, DBV –40°C to +125°C Lead Temperature (soldering, 10s) +300°C Junction Temperature (TJ) +150°C ESD Rating: Human Body Model (HBM) 2000V Charge Device Model (CDM) 1000V Machine Model (MM) (1) 200V Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not supported. Top View Out 1 5 +VCC 4 In 50kΩ 2 NC 3 In 4 3 7 NC 6 VREF 5 −VCC 200Ω x1 200Ω x1 x1 50kΩ AWO 1 SO−8 NC = No Connection SOT23−5 4 NC VREF Out 3 8 50kΩ 2 1 2 5 +VCC x1 50kΩ −VCC Pin Orientation/Package Marking 2 BUF602 www.ti.com SBOS339 – OCTOBER 2005 ELECTRICAL CHARACTERISTICS: VS = ±5V Boldface limits are tested at +25°C. At RL = 100Ω, unless otherwise noted. BUF602ID, IDBV TYP +25°C +25°C (2) 0°C to 70°C (3) –40°C to +85°C (3) UNITS MIN/ MAX VO = 500mVPP 1000 560 550 540 MHz min B VO = 1VPP 920 MHz typ C PARAMETER CONDITIONS AC PERFORMANCE (See figure 30) Bandwidth Full Power Bandwidth MIN/MAX OVER TEMPERATURE TEST LEVEL (1) VO = 5VPP 880 MHz typ C Bandwidth for 0.1dB Flatness VO = 500mVPP 240 MHz typ C Slew Rate VO = 5V Step 8000 7000 6000 5000 V/µs min B VO = 0.2V Step 350 625 640 650 ps max B VO = 1V Step 6 ns typ C Rise Time and Fall Time Settling Time to 0.05% Harmonic Distortion 2nd-Harmonic VO = 2VPP, 5MHz RL = 100Ω –57 –44 –44 –42 dBc max B RL = 500Ω –76 –63 –62 –60 dBc max B RL = 100Ω –68 –63 –63 –63 dBc max B RL = 500Ω –98 –85 –84 –82 dBc max B Input Voltage Noise f > 100kHz 4.8 5.1 5.6 6.0 nV/√Hz max B Input Current Noise f > 100kHz 2.1 2.6 2.7 2.8 pA/√Hz max B Differential Gain NTSC, RL = 150Ω to 0V 0.15 % typ C Differential Phase NTSC, RL = 150Ω to 0V 0.04 ° typ C Maximum Gain RL = 500Ω 0.99 1 1 1 V/V max A Minimum Gain RL = 500Ω 0.99 0.98 0.98 0.98 V/V min A ±16 ±30 ±36 ±38 mV max A ±125 ±125 µV/°C max B ±8 ±8.5 µA max A ±20 ±20 nA/°C max B MΩ || pF typ C 3rd-Harmonic BUFFER DC PERFORMANCE (4) Input Offset Voltage Average Input Offset Voltage Drift ±3 Input Bias Current ±7 Average Input Bias Current Drift BUFFER INPUT Input Impedance 1.0 || 2.1 BUFFER OUTPUT RL = 100Ω ±3.8 ±3.7 ±3.7 ±3.7 V min B RL = 500Ω ±4.0 ±3.8 ±3.8 ±3.8 V min A Output Current (Continuous) VO = 0V ±60 ±50 ±49 ±48 mA min A Peak Output Current VO = 0V ±350 mA typ C f ≤ 10MHz 1.4 Ω typ C Output Voltage Swing Closed-Loop Output Impedance POWER SUPPLY ±5 Specified Operating Voltage V typ C Maximum Operating Voltage ±6.3 ±6.3 ±6.3 V max A Minimum Operating Voltage ±1.4 ±1.4 ±1.4 V min B Maximum Quiescent Current VS = ±5V 5.8 6.3 6.9 7.2 mA max A Minimum Quiescent Current VS = ±5V 5.8 5.3 4.9 4.3 mA min A 54 48 46 45 dB min A Power-Supply Rejection Ratio (+PSRR) (1) (2) (3) (4) Test levels: (A) 100% tested at 25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. ©) Typical value only for information. Junction temperature = ambient for 25°C specifications. Junction temperature = ambient at low temperature limit; junction temperature = ambient + 8°C at high temperature limit for over temperature specifications. Current is considered positive out of node. 3 BUF602 www.ti.com SBOS339 – OCTOBER 2005 ELECTRICAL CHARACTERISTICS: VS = ±5V (continued) Boldface limits are tested at +25°C. At RL = 100Ω, unless otherwise noted. BUF602ID, IDBV TYP PARAMETER CONDITIONS MIN/MAX OVER TEMPERATURE UNITS MIN/ MAX TEST LEVEL (1) –40 to +85 °C typ C +25°C +25°C (2) 0°C to 70°C (3) –40°C to +85°C (3) THERMAL CHARACTERISTICS Specification: ID Thermal Resistance θJA D SO-8 Junction-to-Ambient 125 °C/W typ C DBV SOT23-5 Junction-to-Ambient 150 °C/W typ C 4 BUF602 www.ti.com SBOS339 – OCTOBER 2005 ELECTRICAL CHARACTERISTICS: VS = +5V Boldface limits are tested at +25°C. At RL = 100Ω to VS/2, unless otherwise noted. BUF602ID, IDBV TYP +25°C +25°C (2) 0°C to 70°C (3) –40°C to +85°C (3) UNITS MIN/ MAX VO = 500mVPP 780 400 400 390 MHz min B VO = 1VPP 700 MHz typ C PARAMETER CONDITIONS AC PERFORMANCE (See figure 31) Bandwidth Full-Power Bandwidth MIN/MAX OVER TEMPERATURE TEST LEVEL (1) VO = 3VPP 420 MHz typ C Bandwidth for 0.1dB Flatness VO = 500mVPP 130 MHz typ C Slew Rate VO = 3V Step 2500 1800 1600 1400 V/µs min B VO = 0.2V Step 450 875 875 900 ps max B VO = 1V Step 6 ns typ C Rise Time and Fall Time Settling Time to 0.05% Harmonic Distortion 2nd-Harmonic VO = 2VPP, 5MHz RL = 100Ω –50 –45 –44 –43 dBc max B RL = 500Ω –73 –62 –61 –60 dBc max B RL = 100Ω –70 –64 –64 –63 dBc max B RL = 500Ω –73 –72 –72 –71 dBc max B Input Voltage Noise f > 100kHz 4.9 5.2 5.7 6.1 nV/√Hz max B Input Current Noise f > 100kHz 2.2 2.7 2.8 2.9 pA/√Hz max B Differential Gain NTSC, RL = 100Ω to VS/2 0.16 % typ C Differential Phase NTSC, RL = 100Ω to VS/2 0.05 ° typ C Maximum Gain RL = 500Ω 0.99 1 1 1 V/V max A Minimum Gain RL = 500Ω 0.99 0.98 0.98 0.98 V/V min A ±16 ±30 ±36 ±38 mV max A ±125 ±125 µV/°C max B ±8 ±8.5 µA max A ±20 ±20 nA/°C max B MΩ || pF typ C 3rd-Harmonic BUFFER DC PERFORMANCE (4) Input Offset Voltage Average Input Offset Voltage Drift ±3 Input Bias Current ±7 Average Input Bias Current Drift BUFFER INPUT Input Impedance 1.0 || 2.1 BUFFER OUTPUT Most Positive Output Voltage RL = 100Ω +3.9 +3.7 +3.7 +3.7 V min B RL = 500Ω +4.1 +3.8 +3.8 +3.8 V min A RL = 100Ω +1.1 +1.3 +1.3 +1.3 V max B RL = 500Ω +0.9 +1.2 +1.2 +1.2 V max A Output Current (Continuous) VO = 0V ±60 ±50 ±49 ±48 mA min A Peak Output Current VO = 0V ±160 mA typ C f ≤ 10MHz 1.4 Ω typ C A Least Positive Output Voltage Closed-Loop Output Impedance MID-POINT REFERENCE OUTPUT Maximum Mid Supply Reference Voltage 2.5 2.6 2.6 2.6 V max Minimum Mid Supply Reference Voltage 2.5 2.4 2.4 2.4 V min A Mid-Supply Output Current, Sourcing 800 µA typ C Mid-Supply Output Current, Sinking 70 µA typ C Mid-Supply Output Impedance 200 Ω typ C (1) (2) (3) (4) Test levels: (A) 100% tested at 25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. ©) Typical value only for information. Junction temperature = ambient for 25°C specifications. Junction temperature = ambient at low temperature limit; junction temperature = ambient + 4°C at high temperature limit for over temperature specifications. Current is considered positive out of node. 5 BUF602 www.ti.com SBOS339 – OCTOBER 2005 ELECTRICAL CHARACTERISTICS: VS = +5V (continued) Boldface limits are tested at +25°C. At RL = 100Ω to VS/2, unless otherwise noted. BUF602ID, IDBV TYP MIN/MAX OVER TEMPERATURE +25°C (2) 0°C to 70°C (3) –40°C to +85°C (3) Maximum Operating Voltage +12.6 +12.6 +12.6 Minimum Operating Voltage +2.8 +2.8 PARAMETER CONDITIONS +25°C MIN/ MAX TEST LEVEL (1) V typ C V max A +2.8 V min B UNITS POWER SUPPLY Specified Operating Voltage +5 Maximum Quiescent Current VS = +5V 5.3 5.8 6.3 6.5 mA max A Minimum Quiescent Current VS = +5V 5.3 4.8 4.5 3.9 mA min A 52 46 44 43 dB min A –40 to +85 °C typ C Power-Supply Rejection Ratio (+PSRR) THERMAL CHARACTERISTICS Specification: ID Thermal Resistance θJA D SO-8 Junction-to-Ambient 125 °C/W typ C DBV SOT23-5 Junction-to-Ambient 150 °C/W typ C 6 BUF602 www.ti.com SBOS339 – OCTOBER 2005 ELECTRICAL CHARACTERISTICS: VS = +3.3V Boldface limits are tested at +25°C. At RL = 100Ω, unless otherwise noted. BUF602ID, IDBV TYP MIN/MAX OVER TEMPERATURE CONDITIONS +25°C +25°C (2) 0°C to 70°C (3) –40°C to +85°C (3) UNITS MIN/ MAX VO = 500mVPP 600 320 320 310 MHz min B VO = 1VPP 520 MHz typ C Bandwidth for 0.1dB Flatness VO = 500mVPP 110 MHz typ C Slew Rate VO = 1.4V Step 800 650 600 600 V/µs min B Rise Time and Fall Time VO = 0.2V Step 580 1100 1100 1150 ps max B VO = 1V Step 6.5 ns typ C PARAMETER TEST LEVEL (1) AC PERFORMANCE Bandwidth Full Power Bandwidth Settling Time to 0.05% Harmonic Distortion 2nd-Harmonic VO = 1VPP, 5MHz RL = 100Ω –59 –49 –49 –48 dBc max B RL = 500Ω –76 –61 –57 –53 dBc max B RL = 100Ω –70 –51 –48 –44 dBc max B RL = 500Ω –63 –51 –48 –44 dBc max B Input Voltage Noise f > 100kHz 4.9 5.2 5.7 6.1 nV/√Hz max B Input Current Noise f > 100kHz 2.2 2.7 2.8 2.9 pA/√Hz max B Maximum Gain RL = 500Ω 0.99 1 1 1 V/V max A Minimum Gain RL = 500Ω 0.99 0.98 0.98 0.98 V/V min A ±16 ±30 ±36 ±38 mV max A ±125 ±125 µV/°C max B ±8 ±8.5 µA max A ±20 ±20 nA/°C max B MΩ || pF typ C 3rd-Harmonic BUFFER DC PERFORMANCE (4) Input Offset Voltage Average Input Offset Voltage Drift ±3 Input Bias Current ±7 Average Input Bias Current Drift BUFFER INPUT Input Impedance 1.0 || 2.1 BUFFER OUTPUT Most Positive Output Voltage Least Positive Output Voltage Output Current (Continuous) RL = 100Ω +2.1 +2.0 +2.0 +2.0 V min B RL = 500Ω +2.3 +2.2 +2.2 +2.2 V min A RL = 100Ω +1.2 +1.3 +1.3 +1.3 V max B RL = 500Ω +1.0 +1.1 +1.1 +1.1 V max A VO = 0 ±60 ±50 ±49 ±48 mA min A ±100 mA typ C 1.4 Ω typ C A Peak Output Current Closed-Loop Output Impedance f ≤ 10MHz MID-POINT REFERENCE OUTPUT Maximum Mid Supply Reference Voltage 1.65 1.72 1.72 1.72 V max Minimum Mid Supply Reference Voltage 1.65 1.58 1.58 1.58 V min A Mid Supply Output Current, Sourcing 500 µA typ C Mid Supply Output Current, Sinking 60 µA typ C Mid Supply Output Impedance 200 Ω typ C POWER SUPPLY Specified Operating Voltage V typ C Maximum Operating Voltage +3.3 +12.6 +12.6 +12.6 V max A Minimum Operating Voltage +2.8 +2.8 +2.8 V min B Maximum Quiescent Current VS = +3.3V 5.0 5.5 6.0 6.3 mA max A Minimum Quiescent Current VS = +3.3V 5.0 4.5 4.2 3.8 mA min A 50 44 42 41 dB min A Power-Supply Rejection Ratio (+PSRR) (1) (2) (3) (4) Test levels: (A) 100% tested at 25°C. Over temperature limits set by characterization and simulation. (B) Limits set by characterization and simulation. ©) Typical value only for information. Junction temperature = ambient for 25°C specifications. Junction temperature = ambient at low temperature limit; junction temperature = ambient + 2°C at high temperature limit for over temperature specifications. Current is considered positive out of node. 7 BUF602 www.ti.com SBOS339 – OCTOBER 2005 ELECTRICAL CHARACTERISTICS: VS = +3.3V (continued) Boldface limits are tested at +25°C. At RL = 100Ω, unless otherwise noted. BUF602ID, IDBV TYP PARAMETER CONDITIONS MIN/MAX OVER TEMPERATURE UNITS MIN/ MAX TEST LEVEL (1) –40 to +85 °C typ C +25°C +25°C (2) 0°C to 70°C (3) –40°C to +85°C (3) THERMAL CHARACTERISTICS Specification: ID Thermal Resistance θJA D SO-8 Junction-to-Ambient 125 °C/W typ C DBV SOT23-5 Junction-to-Ambient 150 °C/W typ C 8 BUF602 www.ti.com SBOS339 – OCTOBER 2005 TYPICAL CHARACTERISTICS: VS = ±5V At TA = +25°C and RL = 100Ω, unless otherwise noted. BUFFER BANDWIDTH vs OUTPUT VOLTAGE BUFFER BANDWIDTH vs LOAD RESISTANCE 3 6 RL = 100Ω VOUT = 0.5VPP VO = 0.2VPP RL = 1kΩ 0 −3 VO = 0.5VPP −6 Gain (dB) Gain (dB) 3 VO = 5VPP VO = 1VPP −9 −12 VO = 2VPP 10M 100M −3 −6 −15 1M 0 RL = 100Ω VO = 4VPP −18 −9 1G 2G 1M 10M Frequency (Hz) Figure 1. Figure 2. BUFFER GAIN FLATNESS 1G 2G INPUT VOLTAGE AND CURRENT NOISE DENSITY Input Voltage Noise Density (nV/√Hz) Input Current Noise Density (pA/√Hz) 100 VO = 0.5VPP RL = 100Ω 0.4 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.4 −0.5 10 Input Voltage Noise (4.8nV/√Hz) Input Current Noise (2.1pA/√Hz) 1 1M 10M 100M 1G 100 1k Frequency (Hz) 100k 1M 10M Figure 4. BUFFER SMALL-SIGNAL PULSE RESPONSE BUFFER LARGE-SIGNAL PULSE RESPONSE 150 4 3 Output Voltage (V) 100 50 0 −50 −100 10k Frequency (Hz) Figure 3. Output Voltage (V) 100M Frequency (Hz) 0.5 Gain (dB) RL = 500Ω VOUT = 0.2VPP RL = 100Ω f = 40MHz 2 1 0 −1 −2 −3 −150 −4 Time (2ns/div) Figure 5. VOUT = 5VPP RL = 100Ω f = 40MHz Time (2ns/div) Figure 6. 9 BUF602 www.ti.com SBOS339 – OCTOBER 2005 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At TA = +25°C and RL = 100Ω, unless otherwise noted. HARMONIC DISTORTION vs FREQUENCY −50 −60 Harmonic Distortion (dBc) RL = 500Ω VO = 2VPP −55 Harmonic Distortion (dBc) 5MHz HARMONIC DISTORTION vs LOAD RESISTANCE −50 −65 −70 2nd−Harmonic −75 3rd−Harmonic −80 −85 −90 −95 −60 −70 2nd−Harmonic −80 3rd−Harmonic −90 f = 5MHz VO = 2VPP −100 −100 1 10 100 100 1k Frequency (MHz) Load Resistance (Ω ) Figure 7. Figure 8. HARMONIC DISTORTION vs OUTPUT VOLTAGE 5MHz HARMONIC DISTORTION vs SUPPLY VOLTAGE −40 f = 5MHz RL = 500Ω −70 Harmonic Distortion (dBc) Harmonic Distortion (dBc) −60 2nd−Harmonic −80 −90 3rd−Harmonic −100 −110 RL = 500Ω VO = 2VPP −50 −60 −70 2nd−Harmonic −80 −90 3rd−Harmonic −100 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 2.5 3.0 3.5 4.0 4.5 Output Voltage (VPP) ± Supply Voltage Figure 9. Figure 10. BUFFER OUTPUT IMPEDANCE 5.0 5.5 6.0 BUFFER GROUP DELAY TIME vs FREQUENCY 700 100 Group Delay Time (ps) Output Impedance (Ω ) 600 10 500 400 300 200 100 1 1k 10 10k 100k 1M 10M 100M 1G 0 100 200 300 400 500 600 Frequency (Hz) Frequency (MHz) Figure 11. Figure 12. 700 800 900 1000 BUF602 www.ti.com SBOS339 – OCTOBER 2005 TYPICAL CHARACTERISTICS: VS = ±5V (continued) At TA = +25°C and RL = 100Ω, unless otherwise noted. POWER-SUPPLY REJECTION RATIO vs FREQUENCY OUTPUT SWING VOLTAGE vs TEMPERATURE 4.10 50 45 ±Output Voltage Swing (V) +PSRR 40 PSRR (dB) 35 30 25 20 15 −PSRR 10 4.05 +VO 4.00 −VO 3.95 5 3.90 −40 0 1M 10M 100M −20 0 20 Figure 13. DC DRIFT vs TEMPERATURE 1W Internal Power Limit 10 2 5 1 2 100Ω Load Line 25Ω Load Line 1 50ΩLoad Line 0 −1 −2 −3 1W Internal Power Limit −4 100 50 −5 0 120 −50 Ambient Temperature ( C) 100 −100 80 −150 60 −250 40 −200 20 −300 0 0 300 3 Buffer Input Bias Current (IB) 3 Output Voltage (V) 15 Input Bias Current (µA) 4 Buffer Input Offset Voltage (VOS) −20 120 5 5 −40 100 250 25 0 80 BUFFER OUTPUT VOLTAGE AND CURRENT LIMITATIONS 6 4 Input Offset Voltage (mV) 60 Figure 14. 30 20 40 Ambient Temperature ( C) Frequency (Hz) 200 100k 150 10k Output Current (mA) Figure 15. Figure 16. 11 BUF602 www.ti.com SBOS339 – OCTOBER 2005 TYPICAL CHARACTERISTICS: VS = +5V At TA = +25°C and RL = 100Ω to VS/2, unless otherwise noted. BUFFER BANDWIDTH vs OUTPUT VOLTAGE HARMONIC DISTORTION vs FREQUENCY −40 3 RL = 100Ω VO = 0.5VPP Gain (dB) Harmonic Distortion (dBc) VO = 2VPP −3 VO = 3VPP −6 VO = 0.2VPP −9 −12 VO = 1VPP −15 −55 −60 −65 −70 10M 100M 1G −80 2G 3rd−Harmonic 1 100 Frequency (MHz) Figure 17. Figure 18. BUFFER GAIN FLATNESS 5MHz HARMONIC DISTORTION vs LOAD RESISTANCE −60 VOUT = 0.5VPP RL = 100Ω 0.4 10 Frequency (Hz) 0.5 Harmonic Distortion (dBc) 0.3 0.2 0.1 0 −0.1 −0.2 −0.3 −0.5 1 10 100 −65 2nd−Harmonic −70 −75 −80 500 1k Frequency (MHz) Load Resistance (Ω ) Figure 19. Figure 20. BUFFER PULSE RESPONSE HARMONIC DISTORTION vs OUTPUT VOLTAGE −40 2.7 3.7 −50 2.6 3.1 Large−Signal 2.5VDC ± 1.5V Right Scale 2.5 Harmonic Distortion (dBc) 4.3 Output Voltage (V) 2.8 Small−Signal 2.55VDC ± 0.1V Left Scale 3rd−Harmonic −85 f = 5MHz VO = 2VPP −90 100 −0.4 Output Voltage (mV) 2nd−Harmonic −75 −90 1M Gain (dB) −50 −85 −18 2.5 RL = 500Ω VO = 2VPP −45 0 −60 −70 1.9 2.3 1.3 −90 0.7 −100 2.2 Time (2ns/div) 2nd−Harmonic −80 2.4 RL = 100Ω f = 40MHz f = 5MHz RL = 500Ω 3rd−Harmonic 0.5 1.0 1.5 2.0 2.5 Output Voltage (VPP) Figure 21. 12 Figure 22. 3.0 3.5 BUF602 www.ti.com SBOS339 – OCTOBER 2005 TYPICAL CHARACTERISTICS: VS = +3.3V At TA = +25°C and RL = 100Ω to VS/2, unless otherwise noted. BUFFER BANDWIDTH vs OUTPUT VOLTAGE HARMONIC DISTORTION vs FREQUENCY −40 3 RL = 100Ω VO = 0.5VPP Harmonic Distortion (dBc) Gain (dB) −3 VO = 0.2VPP −6 VO = 1VPP −9 −12 −15 −55 10M 100M 1G −65 −70 2G 1 Figure 24. 5MHz HARMONIC DISTORTION vs LOAD RESISTANCE −50 Harmonic Distortion (dBc) 0.2 0.1 0.0 −0.1 −0.2 −0.3 −0.4 10 100 −55 −60 3rd−Harmonic −65 −70 2nd−Harmonic −75 300 Load Resistance (Ω ) Figure 25. Figure 26. 1.8 −30 2.4 −40 2.1 Large−Signal 1.65VDC ± 0.7V Right Scale 1.8 1.5 Harmonic Distortion (dBc) RL = 100Ω f = 40MHz HARMONIC DISTORTION vs OUTPUT VOLTAGE 2.7 Output Voltage (V) Output Voltage (mV) 1k Frequency (MHz) BUFFER PULSE RESPONSE Small−Signal 1.65VDC ± 0.1V Left Scale f = 5MHz VO = 1VPP −80 100 −0.5 1 100 Figure 23. 0.3 1.6 10 Frequency (MHz) VO = 0.5VPP RL = 100Ω 0.4 1.7 2nd−Harmonic Frequency (Hz) BUFFER GAIN FLATNESS 0.5 1.9 3rd−Harmonic −60 −80 1M Gain (dB) −50 −75 −18 2.0 RL = 500Ω VO = 1VPP −45 0 −50 3rd−Harmonic −60 −70 1.5 1.2 1.4 0.9 −80 0.6 −90 1.3 Time (2ns/div) f = 5MHz RL = 500Ω 2nd−Harmonic 0.50 0.75 1.00 1.25 1.50 Output Voltage (VPP) Figure 27. Figure 28. 13 BUF602 www.ti.com SBOS339 – OCTOBER 2005 APPLICATION INFORMATION WIDEBAND BUFFER OPERATION The BUF602 gives the exceptional AC performance of a wideband buffer. Requiring only 5.8mA quiescent current, the BUF602 will swing to within 1V of either supply rail and deliver in excess of 60mA at room temperature. This low output headroom requirement, along with supply voltage independent biasing, gives remarkable single (+5V) supply operation. The BUF602 will deliver greater than 500MHz bandwidth driving a 2VPP output into 100Ω on a single +5V supply. Figure 29 shows the DC-coupled, dual power-supply circuit configuration used as the basis of the ±5V Electrical and Typical Characteristics. For test purposes, the input impedance is set to 50Ω with a resistor to ground and the output impedance is set to 50Ω with a series output resistor. Voltage swings reported in the specifications are taken directly at the input and output pins while load powers (dBm) are defined at a matched 50Ω load. In addition to the usual power-supply decoupling capacitors to ground, a 0.01µF capacitor can be included between the two power-supply pins. This optional added capacitor will typically improve the 2nd-harmonic distortion performance by 3dB to 6dB. bandwidth. The key requirement of broadband single-supply operation of the BUF602 is to maintain output signal swings within the usable voltage ranges. The circuit of Figure 30 establishes an input midpoint bias using the internal mid-point reference. The input signal is then AC-coupled into this mid-point voltage bias. Again, on a single +5V supply, the output voltage can swing to within 1V of either supply pin while delivering more than 60mA output current. A demanding 100Ω load to a mid-point bias is used in this characterization circuit. VCC 0.1µF VOUT 50Ω To VCC/2 200Ω VCC/2 0.1µF BUF602 Figure 30. AC-Coupled, Single-Supply, Specification and Test Circuit 0.1µF 50Ω Source + LOW-IMPEDANCE TRANSMISSION LINES 4.7µF 50Ω VOUT BUF602 50Ω Load 50Ω 0.1µF + 4.7µF −5V Figure 29. DC-Coupled, Bipolar Supply, Specification and Test Circuit Figure 30 shows the AC-coupled, single-supply circuit configuration used as the basis of the +5V Electrical and Typical Characteristics. Though not a rail-to-rail design, the BUF602 requires minimal input and output voltage headroom compared to other very wideband buffers. It will deliver a 3VPP output swing on a single +5V supply with greater than 400MHz 14 50Ω Load 2kΩ +5V VIN 50Ω The most important equations and technical basics of transmission lines support the results found for the various drive circuits presented here. An ideal transmission medium with zero ohmic impedance would have inductance and capacitance distributed over the transmission cable. Both inductance and capacitance detract from the transmission quality of a line. Each input is connected with high impedance to the line as in a daisy chain or loop-through configuration, and each adds capacitance of at least a few picofarad. The typical transmission line impedance (ZO) defines the line type. In Equation 1, the impedance is calculated by the square root of line inductance (LT) divided by line capacitance ©T): Z0 LT CT (1) BUF602 www.ti.com SBOS339 – OCTOBER 2005 In the same manner, line inductance and capacitance determine the delay time of a transmission line as shown in Equation 2: L T C T R OUT VIN (2) Typical values for ZO are 240Ω for symmetrical traces and 75Ω or 50Ω for coax cables. ZO sometimes decreases to 30Ω to 40Ω in high data rate bus systems for bus lines on printed circuit boards (PCBs). In general, the more complex a bus system is, the lower ZO will be. Because it increases the capacitance of the transmission medium, a complex system lowers the typical line impedance, resulting in higher drive requirements for the line drivers used here. Transmission lines are almost always terminated on the transmitter line and always terminated on the receiver side. Unterminated lines generate signal reflections that degrade the pulse fidelity. The driver circuit transmits the output voltage (VOUT) over the line. The signal appears at the end of the line and will be reflected when not properly terminated. The reflected portion of VOUT, called VREFL, returns to the driver. The transmitted signal is the sum of the original signal VOUT and the reflected VREFL. V T VOUT VREFL (3) ZO BUF602 VOUT RLOAD Figure 31. Typical Line Driver Circuit SELF-BIASED, LOW-IMPEDANCE MID SUPPLY VOLTAGE REFERENCE Using the mid-point reference in conjunction with the BUF602 allows the creation of a low-impedance reference from DC to 250MHz. The 0.1µF external capacitor is used in Figure 32 to filter the noise. VS BUF602 50kΩ 200Ω x1 The magnitude of the reflected signal depends upon the typical line impedance (Z0) and the value of the termination resistor Z1. V REFL VOUT (4) Γ denotes the reflection factor and is described by Equation 5. ZZ ZZ 1 0 1 0 (5) Γ can vary from –1 to +1. The conditions at the corner points of Equation 5 are as follows: Z0 = Z1 → Γ=0 VREFL = 0 Z0 = ∞ → Γ = –1 VREFL = –VOUT Z0 = 0 → Γ = +1 VREFL = +VOUT An unterminated driver circuit complicates the situation even more. VREFL is reflected a second time on the driver side and wanders like a ping-pong ball back and forth over the line. When this happens, it is usually impossible to recover the output signal VOUT on the receiver side. x1 VS/2 50kΩ 20Ω 0.1µF Figure 32. Self-Biased, Low Impedance Mid Supply Voltage Reference SELF-REFERENCED, AC-COUPLED WIDEBAND BUFFER Whenever a high-speed AC-coupled buffer is required, you should consider the BUF602. One feature of the BUF602 is the mid-supply reference voltage, saving external components and power dissipation. A capacitor on the output of the mid-supply reference is recommended to bandlimit the noise contribution of the mid-supply reference voltage generated by the two 50kΩ internal resistors. This circuit is shown on the front page of the datasheet. The figure shown in Figure 31 makes use of the BUF602 as a line driver. The BUF602 exhibits high input impedance and low output impedance, making it ideal whenever a buffer is required. 15 BUF602 www.ti.com SBOS339 – OCTOBER 2005 DESIGN-IN TOOLS DEMONSTRATION BOARDS Two PC boards are available to assist in the initial evaluation of circuit performance using the BUF602 in its two package styles. Both are available free, as unpopulated PC boards delivered with descriptive documentation. The summary information for these boards is shown in Table 1. Table 1. Demo Board Listing PRODUCT PACKA GE BOARD PART NUMBER LITERATURE REQUEST NUMBER BUF602ID SO-8 DEM-BUF-SO-1A SBAU118 BUF602IDBV SOT23-5 DEM-BUF-SOT-1A SBAU117 To request either of these boards, use the Texas Instruments web site (www.ti.com). MACROMODELS AND APPLICATIONS SUPPORT Computer simulation of circuit performance using SPICE is often useful when analyzing the performance of analog circuits and systems. This is particularly true for video and RF amplifier circuits where parasitic capacitance and inductance can have a major effect on circuit performance. A SPICE model for the BUF602 is available through the TI web site (www.ti.com). These models do a good job of predicting small-signal AC and transient performance under a wide variety of operating conditions. They do not do as well in predicting the harmonic distortion or dG/dP characteristics. These models do not attempt to distinguish between package types in their small-signal AC performance. graph is bounded by a Safe Operating Area of 1W maximum internal power dissipation. Superimposing resistor load lines onto the plot shows that the BUF602 can drive ±3V into 25Ω or ±3.5V into 50Ω without exceeding the output capabilities or the 1W dissipation limit. The minimum specified output voltage and current over-temperature are set by worst-case simulations at the cold temperature extreme. Only at cold startup will the output current and voltage decrease to the numbers shown in the Electrical Characteristic tables. As the output transistors deliver power, the junction temperatures will increase, decreasing both VBE (increasing the available output voltage swing) and increasing the current gains (increasing the available output current). In steady-state operation, the available output voltage and current will always be greater than that shown in the over-temperature specifications, since the output stage junction temperatures will be higher than the minimum specified operating ambient. For a buffer, the noise model is shown in Figure 33. Equation 6 shows the general form for the output noise voltage using the terms shown in Figure 33. en eO RS in √4kTRS Figure 33. Buffer Noise Analysis Model OUTPUT CURRENT AND VOLTAGE The BUF602 provides output voltage and current capabilities that are not usually found in wideband buffers. Under no-load conditions at 25°C, the output voltage typically swings closer than 1.2V to either supply rail; the +25°C swing limit is within 1.2V of either rail. Into a 15Ω load (the minimum tested load), it is tested to deliver more than ±60mA. The specifications described above, though familiar in the industry, consider voltage and current limits separately. In many applications, it is the voltage × current, or V-I product, which is more relevant to circuit operation. Refer to the Buffer Output Voltage and Current Limitations plot (Figure 16) in the Typical Characteristics. The X and Y axes of this graph show the zero-voltage output current limit and the zero-current output voltage limit, respectively. The four quadrants give a more detailed view of the BUF602 output drive capabilities, noting that the 16 eO e 2 n 2 inR S 4kTR S nV Hz (6) THERMAL ANALYSIS Due to the high output power capability of the BUF602, heatsinking or forced airflow may be required under extreme operating conditions. Maximum desired junction temperature will set the maximum allowed internal power dissipation as described below. In no case should the maximum junction temperature be allowed to exceed 150°C. Operating junction temperature (TJ) is given by TA + PD × θJA. The total internal power dissipation (PD) is the sum of quiescent power (PDQ) and additional power dissipated in the output stage (PDL) to deliver load power. Quiescent power is simply the specified no-load supply current times the total supply voltage across the part. PDL will depend on the required BUF602 www.ti.com SBOS339 – OCTOBER 2005 output signal and load but would, for a grounded resistive load, be at a maximum when the output is fixed at a voltage equal to ½ of either supply voltage (for equal bipolar supplies). Under this condition, PDL = VS2/(4 × RL). Note that it is the power in the output stage and not into the load that determines internal power dissipation. As a worst-case example, compute the maximum TJ using a BUF602IDBV in the circuit on the front page operating at the maximum specified ambient temperature of +85°C and driving a grounded 20Ω load. PD = 10V × 5.8mA + 52/(4 × 20Ω) = 370.5mW Maximum TJ = +85°C + (0.37W × 150°C/W) = 141°C. Although this is still below the specified maximum junction temperature, system reliability considerations may require lower tested junction temperatures. The highest possible internal dissipation will occur if the load requires current to be forced into the output for positive output voltages or sourced from the output for negative output voltages. This puts a high current through a large internal voltage drop in the output transistors. The output V-I plot (Figure 16) shown in the Typical Characteristics include a boundary for 1W maximum internal power dissipation under these conditions. BOARD LAYOUT GUIDELINES Achieving optimum performance with a high-frequency amplifier like the BUF602 requires careful attention to board layout parasitics and external component types. Recommendations that will optimize performance include: a) Minimize parasitic capacitance to any AC ground for all of the signal I/O pins. Parasitic capacitance on the output pins can cause instability: on the noninverting input, it can react with the source impedance to cause unintentional bandlimiting. To reduce unwanted capacitance, a window around the signal I/O pins should be opened in all of the ground and power planes around those pins. Otherwise, ground and power planes should be unbroken elsewhere on the board. and ground traces to minimize inductance between the pins and the decoupling capacitors. The power-supply connections should always be decoupled with these capacitors. An optional supply decoupling capacitor (0.1µF) across the two power supplies (for bipolar operation) will improve 2nd-harmonic distortion performance. Larger (2.2µF to 6.8µF) decoupling capacitors, effective at lower frequency, should also be used on the main supply pins. These may be placed somewhat farther from the device and may be shared among several devices in the same area of the PC board. c) Careful selection and placement of external components will preserve the high-frequency performance of the BUF602. Resistors should be a very low reactance type. Surface-mount resistors work best and allow a tighter overall layout. Metal film or carbon composition, axially-leaded resistors can also provide good high-frequency performance. Again, keep their leads and PC board traces as short as possible. Never use wirewound type resistors in a high-frequency application. d) Connections to other wideband devices on the board may be made with short, direct traces or through onboard transmission lines. For short connections, consider the trace and the input to the next device as a lumped capacitive load. Relatively wide traces (50mils to 100mils) should be used, preferably with ground and power planes opened up around them. If a long trace is required, and the 6dB signal loss intrinsic to a doubly-terminated transmission line is acceptable, implement a matched impedance transmission line using microstrip or stripline techniques (consult an ECL design handbook for microstrip and stripline layout techniques). A 50Ω environment is normally not necessary on board, and in fact, a higher impedance environment will improve distortion as shown in the distortion versus load plots. e) Socketing a high-speed part like the BUF602 is not recommended. The additional lead length and pin-to-pin capacitance introduced by the socket can create an extremely troublesome parasitic network that makes it almost impossible to achieve a smooth, stable frequency response. Best results are obtained by soldering the BUF602 onto the board. b) Minimize the distance (< 0.25") from the power-supply pins to high-frequency 0.1µF decoupling capacitors. At the device pins, the ground and power-plane layout should not be in close proximity to the signal I/O pins. Avoid narrow power 17 BUF602 www.ti.com SBOS339 – OCTOBER 2005 INPUT AND ESD PROTECTION The BUF602 is built using a very high-speed complementary bipolar process. The internal junction breakdown voltages are relatively low for these very small geometry devices. These breakdowns are reflected in the Absolute Maximum Ratings table. All device pins are protected with internal ESD protection diodes to the power supplies as shown in Figure 34. +VCC External Pin Internal Circuitry −VCC Figure 34. Internal ESD Protection 18 These diodes provide moderate protection to input overdrive voltages above the supplies as well. The protection diodes can typically support 30mA continuous current. Where higher currents are possible (for example, in systems with ±15V supply parts driving into the BUF602), current-limiting series resistors should be added into the two inputs. Keep these resistor values as low as possible since high values degrade both noise performance and frequency response. PACKAGE OPTION ADDENDUM www.ti.com 7-Nov-2005 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) BUF602ID ACTIVE SOIC D 8 75 TBD Call TI Call TI BUF602IDBVR ACTIVE SOT-23 DBV 5 3000 TBD Call TI Call TI BUF602IDBVT ACTIVE SOT-23 DBV 5 250 TBD Call TI Call TI BUF602IDR ACTIVE SOIC D 8 2500 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. 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