CA3194 Semiconductor S IGN OR DF NDE May 1997 NOT ES WD NE Single Chip PAL Luminance/Chroma Processor ME COM RE Features Description • All PAL Luminance and Chrominance Processing Circuitry on a Single Chip in a 24-Lead Plastic Package The Harris CA3194E is a silicon monolithic integrated circuit designed to perform all of the signal processing functions for both the chroma and luminance signals of PAL color television receivers. • Phase-Locked Subcarrier Regeneration Utilizing Sample-and-Hold This circuit performs all the functions needed between the video detector and the video RGB output stages. DC contrast, brightness, and saturation controls and average beam limiting functions are included. The RGB buffer stages are capable of delivering 5mA of current into the video output stages. • DC Controls for Brightness, Contrast, and Color Saturation Functions • Input for Average Beam-Current Limiting • Contrast Control Having Excellent Tracking of Luma and Chroma Channels • Low-lmpedance RGB Outputs with Excellent Tracking for Direct Coupling to Video Driver Circuitry NOTE: Formerly Dev. No. TA10313. Ordering Information PART NUMBER TEMPERATURE RANGE -40oC CA3194E to +85oC PACKAGE 24 Lead PDIP Pinout CA3194 (PDIP) TOP VIEW TERMINAL VOLTAGE AND CURRENT RATINGS APC FILTER 7 AVER. BEAM 24 INFO 23 BRIGHTNESS CONTROL 22 PICTURE CONTROL 21 LOW PASS FILTER 20 LUMA INPUT 19 PEAK BEAM LEVEL 18 R OUTPUT APC FILTER 8 17 G OUTPUT 90o INPUT 9 16 B OUTPUT 0o INPUT 10 15 VR-Y INPUT VCO OUTPUT 11 14 VB-Y INPUT GND 1 CHROMA OUT 2 SAT. CONTR. 3 CHROMA INPUT 4 ACC FILTER 5 ACC FILTER 6 VCC 12 13 SANDCASTLE TERMINAL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NOTE: VOLTAGE (NOTE 1) -V MIN MAX 0 13 0 8 0 5 0 Note 0 Note 0 Note 0 8 0 8 0 13 0 13 0 12 0 5 0 5 0 13 0 13 0 13 0 Note 0 5 0 Note 0 8 0 5 0 12 CURRENT - mA IIN IOUT 0 30 10 0.1 0.5 0.7 10 1.5 1.5 10 10 10 - 1. The maximum should not exceed the VCC voltage. Voltage with respect to Terminal 1 for VCC (Terminal 12) of 12V ±10%. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright © Harris Corporation 1997 7-56 File Number 1270.3 Specifications CA3194 Absolute Maximum Ratings Operating Conditions Supply Voltage and Current Pin 12 Voltage Range . . . . . . . . . . . . . . . . 11V (Min) to 13V (Max) Pin 12 Current Range . . . . . . . . . . . . . 44mA (Typ) to 60mA (Max) Power Dissipation Up to TA = +25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825mW Above TA = +25oC. . . . . . . . . . . . . . . . Derate Linearly 8.7mW/oC Junction Temperature (Plastic Package) . . . . . . . . . . . . . . . +150oC Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . . . . . +300oC Operating Temperature Range . . . . . . . . . . . . . . . . . -40oC to +85oC Thermal Package Characteristics (oC/W) θJA PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications TA = +25oC, VCC = 12V, VS = 2.85V, VC = 2.85V, VAB = VPB = VCC, VB adjusted for V18 = 6.3V, CX adjusted for FOSC = 4.43361875MHz, Sandcastle: VBG = 8.0V, VBLANK = 3.5V - Burst Gate centered on Burst. These conditions exist except as otherwise noted. See Figure 19 for test circuit PARAMETER TEST CONDITIONS TYPICAL VALUE UNITS 6 kΩ 5 pF 0.5 VP-P 8 MHz LUMINANCE SECTION Input Impedance (Terminal 20) Luminance Channel Input Voltage Luma Input Signal = 30% Sync. Bandwidth of Luminance Channel Luma Input Signal: 0.5VP-P (30% Sync) modulated CW Adj. modulation frequency for -3dB at color outputs. Brightness Control Range (Terminal 23) For Control Characteristics, See Figures 1 and 2. 0 - 3.5 VDC Output Black Level Luma Input Signal: 0.5VP-P (30% Sync) VB 0V - 5V,Measured at Pin 18 black level. See Figures 1 and 2. 5.9-9.7 VDC 0.6 Max. VDC Range Offset Contrast Control Range (Terminal 22) Luminance Input: 0.5VP-P (30% Sync), for Control Characteristics. See Figure 3 0-5 VDC Luminance Gain Control Range Luminance Input: 0.5VP-P (30% Sync), VC = 0.5V - 5V measure Pin 18 black level to maximum white level. See Figure 4. 32 dB RGB Output Swing Luminance Input: 0.5VP-P (30% Sync), VC = 5V, read black level to peak white. See Figures 5 and 6. 4 VP-P 4.5 kΩ 5 pF Chroma 220 mVP-P Burst 100 mVP-P +6 - (-20) dB CHROMlNANCE SECTION Input Impedance (Terminal 4) Chroma Channel Input Voltage See Figures 7 and 8. ACC Range Input Burst Level for Kill (Note 1) Adjust chroma input Pin 4 until Pin 2 ≤25mVP-P. Measure Burst level at Pin 4. 10 mVP-P Contrast Control Chroma/Luma Tracking Chroma Input: Burst = 100mVP-P, Chroma = 220mVP-P. Luminance Input: 0.35VP-P, VS adjusted for Chroma at Pin 18 = 2VP-P. VC is adjusted for luminance at Pin 18 = 2VP-P, VC is again adjusted for luminance of +6 and -9dB. Then read chroma percentage difference. See Figure 9. ±5 % 7-57 Specifications CA3194 Electrical Specifications TA = +25oC, VCC = 12V, VS = 2.85V, VC = 2.85V, VAB = VPB = VCC, VB adjusted for V18 = 6.3V, CX adjusted for FOSC = 4.43361875MHz, Sandcastle: VBG = 8.0V, VBLANK = 3.5V - Burst Gate centered on Burst. These conditions exist except as otherwise noted. See Figure 19 for test circuit (Continued) PARAMETER TEST CONDITIONS TYPICAL VALUE UNITS 0-5 VDC Saturation Control Range (Terminal 3) For control characteristic, see Figure 10. Maximum Chroma Output Voltage (Terminal 2) Chroma Input: Burst = 100mVP-P, Chroma = 220mVP-P. Adjust VC and VS for maximum Pin 2 output. 2.5 VP-P Chroma Input: Burst = 100mVP-P, Chroma = 220mVP-P. Adjust CX for HI/LO fOSC without Chroma signal. Apply signal to lock. ±500 Hz 2 Deg./ 100Hz OSCILLATOR SECTION Pull-In Range Static Phase Error DEMODULATOR SECTION R-Y Demodulator Conversion Gain Chroma Input: Burst =100mV, Chroma = 220mVP-P,Vø. Adjust VC for V18 = 1V. Read V15. Calculate V18/V15. 10 Ratio B-Y Demodulator Conversion Gain Chroma Input: Burst = 100mVP-P, Uø. Read V16 and V14. Calculate V16/V14. VC remains as for R-Y gain. 18 Ratio G-Y/B-Y Matrix Ratio Chroma Input: Burst =100mVP-P, Chroma = 220mVP-P, Uø read V17 and V16, Calculate V17/V16. VC remains as above. 0.2 Ratio G-Y/R-Y Matrix Ratio Chroma Input: Burst =100mVP-P, Chroma = 220mVP-P, Vø. Read V17 and V18. Calculate V17/V18. VC remains as above. 0.5 Ratio Sub-Carrier and Harmonic Content at Outputs No Chroma or Luma Input. Read residual carrier at outputs. 30 mVP-P 2-5 V 6.5 - VCC V SANDCASTLE PULSE Horizontal and Vertical Blanking Pedestal Burst Gate Pulse NOTES: 1. If a different value is desired, see the Threshold Adjustment Circuit of Figure 17. 2. Use of the circuit of Figure 18 is suggested to prevent increased color saturation at low level RF signals. 3. The reference voltage can be adjusted by changing the values of the voltage divider. Circuit Description (See Block Diagram and Figure 20) The chroma signal is externally separated from the video signal by means of a bandpass or high-pass filter and applied to pin 4. The burst is separated in the first chroma stage and applied to the synchronous detector which provides information to sample-and-hold circuits for APC (phase-locked loop), ACC (automatic chroma gain control) and identification and killing. The 4.43MHz crystal oscillator is phase-locked to the burst and provides 0 degrees and 90 degrees (via an external phase shifter) carriers to the chroma demodulators. The burst and chroma amplitude at the output of the first chroma amplifier is kept constant by the automatic gain control. A buffer stage drives the external PAL delay line. The separated U and V signals are applied to pins 14 and 15, respectively, and demodulated. A standard G-Y matrix is included on the chip. The luminance signal passes through the subcarrier trap and through the luminance delay line and enters the chip at pin 20. Contrast and brightness control is provided before the luminance signal is combined with the color difference signals in the Y matrix. Average and peak beam limiting circuits are controlled from pins 24 and 19. The second chroma stage provides saturation control (pin 3) which tracks the contrast control in the luminance channel. This stage is also used for color killing. 7-58 7-59 15 20 VR-Y INPUT LUMA INPUT 2 CHROMA OUT 14 3 SAT. CONTR. VB-Y INPUT 4 CHROMA INPUT BG COMPARATOR + LEVEL SHIFT 24 AVER. BEAM INFO. 22 PICTURE CONTROL Y MATRIX Y MATRIX BRIGHTNESS CONTROL 23 BG BG FLIP FLOP BG FF SAMPLE AND HOLD 7 PEAK BEAM LEVEL 19 PEAK BEAM LIMIT COMPARATOR DECODER BG BG BUFFER 0 DEGREE AMPLIFIER SAMPLE AND HOLD 8 APC FILTER 90 DEGREE CARRIER 90o AMPLIFIER SANDCASTLE APC FILTER BL BG LOW PASS FILTER BG 21 R OUTPUT G OUTPUT B OUTPUT BLANKING IDENT BRIGHTNESS COMPARATOR AMPLIFIER + PAL SWITCH + PHASE EQ Y MATRIX FF 0 DEGRE CARRIER ACC SAMPLE AND HOLD AVERAGE BEAM LIMITER G-Y MATRIX AMPLIFIER +PHASE EQ KILLER FF BG LUMA AMPLIFIER R-Y DEMOD B-Y DEMOD BUFFER STAGE 2ND CHROMA STAGE BG SYNCHRONOUS DETECTOR FOR APC AND ACC 5 6 1ST CHROMA STAGE + SWITCHING ACC FILTER ACC FILTER 90o INPUT 0o INPUT VCO OUTPUT 1 GROUND (SUB) 12 VCC 18 R OUTPUT 17 G OUTPUT 16 B OUTPUT SAND 13 CASTLE 9 10 11 CA3194 Block Diagram CA3194 PIN 2 - CHROMA OUTPUT (VP-P) RED BAR Typical Performance Curves 11 VC = VS = 2.85V VCC = 12V PIN 20 : 0.5VP-P (30% SYNC) PIN 18 - BLACK LEVEL (V) 10 9 8 7 6 5 4 3 0 1 2 3 4 PIN 23 - BRIGHTNESS CONTROL (VB, V) 3 2 1 0 1 2 3 4 PIN 22 - COLOR CONTRAST CONTROL (VC, V) 0 5 FIGURE 2. CONTRAST CONTROL (VC) MEASURED AT 2ND CHROMA AMPLIFIER OUTPUT TERMINAL 32 4 VS = 2.85V VCC = 12V PIN 20 : 0.5VP-P (30% SYNC) BLACK LEVEL = 7V 3 VC = VS = 2.85V V18 = 2VP-P AT VCC = 12V VB SET TO BLACK LEVEL = 7V 28 LUMA AMPL GAIN (dB) (WHITE TO BLACK LEVEL) VS = 2.85V VCC = 12V PIN 4 : BURST = 100mVP-P CHROMA = 220mVP-P 5 FIGURE 1. BRIGHTNESS CONTROL (VB) MEASURED AT PIN 18 OUTPUT TERMINAL PIN 18 - LUMA OUTPUT (V) 4 2 1 24 20 16 12 8 4 0 0 0 1 2 3 4 PIN 22 - CONTRAST CONTROL (VC, V) 5 7 9 14 12 V18 - % DIFFERENCE LUMA/CHROMA 20 16 TOP CLIPPING 10 BLACK LEVEL 8 11 12 13 14 15 16 17 FIGURE 4. LUMA GAIN vs SUPPLY VOLTAGE (VCC) MEASURED AT LUMA AMPLIFIER OUTPUT TERMINAL 18 VS = 2.85V VB AND VC ADJUSTED FOR MAX LINEAR V16 PIN 4: BURST = 100mVP-P CHROMA = 220mVP-P 10 PIN 12 - SUPPLY VOLTAGE (V) FIGURE 3. CONTRAST CONTROL (VC) MEASURED AT PIN 18 OUTPUT TERMINAL BLUE OUTPUT (V16 MAX, V) 8 6 BOTTOM CLIPPING 4 CHROMA INPUT: BURST = 100mVP-P CHROMA = 220mVP-P LUMA INPUT: 0.5VP-P (30% SYNC) ADJUST VC FOR V18 = VPEAK LUMA, THEN ADJUST VS FOR V18 = 2VPEAK CHROMA (RED BAR) 10 0 -10 -20 2 11 12 13 14 15 PIN 12 - SUPPLY VOLTAGE (V) 0 16 FIGURE 5. LINEAR OPERATING RANGE AS A FUNCTION OF VCC MEASURED AT PIN 16 OUTPUT TERMINAL (BEST OPERATING RANGE IS 11-13V VCC) 1 2 3 4 PIN 22 - CONTRAST CONTROL (VC, V) 5 FIGURE 6. LUMA/CHROMA TRACKING AS A FUNCTION OF VC MEASURED AT PIN 18 OUTPUT TERMINAL 7-60 CA3194 CHROMA OUTPUT (V2, dB) 0 (Continued) V18 - ∆V (BLACK LEVEL TO WHITE) LUMA Typical Performance Curves COLOR UNKILL -1 VC = VS = 2.85V VCC = 12V CHROMA INPUT: BURST = 100mVP-P CHROMA = 220mVP-P (0dB) CHROMA OUTPUT: 880mVP-P (0dB) -2 -3 -4 COLOR KILL -5 -20 -10 CHROMA INPUT (V4, dB) 0 2 1 0 1 2 3 4 PIN 22 - CONTRAST CONTROL (VC, V) 1 2 3 4 5 4 VC = 2.85V VCC = 12V PIN 4 : BURST = 100mVP-P CHROMA = 220mVP-P 3 2 1 0 1 2 3 4 PIN 3 - CHROMA SATURATION CONTROL (VC , VP-P) 5 8 VC = VS = 2.85V VCC = 12V NO INPUT SIGNAL PIN 18 - RED OUTPUT (VP-P) RED BAR VR - VG 0 FIGURE 10. SATURATION CONTROL (VS) MEASURED AT CHROMA AMPLIFIER OUTPUT TERMINAL PIN 2 0 -100 CENTER DIFF. CORRECTED TO ZERO AT 7.0V - PIN 18 100 VR - VB R/G AND R/B VOLT DIFF. (mV) 1 0 5 FIGURE 9. LUMA/CHROMA TRACKING WITH CONTRAST CONTROL MEASURED AT PIN 18 OUTPUT TERMINAL 100 2 FIGURE 8. LUMA/CHROMA TRACKING vs CONTRAST CONTROL MEASURED AT PIN 18 OUTPUT TERMINAL 3 0 3 PIN 22 - CONTRAST CONTROL (VC, V) PIN 2 - CHROMA OUTPUT (VP-P) RED BAR V18 - ∆V (BLACK LEVEL TO WHITE) RED BAR 4 4 0 CHROMA INPUT: BURST = 100mVP-P CHROMA = 220mVP-P LUMA INPUT: 0.5VP-P (30% SYNCH) ADJUST VC FOR V18 = 2VPEAK LUMA, THEN ADJUST VS FOR V18 = 2VPEAK CHROMA (RED BAR) 5 5 +6 FIGURE 7. ACC CHARACTERISTICS MEASURED AT PIN 2 OUTPUT TERMINAL 6 CHROMA INPUT: BURST = 100mVP-P CHROMA = 220mVP-P LUMA INPUT: 0.5VP-P (30% SYNCH) ADJUST VC FOR V18 = 2VPEAK LUMA, THEN ADJUST VS FOR V18 = 2VPEAK CHROMA (RED BAR) 6 0 -100 BOTTOM CLIPPING OF RED BAR 6 4 VS = 2.85V VCC = 12V PIN 4 : BURST = 100mVP-P CHROMA = 220mVP-P ADJUST VC (DL700 DELAY LINE IN CIRCUIT) 2 0 5 6 7 8 9 R - OUT (PIN 18) BLACK LEVEL REFERENCE - (VB ADJ, V) FIGURE 11. DIFFERENTIAL BLACK-LEVEL TRACKING MEASURED AT RGB OUTPUT TERMINALS 0 1 2 PIN 2 - CHROMA OUTPUT (VP-P) RED BAR 3 FIGURE 12. PIN 18 OUTPUT vs PIN 2 VOLTAGE MEASURED AT CHROMA OUTPUT TERMINALS AND R OUTPUT 7-61 CA3194 Typical Performance Curves (Continued) 13 VCC = 12V VC : SET FOR V18 = 2VP-P VIN : SET FOR BLACK LEVEL = 7V PIN 20: LUMA = 0.5VP-P (30% SYNC) PEAK WHITE LEVEL 8 7 PIN 18 - LUMA OUTPUT (V) 9 12 INITIAL LUMA SET AT 2.0 VP-P PIN 18 - OUTPUT PEAK WHITE AND BLACK LEVEL (V) 10 REDUCED INITIAL BLACK LEVEL SET 7.0V LUMA BLACK LEVEL PEAK WHITE 11 10 9 BLACK LEVEL VCC = 12V VC = 5V VB = 3.5V PIN 20: LUMA = 0.5VP-P (30% SYNC) RC - CONTRAST TERMINAL RESISTANCE = 47kΩ 8 R = 47kΩ 7 6 6 5 0 2 4 6 8 10 1 0 2 3 4 5 6 7 8 9 10 PIN 24 - AVERAGE BEAM LIMITER (VAB, V) PIN 24 - AVERAGE BEAM LIMITER (VAB, V) FIGURE 13. AVERAGE BEAM LIMITER (VAB) MEASURED AT PIN 18 OUTPUT FIGURE 14. AVERAGE BEAM LIMITER (VAB) MEASURED AT PIN 18 OUTPUT 12 PEAK WHITE 11 VCC = 12V VC = 5V VB : SET FOR BLACK LEVEL = 6.3V PIN 20: LUMA = 0.5VP-P (30% SYNC) VARY RC - CONTRAST TERMINAL RESISTANCE 10 PIN 18 (V) R =15kΩ 9 R = 22kΩ 8 R =33kΩ 7 R = 47kΩ 6 5 H+V BLANK PEDESTAL 4 0 1 2 3 4 5 6 7 VBG = 6.5V TO VCC BG PULSE BLACK LEVEL 8 9 10 VBLANK = 2V TO 5V 0V PIN 24 - AVERAGE BEAM LIMITER (VAB, V) FIGURE 15. AVERAGE BEAM LIMITER (VAB) MEASURED AT PIN 18 OUTPUT FIGURE 16. SANDCASTLE INPUT WAVEFORM VCC 2 5.1M 0.01 µF CA3194E CA3194E CHROMA OUTPUT +5V 5K 3 VCC 5.1M 27K (NOTE 1) 5 SATURATION CONTROL 47K 300 5.1M (NOTE 2) 1.0µF (NOTE 1) 1.5K NOTES: 1. Nominal values used in NTSC system. 2. Small signal n-p-n. FIGURE 17. KILLER-THRESHOLD LEVEL CONTROL FIGURE 18. EXTERNAL OVERLOAD DETECTOR 7-62 CA3194 Test Circuit BEAM LIMIT INFO (VAB) BRIGHTN. CONTRAST (VB) (VC) 1K8 1K 15K + LUMA INPUT 2.2µ 15K + OUTPUTS +12V R G B 18 17 16 SAND CASTLE INPUT (VPB) RC 220n + 2.2µ 1µ + 1K 23 24 16µ AV. BEAM LIMIT BRIGHTNESS 22 21 CONTRAST LP FILTER 20 LUMA INPUT 19 PEAK BEAM LIMIT R OUT G OUT B OUT 15 15K 14 VR-Y VB-Y 13 SAND CASTLE INPUT CA3194E CHROMA INPUT GND CHROMA OUT 1 SAT. 2 CHROMA INPUT 3 ACC ACC APC APC VCO 90o 5 6 7 8 9 4 2K2 15K + 2µ2 10p CO DELAY LINE AMPLITUDE 4µ7 22n 0.1µ 120p 5% RO 10% 10n 12 +12V † 0.1µ 820 CX 5-25p + 22µ 39pF 390Ω DL PHASE B+ 11 SAT. (VS) 2K2 1K + + 47n 330 1µ VCO OUT 10 22µH 68p 3n3 VCO 0o 2 L4 10µH 10n 47p 3 DL 700 1 FIGURE 19. TEST CIRCUIT NOTES: † 4.43361875MHz Trim CO for zero phase; Trim RO for quad phase. 7-63 4 L5 9µH BIF. 430Ω/5% CA3194 Test Circuit (Continued) BEAM LIMIT INFO (VAB) BRIGHTN. CONTRAST (VB) (VC) 1K8 10K 15K + LUMA INPUT 2.2µ R G B 18 17 16 SAND CASTLE INPUT (VPB) 15K + OUTPUTS +12V 220n + 2.2µ 1µ + 1K 23 24 16µ AV. BEAM LIMIT BRIGHTNESS 22 21 CONTRAST LP FILTER 20 LUMA INPUT 19 PEAK BEAM LIMIT G OUT B OUT APC APC VCO 90o 7 8 9 R OUT 15 15K 14 VR-Y VB-Y 13 SAND CASTLE INPUT CA3194E CHROMA INPUT GND CHROMA OUT 1 CHROMA INPUT SAT. 2 3 ACC 4 5 DELAY LINE AMPLITUDE 1K 10n 2K2 2µ2 0.05 0.01 10n 10 5% RO + 22n 0.1µ 120p VCO OUT 10% B+ 11 12 +12V † 0.1µ 1500 CX 5-25p + 22µ 39pF 390Ω DL PHASE 330 3.3µ + SAT. (VS) 2K2 1.8K + 15K + 2µ2 10p CO 6 VCO 0o 33µH 68p 3n3 ACC 2 L4 10µH 47p 3 PAL DL 50 1 4 FIGURE 20. APPLICATION CIRCUIT FOR PAL M NOTE: † 3.575611MHz 7-64 L5 9µH BIF. 430Ω/5%