INTERSIL CA3252M

CA3252
Quad Gated Non-Inverting Power Driver
March 1998
Features
Description
• Four 600mA Non-Inverting Power Output Drivers
The CA3252 is used to interface low-level logic to high current loads. Each Power Driver has four inverting switches
consisting of an inverting logic input stage and an inverting
low-side driver output stage. All inputs are 5V TTL/CMOS
logic compatible and have a common Enable input. On-chip
steering diodes are connected from each output (in pairs) to
the CLAMP pins (in pairs) which may be used in conjunction
with external zener diodes to protect the IC against over-voltage transients that result from inductive load switching. The
CA3252 may be used in a variety of automotive and industrial control applications to drive relays, solenoids, lamps and
small motors.
• 50V and 1A Maximum Rated Power Output Drivers
• VCE(SUS) Capability . . . . . . . . . . . . . . . . . . . . . . . . . 35V
• Inputs Compatible With TTL or 5V CMOS Logic
• Suitable For Resistive, Lamp or Inductive Loads
• Inductive Clamps on Each Output
• High Dissipation Power-Frame Package
• Operating Temperature Ranges . . . . . . -40oC to 105oC
To allow for maximum heat transfer from the chip, all ground
pins on the DIP and SOIC packages are directly connected
to the mounting pad of the chip. Integral heat spreading lead
frames directly connect the bond pad and ground leads for
good heat dissipation. In a typical application, the package is
mounted on a copper PC Board. By increasing copper
ground area on the PC Board, more heat is conducted away
from the ground leads. The junction-to-ambient thermal
resistances may be reduced to less than 40oC/W with
approximately two square inches of copper area.
Applications
• Solenoids
• Relays
• Lamps
• Steppers
• Small Motors
• Displays
Ordering Information
System Applications
PART
NUMBER
• Automotive
TEMP. (oC)
PACKAGE
PKG. NO.
• Appliances
CA3252E
-40 to 105
16 Ld PDIP
E16.3
• Industrial Controls
CA3252M
-40 to 105
20 Ld SOIC
M20.3
• Robotics
Pinouts
CA3252E
(PDIP)
TOP VIEW
CA3252M
(SOIC)
TOP VIEW
OUT A
1
16
IN A
CLAMP AB
1
CLAMP AB
2
15
IN B
NC
2
19 IN A
NC
3
18 INB
OUT B
4
17 ENABLE
GND
5
16 GND
GND
6
15 GND
OUT C
7
14 VCC
NC
8
13 IN C
NC
9
12 IN D
OUT B
3
14
ENABLE
GND
4
13
GND
GND
OUT C
CLAMP CD
OUT D
5
6
7
8
12
11
10
9
GND
VCC
IN C
IN D
CLAMP CD 10
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
1
20 OUT A
11 OUT D
File Number
1542.2
CA3252
Functional Block Diagram
VCC
V+
OUT D
IN D
CLAMP
IN C
OUT C
GND
GND
GND
GND
ENABLE
OUT B
IN B
CLAMP
IN A
OUT A
VCC
V+
RELAY
OUT D
IN D
CLAMP
VBATT
IN C
OUT C
SOLENOID
GND
GND
VBATT
ENABLE
OUT B
HIGH CURRENT
HIGH SIDE DR
IN B
CLAMP
MOTOR
IN A
VBATT
OUT A
LAMP
TRUTH TABLE (Each Output)
ENABLE
IN
OUT
H
L
L
H
H
H
L
X
H
H = High, L = Low, X = Don’t Care
FIGURE 1. CA3252 QUAD NON-INVERTING POWER DRIVER SHOWN WITH TYPICAL APPLICATION LOADS
2
CA3252
VCC
CONSTANT
CURRENT
SOURCE
ENABLE
REFERENCE
VOLTAGE
1.2V
IN
11kΩ
TO SUBSEQUENT STAGES
FIGURE 2. SCHEMATIC OF ONE INPUT SECTION
+5V
0.001µF
12kΩ
27kΩ
VBATT
VCC
LOAD
V+
CA3252
OUT
IN
0.001µF
CLAMP
ENABLE
GND
GND
27V
FIGURE 3. TYPICAL LATCHED ON CIRCUIT SWITCHING CONFIGURATION. WHEN VIN IS SWITCHED LOW, THE OUTPUT IS
TURNED ON (LOW).
3
CA3252
Absolute Maximum Ratings
Thermal Information
Output Voltage, VCEX . . . . . . . . . . . . . . . . . . . . . . . . . -0.7 to 50VDC
Logic Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7V
Logic Input Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . .-0.7 to 15V
Output Sustaining Voltage, VCE(SUS) . . . . . . . . . . . . . . . . . . 35VDC
Output Current, IO (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 1ADC
Thermal Resistance (Typical, Note 2)
θJAoC/W
CA3252E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
45
CA3252M. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature Soldering (10s Max) . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 105oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. The Maximum Ambient Temperature is limited for the sustained conditions of the ICC(ON) Supply Current test with all Outputs ON. The total
DC current for the CA3252 with all 4 outputs ON should not exceed 0.7A at each output for a total of (4 X 0.7A + Max. ICC) ~ 2.9A. This
level of sustained current will significantly increase the on-chip temperature due to increased dissipation. Under any condition, the Absolute
Maximum Junction Temperature must not exceed150oC. While any one loaded output may exceed 0.7A, the maximum rating limit is 1A.
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
TA = -40oC to 105oC, VCC = VEN = 5V; Unless Otherwise Specified
PARAMETER
Output Sustaining Voltage
Output Leakage Current
Collector to Emitter Saturation Voltage
SYMBOL
VCE(SUS)
ICEX
VCE(SAT)
TEST CONDITIONS
MIN
MAX
UNITS
35
-
V
VCE = 50V, VIN = 2V, VEN = 0.8V
-
100
µA
IC = 100mA, VIN = 0.8V
-
0.3
V
IC = 300mA, VIN = 0.8V
-
0.5
V
IC = 600mA, VIN = 0.8V
-
0.8
V
-
0.8
V
IC = 100mA, VIN = 2V, VEN = 2V
Input Low Voltage
VIL
Input Low Current
IIL
VIN = 0.4V
-15
10
µA
Input High Voltage
VIH
IC = 600mA
2
-
V
Input High Current
IIH
IC = 600mA, VIN = 4.5V
-10
-10
µA
Logic Supply Current, All Outputs ON
ICC(ON)
IC = 600mA, All Outputs ON (Note 1)
-
90
mA
Logic Supply Current, All Outputs OFF
ICC(OFF)
All Outputs OFF
-
10
mA
Clamp Diode Leakage Current
IR
VR = 50V (Diode Reverse Voltage)
-
100
µA
Clamp Diode Forward Voltage
VF
IF = 0.6A
-
1.8
V
IF = 1.2A
-
2.0
V
0.9
-
A
Output Current
IOUT
VIN = 0.4V, VBATT = +13V,
Output Load = 10Ω
Turn-ON Propagation Delay Time
tPHL
IC = 600mA
-
10
µs
Turn-OFF Propagation Delay Time
tPLH
IC = 600mA
-
10
µs
Low Enable Voltage
VENL
-
0.8
V
Low Enable Current
IENL
-15
10
µA
High Enable Voltage
VENH
2.0
-
V
High Enable Current
IENH
-250
+250
µA
VEN = 0.4V
VEN ≥ 2V
4
CA3252
Dual-In-Line Plastic Packages (PDIP)
E16.3 (JEDEC MS-001-BB ISSUE D)
N
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
SYMBOL
-B-
A2
-C-
SEATING
PLANE
e
B1
D1
B
0.010 (0.25) M
A1
eC
C A B S
MAX
NOTES
-
0.210
-
5.33
4
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
0.204
0.355
-
D
0.735
0.775
18.66
D1
0.005
-
0.13
A
L
D1
MIN
A
E
D
MAX
A1
-ABASE
PLANE
MILLIMETERS
MIN
C
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
-
5
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
e
0.100 BSC
2.54 BSC
-
eA
0.300 BSC
7.62 BSC
6
eB
-
0.430
-
10.92
7
L
0.115
0.150
2.93
3.81
4
N
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
19.68
16
16
9
Rev. 0 12/93
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
5
CA3252
Small Outline Plastic Packages (SOIC)
M20.3 (JEDEC MS-013-AC ISSUE C)
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
N
INDEX
AREA
H
0.25(0.010) M
B M
INCHES
E
SYMBOL
-B1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
A1
B
0.25(0.010) M
C
0.10(0.004)
C A M
B S
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.4961
0.5118
12.60
13.00
3
E
0.2914
0.2992
7.40
7.60
4
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
α
NOTES:
MILLIMETERS
MAX
A1
e
α
MIN
20
0o
20
7
8o
Rev. 0 12/93
1. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusion and gate burrs shall not exceed
0.15mm (0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010
inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual
index feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice.
Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may
result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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