CXD2085M ID-1 Detection Description The CXD2085M is an IC which has the function of detecting ID-1 (EIAJ, CPX1204) from the video signal. Features • Can detect the ID-1 signal on the NTSC video signal. • Includes I2C bus interface. Also, IC can operate without the I2C bus. • Includes a 2-bit general-purpose I/O port function. (When using I2C bus) 16 pin SOP (Plastic) Absolute Maximum Ratings • Supply voltage VDD VSS – 0.5 to +7.0 • Input voltage VI VSS – 0.5 to VDD + 0.5 • Output voltage VO VSS – 0.5 to VDD + 0.5 • Storage temperature Tstg –55 to +150 Applications TVs Structure Silicon gate CMOS IC V V V °C Recommended Operating Conditions • Supply voltage VDD 4.75 to 5.25 • Operating temperature Topr Block Diagram VDIN 7 Slicer VSIN 6 Sync separator –20 to +70 V °C 16 O169 ID-1 decoder 15 OLBX 9 SCL I 2C bus interface 10 SDA 13 12 XI XO Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E98511-PS CXD2085M Pin Description Pin No. Symbol I/O Input level Description 1 XRST I 2 TST I TTL∗1, ∗4 TTL∗2 3 MCON I CMOS 4 ISET I ANALOG 5 AVDD 6 VSIN I ANALOG Sync separation input. 7 VDIN I ANALOG Data slicer input. 8 AVSS 9 SCL I 10 SDA I/O 11 VDD 12 XO O 13 XI I 14 VSS 15 OLBX I/O TTL Letter-box bit output when ID detection result is output. Or, general-purpose I/O port by the I2C bus setting. 16 O169 I/O TTL Full-mode bit output when ID detection result is output. Or, general-purpose I/O port by the I2C bus setting. ∗1 Schmitt input Reset at "0". Test input; connect to Vss. Switching between use and no use of I2C bus; No I2C bus when Low. Bias current setting. Analog power supply. Analog GND. CMOS∗1 I2C bus clock. CMOS∗1, ∗3 I2C bus data. Digital power supply. Oscillator connection. (14.318MHz) CMOS Oscillator connection, or clock input. Digital GND. ∗2 With pull-down resistor ∗3 Open drain ∗4 With pull-up resistor Connect SCL (Pin 9) to Vss in no I2C bus mode with MCON (Pin 3) to Low. Connect SDA (Pin 10) to Vss or VDD in no I2C bus mode. –2– CXD2085M Electrical Characteristics DC Characteristics (Logic section) Item Symbol Output voltage Output voltage Output voltage Input voltage (VDD = 5.0V ± 5%, VSS = 0V, Ta = 25°C) Conditions Min. Typ. Max. VDD – 0.8 VOH IOH = –2mA V VOL IOL = 4mA VOH IOH = –3mA VOL IOL = 3mA VDD/2 V VOL IOL = 3mA 0.4 V 0.4 VIH V 2.0 V 0.8 VIH V 0.8 V 0.7 × VDD VIH V 0.3 × VDD VIL Input voltage V 2.2 VIL Input voltage V VDD/2 VIL Input voltage Unit 0.8 × VDD VIH V V 0.2 × VDD VIL V Remarks Pins 15, 16 Pin 12 Pin 10 Pins 15, 16 Pins 1, 2 Pins 3, 13 Pins 9, 10 0.6 V Pins 9, 10 0.4 V Pin 1 Input hysteresis width Vhys Input leak current Ii VIN = Vss or VDD –10 +10 µA Pins 3, 9 Output leak current IOZ VIN = Vss or VDD –40 +40 µA Pins 10, 15, 16 Input current Ii VIN = VSS –40 –100 –240 µA Pin 1 Input current Ii VIN = VDD 40 100 240 µA Pin 2 Feedback resistance Rfbk XI (Pin 13) = Vss or VDD 250k 1M 2.5M Ω Current consumption IDD Clock frequency: 14.318MHz 9 AC Characteristics Item Clock frequency Between Pins 12 and 13 mA Sum of Pins 5 and 11 (VDD = 5.0V ± 5%, VSS = 0V, Ta = 25°C) Symbol Conditions Min. fxi Typ. Max. Unit Remarks Pin 13 input, or MHz oscillator between Pins 12 and 13 14.318 I/O Pin Capacitance Item Symbol Conditions Min. Typ. Max. Unit Input pin capacitance CIN VDD = VI = 0V, f = 1MHz 9 pF Output pin capacitance COUT VDD = VI = 0V, f = 1MHz 11 pF I/O pin capacitance CI/O VDD = VI = 0V, f = 1MHz 11 pF –3– Remarks CXD2085M Pin and Electrical Characteristics Analog Section Pin No. (VDD = 5.0V ± 5%, Vss = 0V, Ta = 25°C) Symbol Equivalent circuit Description 5 AVDD Not connected to VDD (Pin 11) in the IC. Analog power supply. Connect a low-noise power supply from the digital system. 8 AVSS Not connected to Vss (Pin 14) in the IC. Analog ground. Connect to the same potential as Vss. AVDD Bias setting. 4 4 ISET Connect to AVDD (Pin 5) with 33kΩ. AVSS Sync tip clamp, sync separation input. Input with the capacitance coupled. AVDD 6 6 VSIN Clamp voltage 1.5V AVSS Pedestal clamp, ID signal data slice input. Input with the capacitance coupled. AVDD 7 VDIN 7 Clamp voltage 1.5V AVSS –4– CXD2085M 1. Description of ID-1 (transmission system of additional video information, aspect ratio identification) As shown in the table below, the additional video information consists of 14-bits data, and a 6-bit CRCC is added to the data to form 20-bit data in total. This is carried on lines 20 and 283 in the vertical blanking area of the NTSC video signal. Table 1. Description of ID-1 signal Bit No. Description "1" "0" 4:3 Normal — Full-mode (16:9) Letter-box — A 1 2 3 Transmission aspect ratio Screen display format Not defined B 4 5 6 Identification information relating to the video signals and other signals (audio signals, etc.) transmitted simultaneously with the video signals WORD0 4bits 4bits WORD1 WORD2 Identification signal dependent on WORD0 Identification signal and other information dependent on WORD0 (From the Provisional standard of EIAJ, CPX-1204) In the CXD2085M, the above 14-bit data are obtained in the I2C bus for I2C bus mode. Also, first two bits only can be output to OLBX (Pin 15) and O169 (Pin 16) set as the direct output pins. 2. Difference between ID-1 Data from the I2C Bus and Direct Output Pin 2 ID-1 decoding Data validity determination 14 I2C Direct pin outputs OLBX, O169 To microcomputer VBVLD CXD2085M As shown in the figure above, the data validity determination which detects that the valid ID signal is exist or not, and the decoded result are obtained independently during ID-1 decoding. These two results are output to the direct output pins after taking their logical AND. Processing inside the microcomputer which has acquired the information from the I2C bus is performed either by simply outputting this data directly to the pins or by taking the logical AND as above. In addition, performing the processing when the data validity determination (VBVLD) is "1" and the decoding results bits 1 and 2 are "0" allows the video to be identified as 4:3 video. 3. General-Purpose I/O Port Function In I2C bus mode, the CXD2085M can use two pins OLBX (Pin 15) and O169 (Pin 16) as the general-purpose I/O ports. The three types of setting are available; both two pins for inputs, for outputs, and one for input and another for output. While resetting by XRST (Pin 1) in I2C bus mode, two pins are set as the general-purpose input ports. Perform the power-on reset by XRST when there is a possibility that the IC external circuit and the OLBX and O169 signals could collide. Be sure to set the OLBX and O169 pins as the output pins when they are not used. –5– CXD2085M 4. Clock The CXD2085M requires a 4fsc clock (14.318MHz). When using a crystal oscillator, connect it between XI (Pin 13) and XO (Pin 12). When inputting the clock from an external source, input it to XI (Pin 13). 5. Various Settings and Data I/O The various settings and data I/O can be made by using the pin directly or using I2C bus interface. 5-1. I2C bus By setting MCON (Pin 3) to High, the various settings and data extraction can be made with the I2C bus. The CXD2085M supports the I2C bus slave RECEIVER and slave TRANSMITTER modes. The slave address is 40 (H). In addition to standard mode (max. 100K bits/s), this IC also supports high-speed mode (max. 400K bits/s). Even when the power supply falls to 0V, it does not occupy the I2C bus. However, the absolute maximum ratings should not be exceeded. The I2C bus transmission process is shown in the figure below. The number of transmission data is one byte for write (RECEIVER) and two bytes for read (TRANSMITTER). There is no sub-address setting function. Note that the I2C bus transmission cannot be performed during resetting by the XRST pin (Pin 1). Data write (RECEIVER mode) 7654321 0 1 76543210 1 SLAm Wm As DATAm As Sm P Data read (TRANSMITTER mode) 7654321 0 1 76543210 1 SLAm Rm As DATAs Am Sm from Master to Slave ∗s from Slave to Master S Start Condition P Stop Condition SLA Slave Address Data W 0: Write Master → Slave R 1: Read Slave → Master A Clock pulse for Acknowledgment (SDA: L) XA 1 DATAs XAm Description Symbol ∗m DATA 76543210 Acknowledgment none (SDA: H) –6– P CXD2085M Table 2. List of I2C bus controls R/W Bit Symbol Description bit7 MSB POLBX Output value when the OLBX pin used as the general-purpose output port. bit6 PO169 Output value when the O169 pin used as the general-purpose output port. Settings whether the OLBX and O169 pins are used as the direct output pin of decoding result or as the general-purpose I/O port. bit5 PORT2 PORT2 0 0 1 1 PORT1 0 1 0 1 1st byte WR 1st byte General-purpose I/O port bit4 Direct output O169 pin function Direct output PORT1 Output Input Input General-purpose I/O port Output Output Input bit3 TST Test signal. Be sure to set to Low. bit2 XJGLK Normally set to Low. When Low, the decoding result is held during the VCR variable-speed playback for home use. When High, it is not held. bit1 LNJ1 Normally set to Low. When Low, the ID signal can be detected not only for the line where it should locate but for one line before and after it. When High, decoding is performed only to the line where the ID signal should locate. bit0 LSB RES Normally set to Low. When High, the decoding function is reset. Reset immediately after switching the input signal such as for TV channels. bit7 MSB ID5 ID decoding result 5th bit. bit6 ID4 ID decoding result 4th bit. bit5 ID3 ID decoding result 3rd bit. bit4 ID1 ID decoding result 1st bit. bit3 ID2 ID decoding result 2nd bit. bit2 VBVLD High when the valid ID signal is detected. bit1 IOLBX Input value when OLBX is used as the general-purpose input port. bit0 LSB IO169 Input value when O169 is used as the general-purpose input port. ID decoding result 14th bit when O169 is used as the general-purpose output port or as the direct output. bit7 MSB ID13 ID decoding result 13th bit. bit6 ID12 ID decoding result 12th bit. bit5 ID11 ID decoding result 11th bit. bit4 ID10 ID decoding result 10th bit. bit3 ID9 ID decoding result 9th bit. bit2 ID8 ID decoding result 8th bit. bit1 ID7 ID decoding result 7th bit. bit0 LSB ID6 ID decoding result 6th bit. RD 2nd byte OLBX pin function –7– CXD2085M 5-2. No bus mode No bus mode is established when setting the MCON pin (Pin 3) to Low and then the CXD2085M can be operates without using the I2C bus. In this case, the contents to be set by the I2C bus is fixed as shown below. OLBX and O169 obtain the decoding results as they become the direct output pins. Table 3. Settings in No Bus Mode (Pin 3, MCON = Low) WR Bit 1st byte R/W Symbol Contents bit7 MSB POLBX bit6 PO169 bit5 PORT2 bit4 PORT1 PORT1 and PROT2 fixed to Low. The OLBX and O169 pins are the direct output pins of the ID decoding result. bit3 TST SCL (Pin 9) input reflected as it is. Therefore, connect the SCL pin to Vss in no I2C bus mode. bit2 XJGLK bit1 LNJ1 SCL (Pin 9) input reflected as it is. Fixed to Low as the SCL pin is surely connected to Vss. RES Fixed to Low. When resetting is required, use the XRST pin (Pin 1). bit0 LSB Fixed to Low. In no I2C bus mode, there is no general-purpose I/O port function and this bit's operation is not affected. –8– CXD2085M For 2Vp-p input amplitude, using the I2C bus Application Circuit VDD = 5.0V ± 5% ≈ 16mA 5 11 AVDD VDD 2.2k 8 XRST 1 MCON 3 AVSS 33k SDA 10 4 ISET I2C SCL 9 10k ∗1 OLBX 15 CXD2085M 2.2k 1µ 100 10k O169 16 10 6 VSIN 1000p 47µ TST 2 Vin VSS 14 0.1µ 22p 100 7 VDIN XO 12 14.3MHz 10k 4.7k XI 13 470 22p ∗1 When OLBX (Pin 15) and O169 (Pin 16) are not used, connect the pull-down or pull-up resistor to these pins. 100 IRE 2.0Vp-p 0 IRE –40 IRE Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. –9– CXD2085M For 1Vp-p input amplitude not using the I2C bus Application Circuit VDD = 5.0V ± 5% ≈ 16mA 5 11 AVDD VDD 2.2k 8 XRST 1 MCON 3 AVSS 33k SDA 10 4 ISET SCL 9 OLBX 15 CXD2085M 1µ 100 O169 16 Decoding result output 10 6 VSIN 1000p 47µ TST 2 Vin VSS 14 0.1µ 22p 100 7 VDIN XO 12 14.3MHz 10k 4.7k XI 13 470 22p 100 IRE 1.0Vp-p 0 IRE –40 IRE Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. – 10 – CXD2085M Package Outline Unit: mm 16PIN SOP (PLASTIC) + 0.4 1.85 – 0.15 + 0.4 9.9 – 0.1 16 9 6.9 + 0.2 0.1 – 0.05 8 + 0.1 0.2 – 0.05 1.27 0.45 ± 0.1 0.5 ± 0.2 1 7.9 ± 0.4 + 0.3 5.3 – 0.1 0.15 0.24 M PACKAGE STRUCTURE SONY CODE SOP-16P-L01 EIAJ CODE SOP016-P-0300 PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL COPPER ALLOY PACKAGE MASS 0.2g JEDEC CODE – 11 –