CXD2500BQ CD Digital Signal Processor Description The CXD2500BQ is a digital signal processing LSI designed for use in compact disc players. It has the following functions: 80 pin QFP (Plastic) • Wide-frame jitter margin (±28 frames) realized by a built-in 32K RAM. • Bit clock generated by digital PLL for strobing EFM signals. Capture range of ±150 kHz and over. • EFM data demodulation • Enhanced protection of EFM Frame Sync signals • Powerful error correction based on Refined Super Strategy Error correction C1: Double correction C2: Quadruple correction • Double-speed playback and vari-pitch playback • Reduced noise generation at track jump • Auto zero-cross muting • Subcode demodulation and subcode Q data error detection • Digital spindle servo system (incorporating an oversampling filter) • 16-bit traverse counter • Built-in asymmetry correction circuit • CPU interface using a serial bus • Servo auto sequencer • Output for digital audio interface • Built-in digital level meter and peak meter • Bilingual Features • All digital signals for regeneration are processed using one chip. • The built-in RAM enables high-integration mounting. Structure Silicon-gate CMOS IC Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. —1— E91Y46F64-TE CXD2500BQ Absolute Maximum Ratings (Ta=25 °C) • Supply voltage VCC • Input voltage VI • Output voltage VO • Operating temperature Topr • Storage temperature Tstg • Supply voltage differences VSS–AVSS VDD–AVDD Recommended Operating Conditions • Supply voltage VDD • Operating temperature Topr • Input voltage VIN –0.3 to +7.0 –0.3 to +7.0 –0.3 to +7.0 –20 to +75 –40 to +125 –0.3 to +0.3 –0.3 to +0.3 V V V °C °C V V 4.75∗1 to 5.25∗3 (5.0 V typ.) –20 to +75 VSS–0.3 to + VDD + 0.3 V °C V ∗1 VDD value of 4.75 V (min.) is for the double-speed playback mode at vari-pitch control reset. For the low power consumption special playback mode, VDD value is 3.6 V (min.). ∗2 In the normal-speed playback mode VDD value is 4.5 V (min.) ∗2 Low power consumption, special playback mode Set the internal operation of LSI at the double-speed mode, and half the crystal oscillation frequency. This will result in the normal-speed playback mode. ∗3 VDD value of 5.25 V (max.) is for the double-speed playback mode at vari-pitch control reset. For normalspeed playback and the low power consumption special playback mode, the VDD value is 5.5 V (max.). I/O Capacity • Input pins CI 12 pF max. • Output pins CO 12 pF max. at high impedance Note: Test Conditions VDD=VI=0 V fM=1 MHz —2— CXD2500BQ VCKI VPCO 53 XTAO XTAI 56 XTSL FSTT Block Diagram 54 53 17 19 C4M 57 23 AVDD Clock generator C16M 58 21 AVSS 32K RAM PDO 11 Digital PLL vari-pitch double speed 8 EFM demodulator 12 VSS Address generator PCO 20 FIL1 19 Priority encoder 8 FIL0 18 Sync Protector CLTV 22 D/A data processor RF 24 ASY1 26 52 VSS Serial/Parallel processor VCO0 73 VDD 9 Register VCO1 33 VDD ∗ 30 PSSL 49 DAO 1 to 6 MUX 68 MUTE ASY0 27 ASYE 28 Timing Generator WFCK 62 Peak detector SCOR 63 EXCK 65 Digital out Subcode P-W Processor SBSO 64 60 DOUT 59 MD 2 EMPH 61 71 DATA SQCK 67 SQSO 66 MON Error corrector Subcode Q Processor 74 CLOK CPU interface 72 XLAT 3 FSW 2 MDP 4 CLV processor MDS 43 Noise shaper TEST 10 77 DATO Servo auto sequencer Timing Generator 2 79 CLKO 78 XLTO 18-times over samplling filter NC ∗Asymmetry correction. 32 31 75 69 76 80 1 WDCK SEIN MIRR CNIN FOX —3— SENS 51 LRCK LOCK 50 APTL 6 APTR 70 XRST 5 CXD2500BQ DA08 DA09 45 44 43 42 41 DA07 46 DA06 DA04 48 47 DA05 DA03 50 49 DA02 52 51 DA01 VSS 53 APTR XTAI 55 54 APLL XTAQ 57 56 XTSL 59 58 FSTT MD2 60 C4M DOUT 62 61 C16M EMPH 64 63 WFCK SCOR SBSO Pin Configuration EXCK 65 40 DA10 SQSO 66 39 DA11 SQCK 67 38 DA12 MUTE 68 37 DA13 SENS 69 36 DA14 XRST 70 35 DA15 DATA 71 34 DA16 XLAT 72 33 VDD D2500B 77 28 ASYE XLTO 78 27 ASYO CLKO 79 26 ASYI MIRR 80 25 BIAS 10 11 12 13 14 15 16 —4— 17 18 19 20 21 22 23 24 CLTV 9 AVSS 8 PCO 7 FILI 6 FILO 5 VCKI 4 VPCO 3 NC 2 PDO 1 RF DATO AVDD NC NC 29 NC 76 VSS CNIN TEST PSSL VCOI 30 VCOO 75 NC SEIN LOCK WDCK MDS CLOK 31 MDP LRCK 74 MON 32 FSW 73 FOK VDD CXD2500BQ Pin Description Pin No. 1 2 3 4 5 Symbol I/O Description FOK FSW MON MDP MDS I O O O O Z, 0 1, 0 1, Z, 0 1, Z, 0 6 LOCK O 1, 0 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 NC VCOO VCOI TEST PDO VSS NC NC NC VPCO VCKI FILO FILI PCO AVSS CLTV AVDD RF BIAS ASYI ASYO ASYE NC 30 PSSL I 31 32 33 WDCK LRCK VDD O O 34 DA16 O 35 DA15 O 36 DA14 O 37 38 39 40 DA13 DA12 DA11 DA10 O O O O Focus OK input. Used for SENS output and servo auto sequencer. Output used to switch the spindle motor output filter. Output for spindle motor ON/OFF control Output for spindle motor servo control Output for spindle motor servo control Output is “H” when the GFS signal sampled at 460 Hz is “H”. Output is “L” when the GFS signal is “L” 8 or more times in succession. — O I I O 1, 0 1, Z, 0 Output of oscillation circuit for analog EFM PLL Input to oscillation circuit for analog EFM PLL fLOCK=8.6436 MHz Test. Normally at 0 V (GND). Output of charge pump for analog EFM PLL GND — — — O I O I O I I I I O I 1, Z, 0 Output of charge pump for vari-pitch PLL Clock input from external VCO for vari-pitch control. fc center=16.9344 MHz. Analog Output of filter for master PLL (Slave=Digital PLL) Input to filter for master PLL 1, Z, 0 Output of charge pump for master PLL Analog GND VCO control voltage input for master PLL Analog power supply (+5 V) EFM signal input Asymmetry circuit constant current input Asymmetry comparator circuit voltage input 1, 0 EFM full-swing output Asymmetry circuit OFF at “L”. Asymmetry circuit ON at “H”. — Input used to switch the audio data output mode. “L” for serial output, “H” for parallel output. 1, 0 D/A interface for 48-bit slot. Word clock f=2Fs 1, 0 D/A interface for 48-bit slot. LR clock f=Fs Power supply (+5 V) Outputs DA16 (MSB) when PSSL=1, or serial data from the 48-bit slot 1, 0 (2’s complements, MSB first) when PSSL=0. 1, 0 Outputs DA15 when PSSL=1, or bit clock from the 48-bit slot when PSSL=0. Outputs DA14 when PSSL=1, or serial data from the 64-bit slot (2’s 1, 0 complements, LSB first) when PSSL=0. 1, 0 Outputs DA13 when PSSL=1, or bit clock from the 64-bit slot when PSSL=0. 1, 0 Outputs DA12 when PSSL=1, or LR clock from the 64-bit slot when PSSL=0. 1, 0 Outputs DA11 when PSSL=1, or GTOP when PSSL=0. 1, 0 Outputs DA10 when PSSL=1, or XUGF when PSSL=0. —5— CXD2500BQ Pin No. Symbol I/O 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 DA09 DA08 DA07 DA06 DA05 DA04 DA03 DA02 DA01 APTR APTL VSS XTAI XTAO XTSL O O O O O O O O O O O 56 FSTT O 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 C4M C16M MD2 DOUT EMPH WFCK SCOR SBSO EXCK SQSO SQCK MUTE SENS XRST DATA XLAT VDD CLOCK SEIN CNIN DATO XLTO CLKO O O I O O O O O I O I I — I I I 80 MIRR I I O I I I I O O O Description 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 1, 0 Outputs DA9 when PSSL=1, or XPLCK when PSSL=0. Outputs DA8 when PSSL=1, or GFS when PSSL=0. Outputs DA7 when PSSL=1, or RFCK when PSSL=0. Outputs DA6 when PSSL=1, or C2PO when PSSL=0. Outputs DA5 when PSSL=1, or XRAOF when PSSL=0. Outputs DA4 when PSSL=1, or MNT3 when PSSL=0. Outputs DA3 when PSSL=1, or MNT2 when PSSL=0. Outputs DA2 when PSSL=1, or MNT1 when PSSL=0. Outputs DA1 when PSSL=1, or MNT0 when PSSL=0. Control output for aperture correction. “H” for R-ch. Control output for aperture correction. “H” for L-ch. GND Input for 16.9344 MHz and 33.8688 MHz X'tal oscillation circuit. 1, 0 Output for 16.9344 MHz X'tal oscillation circuit. X'tal selection input. “L” for 16.9344 MHz X'tal, “H” for 33.8688 MHz X'tal. 2/3 frequency demultiplication output for Pins 53 and 54. Unaffected by 1, 0 vari-pitch control. 1, 0 4.2336 MHz output. Subject to vari-pitch control. 1, 0 16.9344 MHz output. Subject to vari-pitch control. Digital-Out ON/OFF control. “H” for ON, “L” for OFF. 1, 0 Digital-Out output. 1, 0 “H” for playback disc provided with emphasis, “L” for without emphasis. 1, 0 WFCK (Write Frame Clock) output. 1, 0 “H” when subcode Sync S0 or S1 is detected. 1, 0 Serial output of Sub P to W Clock input for reading SBSO 1, 0 Outputs 80-bit Sub Q and 16-bit PCM peak-level data. Clock input for reading SQSO “H” for muting, “L” for release. 1, Z, 0 SENS output to CPU System reset. “L” for resetting. Inputs serial data from CPU. Latches serial data input from CPU at falling edge. Power supply (+5 V) Inputs serial data transfer clock from CPU. Inputs SENSE from SSP. Inputs track jump count signal. 1, 0 Outputs serial data to SSP. 1, 0 Latches serial data output to SSP at falling edge. 1, 0 Outputs serial data transfer clock to SSP. Inputs mirror signal to be used by auto sequencer when jumping 16 or more tracks. —6— CXD2500BQ Note: • The data at the 64-bit slot is output in 2’s complements on an LSB-first basis. The data at the 48-bit slot is output in 2’s complements on an MSB-first basis. • GTOP monitors the state of Frame Sync protection. (“H”: Sync protection window released) • XUFG is a negative Frame Sync pulse obtained from the EFM signal before Frame Sync protection is effected.. • XPLCK is an inversion of the EFM PLL clock. The PLL is designed so that the falling edge of XPLCK coincides with a change point of the EFM signal. • The GFS signal turns “H” upon coincidence between Frame Sync and the timing of interpolation protection. • RFCK is a signal generated at 136-µs periods using a crystal oscillator. • C2PO is a signal to indicate data error. • XRAOF is a signal issued when a jitter margin of ±28F is exceeded by the 32K RAM. —7— CXD2500BQ Item Input voltage. “H” level Input voltage “L” level. Input voltage “H” level Input voltage “L” level Input voltage Output voltage (3) Output voltage “H” level Output voltage “L” level Output voltage “H” level Output voltage “L” level Output voltage “L” level Output voltage (4) Output voltage (2) Output voltage (1) Input voltage (3) Input voltage (2) Input voltage (1) Electrical Character DC characteristics Output voltage “H” level Output voltage “L” level (VDD=AVDD=5.0 V±5 %, VSS=AVSS=0 V, Topr=–20 to +75°C) Condition Min. Typ. Max. 0.7VDD VIH (1) Unit Related pins V ∗1 VIL (1) VIN (2) VIN (2) VIN (3) 0.3VDD Schmitt circuit input 0.8VDD V ∗2 0.2VDD V VSS VDD V VDD–0.5 VDD V Analog input VOH (1) IOH=–1 mA V ∗3 ∗4 VOL (1) IOL=1 mA VOH (2) IOH=–1 mA 0 0.4 V VDD–0.5 VDD V ∗5 VOL (2) IOL=2 mA 0 0.4 V VOL (3) IOL=2 mA 0 0.4 V VDD–0.5 VDD V VOH (4) IOH=–0.28 mA ∗6 ∗7 VOL (4) IOL=0.36 mA 0 0.4 V Input leak current ILI VI=0 to 5.25 V ±5 µA ∗1, ∗2, ∗3 Tristate pin output leak current ILO VO=0 to 5.25 V ±5 µA ∗8 Related pins ∗1 XTSL, DATA, XLAT, MD2, PSSL ∗2 CLOK, XRST, EXCK, SQCK, MUTE, FOK, SEIN, CNIN, MIRR, VCKI, ASYE ∗3 CLTV, FILI, RF ∗4 MDP, PDO, PCO, VPCO ∗5 ASYO, DOUT, FSTT, C4M, C16M, SBSO, SQSO, SCOR, EMPH, MON, LOCK, WDCK, DATO, CLKO, XLTO, SENS, MDS, DA01 to DA16, APTR, APTL, LRCK, WFCK ∗6 FSW ∗7 FILO ∗8 SENS, MDS, MDP, FSW, PDO, PCO, VPCO —8— CXD2500BQ AC Characteristics (1) XTAI and VCOI pins 1) During self-oscillation (Topr=–20 to +75 °C, VDD=AVDD=5.0 V±5 %) Item Oscillation frequency Symbol fMAX 2) With pulses input to XTAI and VCOI pins Item Symbol Min. 7 Typ. Max. 34 Unit MHz (Topr=–20 to +75 °C, VDD=AVDD=5.0 V±5 %) Typ. Max. Unit Min. “H” level pulse width tWHX 13 500 “L” level pulse width tWLX 13 500 Pulse period tCX 26 1,000 Input “H” level VIHX VDD–1.0 ns V Input “L” level VILX 0.8 Rising time Falling time tR, tF 10 ns tCX tWHX tWLX VIHX VIHX×0.9 VDD/2 XTAI VIHX×0.1 VILX tR tF 3) With sine waves input to XTAI and VCOI pins via capacitor (Topr=–20 to +75 °C, VDD=AVDD=5.0 V±5 %) Item Input amplitude Symbol V1 —9— Min. 2.0 Typ. Max. VDD+0.3 Unit Vp-p CXD2500BQ (1) CLOK, DATA, XLAT, CNIN, SQCK, and EXCK pins (VDD=AVDD=5.0 V±5 %, VSS=AVSS=0 V, Topr=–20 to +75 °C Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width EXCK, CNIN, SQCK frequency EXCK, CNIN, SQCK pulse width Symbol fCK tWCK tSU tH tD tWL fT tWT Min. Typ. Max. 0.65 750 300 300 300 750 Unit MHz ns 1 MHz ns 300 1/fCK tWCK tWCK CLOK DATA XLAT tSU tH tD EXCK CNIN SQCK tWT tWL tWT 1/fT SUBQ SQCK tSU tH Description of Functions §1 CPU Interface and Commands • CPU interface This interface is used to set various modes using DATA, CLOK, and XLAT. The interface timing chart is shown below. 750ns or more CLOK DATA D1 D2 Data D3 D0 D1 D2 D3 Address 750ns or more XLAT Registers 4 to E Valid 300ns max • The command addresses of the CXD2500B and the data capable of being set are shown in Table 1-1. • When XRST is set to 0, the CXD2500B is reset, causing its internal registers to be initialized to the values listed in Table 1-2. —10— —11— Servo factor setting CLV CRTL CLV mode D E counter setting Traverse monitor C B Audio CTRL Func specification 9 A MODE specification jump (N) setting Auto sequencer track KICK (D) Brake (B) Blind (A, E), Overflow (C) 8 7 6 5 1 1 1 1 1 1 1 0 0 0 0 4 Auto sequence D3 Command name Register Commands 1 1 1 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 D1 Address D2 0 1 0 1 0 1 0 1 0 1 0 D0 D1 AS0 D0 DSPB D CLV A SEQ Mute-F D OUT 8,192 2.9 ms D PLL WSEL 4,096 1.45 ms 0.09 ms 0.045 ms CM3 PWM MD DCLV MDP1 Gain 32,768 UP Vari CM2 TB MDP0 Gain 16,384 Down Vari CM1 TP MDS1 Gain 8,192 Mute Table 1-1 CM0 Gain CLVS MDS0 Gain 4,096 ATT ON-OFF ON-OFF ON-OFF ON-OFF 0 16,384 5.8 ms 0.18 ms 0.09 ms 0.045 ms 0.022 ms AS1 Data 1 AS2 D2 CDROM 32,768 11.6 ms 0.36 ms 0.18 ms AS3 D3 — — — 2,048 PCT1 MAIN BiliGL — 2,048 — — — D3 — — — 1,024 PCT2 SUB BiliGL — — — — D1 — — — 512 — FLFC — 512 Data 2 1,024 — — — D2 — — — 256 — — — 256 — — — D0 — — — 128 — — — 128 — — — D3 — — — 64 — — — 64 — — — — — — 32 — — — 32 — — — D1 Data 3 D2 — — — 16 — — — 16 — — — D0 — — — 8 — — — 8 — — — D3 — — — 4 — — — 4 — — — — — — 2 — — — 2 — — — D1 Data 4 D2 — — — 1 — — — 1 — — — D0 CXD2500BQ —12— Servo factor setting CLV CRTL CLV mode D E counter setting Traverse monitor C B Audio CTRL Func specification 9 A MODE specification track jump setting Auto sequencer KICK (D) Brake (B) Blind (A, E), Overflow (C) Auto sequence Command 8 7 6 5 4 name Register Reset Initialization 1 1 1 1 1 1 1 0 0 0 0 D3 1 1 1 0 0 0 0 1 1 1 1 D2 1 0 0 1 1 0 0 1 1 0 0 D1 Address 0 1 0 1 0 1 0 1 0 1 0 D0 0 0 0 0 0 1 0 0 0 0 0 D3 0 0 1 0 0 0 0 0 1 1 0 D2 Data 1 0 0 1 0 1 0 0 0 1 0 0 D1 Table 1-2 0 0 0 0 1 1 0 0 1 1 0 D0 — — — 0 0 0 — 0 — — — D3 — — — 0 0 0 — 0 — — — D2 Data 2 — — — 0 — 0 — 0 — — — D1 — — — 1 — — — 1 — — — D0 — — — 0 — — — 0 — — — D3 — — — 0 — — — 0 — — — D2 — — — 0 — — — 0 — — — D1 Data 3 — — — 0 — — — 0 — — — D0 — — — 0 — — — 0 — — — D3 — — — 0 — — — 0 — — — D2 — — — 0 — — — 0 — — — D1 Data 3 — — — 0 — — — 0 — — — D0 CXD2500BQ CXD2500BQ §1 Meanings of Data Set at Command Addresses $4X Command Command CANCEL FOCUS-ON 1 TRACK JUMP 10 TRACK JUMP 2N TRACK JUMP M TRACK MOVE AS3 0 0 1 1 1 1 AS2 0 1 0 0 1 1 AS1 0 1 0 1 0 1 AS0 0 1 RXF RXF RXF RXF RXF=0 FORWARD RXF=1 REVERSE • If a Focus-ON command ($47) is canceled during execution, $02 is issued and the auto sequence operation is discontinued. • If a Track Jump or Track Move command ($48 to $4F) is canceled during execution, the auto sequence operation is discontinued. $5X Command Used to set timers for the auto sequencer. Timers set: A, E, C, and B Command Blind(A, E), Overflow(C) Brake(B) Example: D3 0.18 ms 0.36 ms D1 0.045 ms 0.09 ms D0 0.022 ms 0.045 ms D2 5.8 ms D1 2.9 ms D0 1.45 ms Data 3 D3 D2 D1 D0 Data 4 D3 D2 D1 D0 27 23 D2=D0=1, D3=D1=0 (Initial Reset) A=E=C=0.112 ms B=0.225 ms $6X Command Used to set a timer for the auto sequencer. Timer set: D Command D3 KICK (D) 11.6 ms Example: D2 0.09 ms 0.18 ms D3=0 D2=D1=D0=1 (Initial Reset) D=10.15ms $7X Command Used to set the number of auto sequencer track jumps/moves. Data3 Data 2 Command D3 D2 D1 D0 D3 D2 D1 D0 Auto sequencer track jump number setting 215 214 213 212 211 210 29 28 26 25 24 22 21 20 This command sets the value of “N” for 2N track jump and M track move execution using the auto sequencer. —13— CXD2500BQ • The maximum number of tracks that can be counted is 65,535. However, in the case of 2N track jumps, it is subject to mechanical restrictions due to the optical system. • When the number of tracks to be jumped is smaller that 15, the signals input from CNIN are counted. When it is 16 or larger, the signals input from the MIRR pin are counted. This count signal selection contributes toward improving the accuracy of high-speed track jumping. Command D3 D2 MODE specification CDROM 0 $8X Command Command C2PO timing CDROM=1 1-3 CDROM=0 1-3 Command bit D. out Mute F=1 D. out Mute F=0 D1 D. OUT Mute-F AS0 WSEL Processing CDROM mode is entered. In this mode, average value interpolation and preceding value holding are not performed. Audio mode is entered. In this mode, average value interpolation and preceding value holding are performed. Processing When Digital Out is ON (pin MD2=1), DA output is muted. Da output muting is unaffected by the setting of Digital Out. D/A Out D.out Mute with F=1 MD2=1 (D. out-ON) – ∞dB – ∞dB Mute-ON Mute-OFF Command bit WSEL=1 WSEL=0 MD2=0 (D. out-OFF) – ∞dB 0dB Sync protection window width Application ∗ ±26 channel clock pulses Anti-rolling is enhanced. ±6 channel clock pulses Sync window protection is enhanced. ∗ In normal-speed playback, the channel clock frequency is 4.3218 MHz. $9X Command Command Func specification Data 1 D3 DCLV ON-OFF D2 DSPB ON-OFF D1 A. SEQ ON-OFF —14— D0 D. PLL ON-OFF D3 BiliGL MAIN Data 2 D2 BiliGL Sub D1 FLFC CXD2500BQ Command bit CLV mode DCLV ON-OFF=0 DCLV ON-OFF=1 (FSW and MON are unnecessary) Contents FSW=L, MON-H, MDS-Z, MDP=servo control signal, with carrier In CLVS mode frequency of 230 Hz at TB=0 and 460 Hz at TB=1 FSW=Z, MON=H, MDS=speed control signal with carrier frequency of In CLVP mode 7.35 kHz, MDP=phase control signal with carrier frequency of 1.84 kHz MDS= PWM polarity signal. Carrier DCLV when frequency=132 kHz PWM, MD=1 MDS= PWM absolute value output (binary). In CLVS or Carrier frequency=132 kHz CLVP mode MDS= Z DCLV when MDP= ternay PWM output. PWM, MD=0 Carrier frequency=132 kHz In the Digital CLV servo mode with DCLV ON-OFF set to 1, the sampling frequency of the internal digital filter is switched at the same time as the switching between CLVP and CLVS. Therefore, for CLVS, the cut-off frequency fC is 70 Hz when TB is set to 0, and 140Hz when TB is set to 1. Command bit DSPB=0 DSPB=1 Processing Normal-speed playback. ECC quadruple error correction is made. Vari-pitch control is enabled. Double-speed playback. ECC double error correction is made. Vari-pitch control is disabled. Set FLFC at 1 when in double-speed playback mode (exclude the low power consumption special playback mode). However, FLFC can be set to 0 during PLL pull-in (lock). Set to 0 for all other modes. SENS Output Microcomputer serial register values (Latching unnecessary) $0X $1X $2X $3X $4X $5X $6X $AX $BX $CX $EX $7X, 8X, 9X, DX, FX ASEQ=0 ASEQ=1 Z Z Z Z Z Z Z GFS COMP COUT OV64 Z SEIN (FZC) SEIN (A, S) SEIN (T. Z. C) SEIN (SSTOP) XBUSY FOK SEIN (Z) GFS COMP COUT OV64 0 —15— CXD2500BQ Description of SENS signals SENS output Z SEIN XBUSY FOK GFS COMP COUT OV64 Command bit DPLL=0 DPLL=1 Command bit BiliGL SUB=0 BiliGL SUB=1 Meaning SENS is at High-Z state. SEIN signal, which was input to the CXD2500B, is output from SSP. “L” when auto sequencer is in operation; “H” when terminated. Output of the signal (normally FOK input from RF) input to the FOK pin. “H” when Focus OK is received. “H” when regenerated Frame Sync is obtained at the correct time. Used in counting the number of tracks set in register B. “H” when the count is latched to register B twice in succession. It is reset to “L” level when the count of CNIN inputs equals the originally set number for register B. Used in counting the number of tracks set in register B. “H” when the count is latched to register B, then to register C. It is toggled every time the count of CNIN inputs reaches the value set in register B. “L” when after passing through the sync detection filter, the EFM signal become longer than the 64 channel clocks. Meaning RFPLL enters analog mode. PDO, VCOI, and VCOO are used. RFPLL enters digital mode. PDO becomes Z. BiliGL MAIN=0 STEREO SUB BiliGL MAIN=1 MAIN Mute Definition of Bilingual MAIN, SUB, and STEREO MAIN; The input L-ch signal is output to both L-ch and R-ch. Sub: The input R-ch signal is output to both L-ch and R-ch. STEREO: The input L-ch and R-ch signals are output to both L-ch and R-ch respectively. —16— CXD2500BQ $AX Command Command Audio CTRL Data 1 D3 Vari UP D2 Vari DWN Data 2 D1 D0 D3 D2 Mute ATT PCT1 PCT2 Vari UP Vari DWN Pitch XTal 0% VCO 0% +0.1% +0.2% +0.3% +0.2% +0.1% +0% Command bit Meaning Mute=0 Muting is off unless condition to make muting occurs. Mute=1 Muting is on. Peak register reset. -0.1% -0.2% XTal 0% Command bit Meaning ATT=0 Attenuation is off. ATT=1 –12dB Condition for Muting (1) Mute=1 in register A (2) Pin Mute=1 (3) D.OUT Mute F=1 in register 8 with D.Out ON (MD2=1) (4) Elapse of over 35 msec after GFS turns “Low” (5) BiliGL MAIN=Sub=1 in register 9 (6) PCT1=1 and PCT2=2 in register A In the case of (1) to (4), zero-cross muting not exceeding 1 msec is performed. Command bit Meaning PCM Gain PCT1 PCT2 0 0 Normal mode ×0 dB 0 1 Level meter mode ×0 dB 1 0 Peak meter mode Mute 1 1 Normal mode ×0 dB ECC correction capacity C1: Double, C2: Quadruple C1: Double, C2: Quadruple C1: Double, C2: Double C1: Double, C2: Double Level Meter Mode (See Timing Chart 1-4.) • This mode makes the digital level meter function available. • Inputting 96-bit clock pulses to SQCK will enable 96 data to be output to SQSO. Of the output data, the first 80 bits comprise Sub-Q data, which transmit the description for the data format to the Sub Code interface. The last 16 bits are ordered LSB-first, of which the first 15 bits constitute PCM data (absolute value). The final 1 bit is “High” if the prior PCM data was generated at the left channel; “Low” if generated at the right channel. • The PCM data is reset once it is read, and the L/R flag is reversed. While this state is kept until the next read operation is started, testing for the maximum value is conducted. —17— CXD2500BQ Peak Meter Mode (See Timing Chart 1-5.) • In this mode, the maximum value of PCM data is detected whether the channel involved is L-ch or R-ch. To read the detected maximum value, it is necessary to input 96 clock pulses to SQCK. • When 96 clock pulses have been input to SQCK, 96 bits of data is output to SQSO. At the same time, the data is re-set in an internal register of the LSI. That is, the PCM peak detection register is not reset when it is read. • To reset the PCM peak register, set both PCT1 and PCT2 to 0. Or, Set $AX mute. • In this mode, the absolute time of Subcode Q is controlled automatical. • Namely, every time a peak value is detected, the absolute time when the CRC was passed is stored. The program time operation is performed in the normal way. • The last bit (L/R flag) of the 96-bit data stays 0. • In this mode, the preceding value holding and average value interpolation data are fixed to level (–∞). $CS Command Command Servo factor setting D3 Gain MDP1 D2 Gain MDP0 D1 Gain MDS1 CLV CTRL ($DX) D0 Gain MDS0 Gain CLVS Explanation Only DCLV=1 is effective. DCLV=1 and DCLV=0 are both effective. This command is used to externally set the spindle servo gain when DCLV=1. • Gain setting for CLVS mode: GCLVS Gain Gain Gain MDS1 MDS0 CLVS 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 GCLVS Note: –12dB –6dB –6dB 0dB 0dB +6dB When DCLV=0, the CLVS gain is determined as follows: If Gain CLVS=0, then GCLVS=–12 dB. If Gain CLVS=1, then GCLVS=0 dB • Gain setting for CLVP mode: GMDP, GMDS Gain MDP1 0 0 1 Gain MDP0 0 1 0 GMDP –6 dB 0 dB + 6dB Gain MDS1 0 0 1 —18— Gain MDS0 0 1 0 GMDS –6dB 0dB +6dB CXD2500BQ $DC Command Command D3 D2 CLV CTRL DCLV PWM MD TB D1 TP D0 CLVS Gain See “$CX Command.” Command bit DCLV PWM MD=1 DCLV PWM MD=0 Command bit TB=0 TB=1 TP=0 TP=1 Description (See Timing Chart 1-6.) Specification of PWM mode for digital CLV. Both MDS and MDP are used. Specification of PWM mode for digital CLV. Ternary MDP values are output. Description In CLVS or CLVH mode, bottom value is held at periods of RFCK/32. In CLVS or CLVH mode, bottom value is held at periods of RFCK/16. In CLVS mode, peak value is held at periods of RFCK/4. In CLVS mode, peak value is held at periods of RFCK/2. In CLVH mode, peak holding is made at 34 kHz. $EX Command Command CLV mode CM3 0 1 1 1 1 1 0 STOP: KICK: BRAKE: CLVS: CLVP: CLVA: CM2 0 0 0 1 1 1 1 D3 CM3 D2 CM2 D1 CM1 CM1 0 0 1 1 0 1 1 CM0 0 0 0 0 0 1 0 Mode STOP KICK BRAKE CLVS CLVH CLVP CLVA D0 CM0 Explanation See Timing Chart 1-7. See Timing Chart 1-8. See Timing Chart 1-9. Spindle motor stop mode Spindle motor forward run mode Spindle motor reverse run mode Rough servo mode for use for pulling disc run into RF-PLL capture range when the RF-PLL circuit lock has been disengaged PLL servo mode Automatic switching mode for CLVS and CLVS. This mode is used during normal play status. —19— —20— C2PO CDROM=1 C2PO CDROM=0 WDCK LRCK Timing Chart 1-3 C2 Pointer for Lower 8bit Rch C2 pointer C2 Pointer for upper 8bit Rch 16bit C2 Pointer C2 Pointer for Lower 8bit Lch C2 pointer C2 Pointer for upper 8bit Lch 16bit C2 Pointer If C2 pointer=1, data is NG 48bit Slot CXD2500BQ —21— SQSO SQCK WFCK SQSO SQCK CRCF Timing Chart 1-4 1 1 2 3 80 81 CRCF D0 D2 1 16 bit 96 clock pulses D1 Level Meter Timing Peak data of this section Sub-Q Data See "Sub Code interface" L/R 3 96 bit data Hold section 96 clock pulses 2 D4 D5 D6 2 R/L 3 CRCF 15-bit peak-data Absolute value display, LSB first D3 750ns to 120µs D13 D14 96 Peak data L/R flag L/R CXD2500BQ SQCK WFCK 96 clock pulses Measurement CRCF Timing Chart 1-5 1 2 3 Peak Meter Timing Measurement CRCF 96 clock pulses 1 2 3 Measurement CRCF CXD2500BQ —22— CXD2500BQ Timing Chart 1-6 DCLV PWM MD=0 MDS Z n·236 (nsec) n=0 to 31 Acceleration MDP Z 132KHz 7.6µSec Deceleration DCLV PWM MD=1 MDS Deceleration Acceleration MDP n·236 (nsec) n=0~31 7.6µSec Output Waveforms with DCLV=1 Timing Chart 1-7 STOP DCLV=0 MDS Z MDP L FSW L MON L DCLV=1 DCLV PWM MD=0 STOP MDS Z MDP Z DCLV=1 DCLV PWM MD=1 STOP MDS MDP L FSW and MON are the same as for DCLV=0 —23— CXD2500BQ Timing Chart 1-8 KICK DCLV=0 MDS Z MDP H FSW L MON H DCLV=1 DCLV PWM MD=0 KICK Z MDS MDP H Z 7.6µs FSW and MON are the same as for DCLV=0 DCLV=1 DCLV PWM MD=1 KICK MDS MDP H H L FSW and MON are the same as for DCLV=0 —24— CXD2500BQ Timing Chart 1-9 BRAKE DCLV=0 MDS Z MDP L FSW L MON H DCLV=1 DCLV PWM MD=0 BRAKE MDS MDP Z L Z FSW and MON are the same as for DCLV=0 DCLV=1 DCLV PWM MD=1 MDS MDP FSW and MON are the same as for DCLV=0 —25— CXD2500BQ §2 Subcode Interface In this section, the subcode interface will be explained. The contents of the subcode interface can be externally read in two ways. The subcodes P through W totaling 8 bits can be read from SBSO by inputting EXCK to the CXD2500B. Sub-Q can be read after conducting a CRC check on the 80bits of information in the subcode frame. First, check SCOR and CRCF, then input 80 clock pulses to SQCK and read the data. §2-1 P-W Subcode Read These subcodes can be read by entering EXCK immediately after the fall of WFCK. (See Timing Chart 2-1.) §2-2 80-bit Sub-Q Read Figure 2-2 shows a block diagram of the peripheral part of the 80-bit Sub-Q register. • The Sub Q regenerated on a bit-per-frame basis is input to the 80-bit serial/parallel register and the CRC circuit. • When the results of CRC of the 96-bit Sub-Q are OK, CRCF is set to 1 and the 96-bit data is output to SQSO. Furthermore, it is loaded into the 80-bit, parallel/serial register. If SQSO is “H” after the output of SCOR, it can be taken that CPU has been loaded a new set of CRCOK data. • When 80-bit data is loaded into CXD2500B, MSB and LSB are reversed within each byte of the data. Therefore, the bits are ordered LSB-first within each byte, even though the byte arrangement is kept unchanged. • When 80 bits of data are confirmed to have been loaded, SQCK is input to read the data. Subsequently in the CXD2500B, the input of SQCK is detected and the retriggerable monostable multivibrator is reset during Low. • The time constant of the retriggerable monostable multivibrator ranges from 270 to 400 µs. If the time of High for SQCK is less than this time constant, the monostable multivibrator will keep resetting, preventing the contents of the P/S register from being loaded into the P/S register. • While the monostable multivibrator is resetting, data loading into the peak detection parallel/serial register and 80-bit parallel/serial register is forbidden. Therefore, while data read operation is carried out at clock periods shorter than the time constant of the monostable multivibrator, the contents of these registers are retained without being rewritten by CRCOK, etc. • The CXD2500B permits the peak detection register to be connected to the shift-in of the 80-bit P/S register. For Ring Control 1, the input and output are short-circuited during peak meter and level meter mode. For Ring Control 2, the input and output are short-circuited during peak meter mode only. The Ring Controls are arranged in this way in order for the registers to be reset each time their contents are read in the level meter mode, while preventing destructive read in the peak meter mode. To enable this control, 96 clock pulses must be input to the peak meter mode. • As afore mentioned, in the peak meter mode, the absolute time following the generation of a peak value is stored. These operations are shown in Time chart 2-3. Note: To perform the above operations, the duration of the clock pulse input to SQCK must be between 750ns and 120 µs for both “High” and “Low”. —26— CXD2500BQ Timing Chart 2-1 Internal PLL c lock 4.3218±∆MHz WFCK SCOR EXCK 750ns max SBSO S0·S1 Q R WFCK SCOR EXCK SBSO S0·S1 Q R S T U V W S0·S1 Same P1 QR S T U VW P1 Same Subcode P. Q. R. S. T. U. V. W Read Timing —27— P2 P3 SUB-Q Block Diagram 2-2 SI (ASEC) LD 8 80 bit P/S Register 8 80 bit S/P Register LD SUBQ LD —28— SO LD LD Peak detection 8 SI 8 Ring control 2 SHIFT 8 LD 16 16 bit P/S register Monostable multivibrator LD LOAD CONTROLE CRCC 8 SHIFT 8 Mix CRCF 8 ADDRS CTRL LD Ring control 1 8 (AMIN) Order Inversion ABS time load control for peak value H G F E D C B A A B C D E F G H SIN (AFRAM) SQSO SQCK SO CXD2500BQ LD —29— SQSO SQCK SQCK SQSO SCOR WFCK Timing Chart 2-3 CRCF Monostable multivibrator (Internal) CRCF 1 1 3 300ns max 3 2 1 ADR1 CRCF 1 ADR2 ADR3 CTL0 When SQCK=High, 270 to 400µsec Register load forbidder 94 Determined by mode 93 92 91 80 or 96 Clock 750ns to 120µs Order Inversion ADR0 2 95 CTL1 96 CTL2 97 CTL3 CRCF 2 98 CXD2500BQ CXD2500BQ §3 Other Functions §3-1 Channel Clock Regeneration Using Digital PLL Circuit • Demodulation of regenerated EFM signals using an optical system requires the use of channel clock pulses. The EFM signal to be demodulated has been modulated into an integer multiple of the channel clock period T, ranging from 3T to 11T. To read the information conveyed by the EFM signal, it is essential to correctly recognize the integral value; hence, the need to use channel clock pulses. In an actual CD player, the pulse width of the EFM signal will vary, affected by fluctuations of the disc rotation. For this reason, it is necessary to use a PLL in regenerating channel clock pulses. Figure 3-1 shows a block diagram of the 3-stage PLL contained in the CXD2500B. • The 1st-stage PLL is used for vari-pitch regeneration. To use this PLL, LPF and VCO are necessary as external parts. The minimum pitch variable possible is 0.1 %. The output of this 1st-stage PLL is used as the standard for all the clock pulses used in the LSI. When vari-pitch control is not in uses, connect the output pin of XTAO to VCKI. • The 2nd-stage PLL generates high frequency clock pulses necessary for the 3rd-stage digital PLL. • The 3rd-stage comprises a digital PLL used to regenerate the actual channel clock pulses. It realizes a capture range of ±150 kHz (normal conditions) or more. • The digital PLL features a secondary loop. It is controlled through the primary loop (phase) secondary loop (frequency). When FLFC=1, the secondary loop can be turned off. • When high frequency components such as 3T, 4T, are deviated, turning off the secondary loop will provide better play ability. • However, the capture range will be 50 kHz. —30— CXD2500BQ Block Diagram 3-1 16,9344MHz (384Fs) 1/1000 1/4 Phase comparator OSC X'Tal XTSL 1/4 1/1000+n VPCO LPF VCO 19. 78 to 13.26MHz VCKI 2/1 MUX Vari-pitch Up down counter n=-217 to 168 Microcomputer control Vari-pitch Phase comparator I/M I/N PCO FILI FILO VCO Digital PLL RFPLL D2500B —31— CLTV CXD2500BQ §3-2 Frame Sync Protection • During CD player operation at normal speed, Frame Sync is recorded approximately once every 136 µs (at 7.35 kHz). This signal can be used to identify the data within each frame. When Frame Sync cannot be recognized, the data also cannot be identified; as a result, it is treated as an error. Therefore, correct Frame Sync recognition is very important to ensure high play ability for the CD player. • The CXD2500B employs window protection, front protection and rear protection to realize a powerful Frame Sync protection. The CXD2500B offers two window widths, one for use when the player is subjected to rotational disturbance and the other for use without such disturbance (WSEL=0/1). The front protection counter is fixed at 13 and the rear protection counter at 3. Therefore, during normal play back, when the frame sync cannot be detected due to damages on the disc. If the number to frames with undetected Frame Sync exceeds 13, the window is released and the Frame Sync signal are re-synchronized. If no Frame Sync is correctly detected in 3 successive frames immediately after Frame Sync resynchronization performed following a window release, the window is released at once. §3-3 Error Correction • On CDs, each data unit (8 bits) is formatted so that it is contained in two correction codes, C1 and C2. C1 consists of 28 bytes of information and 4-byte parity, whereas C2 is made up of 24 bytes of information and 4-byte parity. Both C1 and C2 comprise a read Solomon code with a minimum distance of 5. • C1 realizes double corrections and C2 realizes quadruple corrections, both by the refined superstrategy method. • To prevent erroneous C2 corrections, C1 pointer based on the conditions of C1 error, EFM signal play back, and player operation during C1 operation is attached to the corrected data. • The status of error correction can be monitored from outside the LSI. It is indicated as shown in Table 3-2. • When C2 pointer is High, this signifies uncorrectable data error. The data are either previous data held subsitute the error, or an average value interpolation. MNT3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 MNT2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 MNT1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 MNT0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 C1: C1: C1: C1: C1: C1: C2: C2: C2: C2: C2: C2: C2: Description No error detected. C1 pointer reset. 1 error corrected. C1 pointer set. — — No error detected. C1 pointer set. 1 error corrected. C1 pointer set. 2 errors corrected. C1 pointer set. Uncorrectable error. C1 pointer set. No error detected. C2 pointer reset. 1 error corrected. C2 pointer reset. 2 errors corrected. C2 pointer reset. 3 errors corrected. C2 pointer reset. 4 errors corrected. C2 pointer reset. — Uncorrectable error. C1 pointer copied. Uncorrectable error. C2 pointer set. Table 3-2 Indication of error correction status —32— CXD2500BQ Timing Chart 3-3 Normal - speed PB 400 to 500nsec RFCK t=Dependent on error condition MNT3 C2 correction C1 correction MNT2 MNT1 MNT0 Strobe Strobe C4M MNT0 to 3 Valid Valid Invalid §3-4 DA Interface • The CXD2500B has two modes of DA interface. a) 48-bit slot interface This is an MSB-first interface made up of LRCK signals with 48-bit clock cycles per LRCK cycle. While the LRCK signal is High, the data going through this interface is of the left channel. b) 64-bit slot interface This is an LSB-first interface made up of LRCK signals with 64-bit clock cycles per LRCK cycle. While the LRCK signal is Low, the data going through this interface is of the left channel. —33— —34— DA16 WDCK DA15 (4.23M) LRCK (88.2K) 1 2 3 R0 L ch MSB (15) 1 2 5 L ch MSB (15) 4 48 bit slot Double-Speed Playback DA16 R0 WDCK DA15 (2.12M) LRCK (44.1K) 6 48 bit slot Normal-Speed Playback PSSL=L Timing Chart 3-4 7 8 9 L14 10 L13 11 L12 12 L0 24 L11 L9 R ch MSB L10 L8 L7 L6 L5 L4 L3 L2 L1 L0 24 RMSB CXD2500BQ —35— DA 14 DA 13 (5.64M) DA 12 (88.2K) DA 14 DA 13 (2.82M) DA 12 (44.4K) 2 4 5 R ch LSB (0) 3 L15 1 2 4 5 R ch LSB (0) 3 64 Bit slot Double–Speed PB 1 6 7 64 Bit slot Normal Speed PB PSSL=L Timing Chart 3-5 8 10 9 10 11 12 15 13 14 1 15 2 3 20 4 1 5 6 2 7 3 20 8 25 4 6 7 9 30 31 32 8 10 11 12 9 10 11 12 13 14 15 L ch LSB 5 13 30 32 14 R15 31 L ch LSB (0) CXD2500BQ CXD2500BQ §3-5 Digital Out There are three digital-out formats: type 1 for use at broadcasting stations, type 2, form 1 for use in general civil applications, and type 2, form 2 for use in software production. The CXD2500B supports type 2, form 1. The clock accuracy for the channel status is automatically set at Level II when the X'tal clock is used, or Level III when vari-pitch control is made. CRC checks are conducted on the Sub-Q data on the first 4 bits (bits 0-3). The data is input only after two checks are passed in succession. The X'tal clock is set to 34 MHz, and variable pitch is reset. When D out is output at DSPB=1, set MD2 to 0 and turn off D out 34. Digital Out C bit 0 1 2 0 16 3 From sub-Q ID0 ID1 COPY Emph 0 0 0 0 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/1 0 0 32 48 0 176 Bits 0-3: Sub-Q control bits required to pass the CRC twice in succession. bit 29: Varipitch: 1 X'tal: 0 Table 3-6 Digital Out C bits §3-6 Servo Auto Sequencer The servo auto sequencer controls a series of operation including auto-focusing and track jumping. When an auto sequence command is received from CPU, the servo auto sequencer automatically executes autofocusing, 1-track jumping, 2N track jumping and M track moving. During auto sequence execution (X Busy=Low), as SSP (servo signal processing LSI) is used exclusively, commands from CPU are not transferred to SSP. Instead, the commands can be sent to CXD2500B. To make this servo auto sequencer usable, connect a CPU, RF and SSP to the CXD2500B as shown in Figure 3-7 and set A.SEQ ON-OFF of Register 9 to ON. When the CLOK changes from Low to High while XBUSY is at Low, from that point on to a maximum of 100 µsec, X BUSY does not become High. Due to the monostable multivibrator which is reset when CLOK is Low (XBUSY=Low), transfer of erroneous data to SSP is prevented when XBUSY changes from Low to High. —36— CXD2500BQ (a) Auto Focus ($47) In auto focus operation, ‘focus search up’ is performed, FOK and FZC are checked, and the focus servo is turned on. When $47 is received from CPU, the focus servo is turned on through the steps shown in Figure 3-8. Since this auto focus sequence begins with ‘focus search up,’ it requires the pickup to be put down (focus search down) beforehand. Blind E of Register 5 is used to eliminate chattering from FZC. The focus servo is turned on at the trailing edge of FZC after staying High continuously for a longer period than E. System Configuration for Auto Sequencer Operation (Example) RF MIRR FOK MIRR FOK DATA CLOK XLAT SENS CXD2500B SSP C.out SENS DATA CLK XLT CNIN SEIN DATO CLKO XLTO Figure 3-7 —37— Micro-computer CXD2500BQ Auto focus Focus search up Checking whether FZC has stayed High longer than time E set in Register 5. FOK=H NO YES FZC=H NO YES FZC=L NO YES Focus servo ON END Figure 3-8 (a) Flow chart of auto focus operation $47 latch XLAT FOK SEIN(FZC) BUSY Command to SSP Blind E $03 Figure 3-8 (b) Timing chart for auto focus operation —38— $08 CXD2500BQ (b) Track Jump Track jump operation includes 1, 10 and 2N track jumps. Do not perform this track jump unless the focus, tracking and sled servos are on. Such steps as tracking gain up and braking are not included in this track jump. Therefore, the commands for tracking gain up and brake ON ($17) must be issued in advance. • 1-track jump When a $48 is received from CPU (or a $49 from REV), the servo auto sequencer executes a FWD (REV) 1-track jump as shown Figure 3-9. The values of blind A and brake B must be set in Register 5. • 10-track jump When a $4H is received from CPU (or a $4B from REV), the servo auto sequencer executes a FWD (REV) 10-track jump as shown in Figure 3-10. The principal difference between the 1-track and 10-track jumps is whether the sled is kicked or not. In the 10-track jump, the actuator after being kicked is braked when CNIN has been counted 5 tracks. When the actuator has adequately slowed down as a result of braking, the tracking and sled servos are turned on (this actuator slow-down is detected by checking whether the CNIN period has exceeded overflow C specified in Register 5). • 2N track jump When a $4C is received from CPU (or a $4D from REV), the servo auto sequencer executes a FWD (REV) 2N track jump. The number of tracks to be jumped is determined by N, set Register 7 beforehand. The maximum permissible number is 216. In actual use, however, it is subject to limitation imposed by the actuator. When N is smaller than 16, the jumps are counted by means of counting CNIN signals. If N is 16 and above, MIRR signals are counted instead of CNIN signals. The 2N track jump sequence is basically the same as the 10-track jump sequence. The only difference between them is that, in the 2N track jump sequence, the sled is kept moving for time D specified in Register 6 after the tracking servo is turned on. • M track move When a $4E is received from CPU (or a $4F from REV), the servo auto sequencer executes a FWD (REV) M-track move as shown in Figure 3-12. The maximum value that can be set from M is 216. The track moves are counted in the same way as for 2N track jumps. That is, when M is smaller than 16, the moves are counted by means of counting CNIN signals. If M is 16 and above, MIRR signals are counted instead of the CNIN signals. In this M track move, only the sled is moved. This method is suitable for a large track move ranging from several thousand to several tens of thousand tracks. —39— CXD2500BQ 1 Track Track Kick Sled servo (REV kick is made for REV jump.) WAIT (Blind A) CNIN= NO YES Track REV Kick (FWD kick is made for REV jump.) WAIT (Brake B) Track sled Servo ON END Figure 3-9 (a) Flow chart of 1-track jump $48 (REV=$49) latch XLAT CNIN BUSY Blind A Commands to SSP $28 ($2C) Brake B $2C ($28) Figure 3-9 (b) Timing chart for 1-track jump —40— $25 CXD2500BQ 10 Track Track, Sled FWD Kick WAIT (Blind A) CNIN= 5? (5 CNINs are counted.) NO YES Track, REV FWD Kick Checking whether the CNIN period has exceeded the value of overflow C. C=Overflow? NO YES Track, Sled Servo ON END Figure 3-10 (a) Flow chart of 10-track jump $4A (REV=$4B) latch XLAT CNIN BUSY Blind A Commands to SSP CNIN 5count $2A ($2F) Overflow C $2E ($2B) Figure 3-10 (b) Timing chart for 10-track jump —41— $25 CXD2500BQ 2N Track Track, Sled FWD Kick WAIT (Blind A) For the first 16 times CNIN is counted. After that MIRR is counted. CNIN (MIRR) =N NO YES Track, REV Kick C=Overflow NO YES Track Servo ON WAIT (Klick D) Sled Servo ON END Figure 3-11 (a) Flow chart of 2N track jump $4C (REV=$4D) latch XLAT CNIN (MIRR) BUSY Blind A Commands to SSP $2A ($2F) Kick D CNIN (MIRR) N count Overflow $2E ($2B) $26 ($27) Figure 3-11 (b) Timing chart for 2N track jump —42— $25 CXD2500BQ M Track move Track Servo OFF Sled FWD Kick WAIT (Blind A) CNIN is counted for M<16, MIRR is counted for M≥16. CNIN (MIRR) =M NO YES Track, Sled Servo ON END Figure 3-12 (a) Flow chart of M track move $4E (REV=$4F) latch XLAT CNIN (MIRR) BUSY Blind A Commands to SSP CNIN (MIRR) M count $22 ($23) $25 Figure 3-12 (b) Timing chart for M track move —43— CXD2500BQ §3-7 Digital CLV The digital CLV is a digital spindle servo, of which its block diagram is shown in Figure 3-14. It is capable of outputting MDS or MDP error signals by the PWM method after raising the sampling frequency up to 130 kHz based on the normal speed in the CLVS, CLVP and other modes. It also permits gain setting. Digital CLV Gain CLVS U/D MDS Error MDP Error 0, –6dB Measure Measure CLV P/S Over Sampling Filter-1 2/1 MUX Gs(Gain) GP(Gain) CLV P 1/2 + Mux CLV S CLV – P/S Over Sampling Filter-2 Noise Shape KICK, BRAKE STOP Modulation MDP Mode Select MDS DCLVMD Figure 3-14 Block diagram —44— CXD2500BQ §3-8 Asymmetry correction Block diagram and circuit example are shown on Fig. 3-15. D2500B 28 ASYE ASYO RF 24 R1 27 R1 R2 R1 ASYI 26 R1 25 BIAS R1 R2 = 2 5 Figure 3-15 Asymmetry correction application circuit example —45— CXD2500BQ Application Circuit R1 C9 5 4 3 2 1 FESRCH FEO FLB FGD FS3 VC FE SENS LDON FOK MUTE SQCK RV2 FOK BCLK (64) LRCK (64) GTOP RV1 FSW SENS RF 1 XRST DATA (64) GND 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 DATA XRST BCLK (64) TE MIRR 2 FOK 3 MON MOP C17 4 LOCK MOS AVSS CLTV VDD GND GND C15 5 22 RF AVDD DATA (64) GND C11 C16 6 NC VCOO DVCC 3 6 8 NC VCOI 13 9 14 NC TEST1 15 VPCO 10 16 VCKI FILO PDO 17 PCO FILI 12 18 11 7 34 33 DFCT 19 VSS NC 35 CC2 CC1 FOK 30 31 EFM 3 2 ASY DFCT 27 20 23 21 SUBQ CLOK WDCK (48) GND 6 MIRR 2 9 SENS 25 26 COUT XRST DGND 2 8 CP CB GND 7 TGU XLT DATA 48 47 46 45 44 43 42 41 40 39 38 37 8 CNIN SEIN 24 C4M C16M DOUT MO2 EMPH WFCK SBSO SCOR 54 56 57 58 59 61 62 63 64 FSTT 53 55 60 XTAI XTSL XTAO MNT3 RADF MNT2 MNT1 MNT0 APTL APTR 44 45 47 48 49 50 42 46 51 C2PO 43 52 RFCK 41 VSS GFS PLCK WFCK DOUT PLCK GFS RFCK RAOV GND TRACK-D GND FOCUS-D C10 9 NC PSSL GND GND MNT0 MNT1 MNT2 MNT3 GND STTP UGFS —46— GND SLED-D GND C23 C26 RFO 13 14 15 16 17 18 19 20 21 22 23 24 R4 R3 DATO 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 200p GND GND WDCK GND GND C2PO MUTE SPIND-D GND RFI CLK MUTE ASYE VCC V0 VCC DVee DIRC LOCK GFS CLK XLT VDD TG2 AVCC TAO TA- CXA1372Q AVee XLAT DATA CXD2500BQ LRCK (48) 10 11 12 C27 GND GND GND GND GND GND C14 TE TZC SSTOP SSTOP GND R2 R7 C28 R6 R11 C35 GND GND R12 AVDD FE TE RF LDON C13 TDFCT ISET R13 VCC GND R10 R14 Vee SL- SQSO EXCK XUGF ATSC FSET SCOR SQCK XLTO GND FE FZC VCC MIRR CLKO BIAS FD GND R5 R9 GND GND GND C12 FDFCT SL+ SLO GND GND GND GND ASTI ASTO GND 1M TD SLD SPD BCLK DATA LRCK DEMP Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party and other right due to same. CXD2500BQ Package Outline Unit : mm CXD2500BQ 80PIN QFP (PLASTIC) 23.9 ± 0.4 + 0.1 0.15 – 0.05 + 0.4 20.0 – 0.1 64 0.15 41 65 16.3 17.9 ± 0.4 + 0.4 14.0 – 0.1 40 A 80 + 0.2 0.1 – 0.05 1 24 0.8 0.12 + 0.15 0.35 – 0.1 M 0.8 ± 0.2 25 + 0.35 2.75 – 0.15 0° to 10° DETAIL A PACKAGE STRUCTURE SONY CODE QFP-80P-L01 EIAJ CODE ∗QFP080-P-1420-A JEDEC CODE PACKAGE MATERIAL EPOXY RESIN LEAD TREATMENT SOLDER PLATING LEAD MATERIAL COPPER / 42 ALLOY PACKAGE WEIGHT 1.6g CXD2500BQ 80PIN QFP (PLASTIC) 24.0 ± 0.3 + 0.4 20.0 – 0.1 + 0. 0.15 – 1 0.05 25 1 24 0.8 ± 0.12 M + 0.15 0.35 – 0.1 16.6 80 0.7 ± 0. 40 + 0.4 14.0 – 0.1 65 1 41 18.0 ± 0.3 64 + 0.2 0.1 – 0.05 2.7 ± 0.1 0° to 10° 3.1 MAX 0.15 22.6 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-80P-L121 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗QFP080-P-1420-AX LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 1.6g JEDEC CODE —47— CXD2500BQ CXD2500BQ QFP 80PIN (PLASTIC) 23.9 ± 0.2 ∗20.0 ± 0.2 0.15 ± 0.05 15° 24 1 0.35 ± 0.1 .2 15° 25 A 4 – 1.0 ∗14.0 ± 0.2 40 80 C1 4 – 0.8 0.15 M 1.45 0.8 ± 0.15 0.15 0° to 10° DETAIL A NOTE: Dimension “∗” does not include mold protrusion. PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE QFP-80P-L051 LEAD TREATMENT SOLDER PLATING EIAJ CODE ∗QFP080-P-1420-AH LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 1.6g JEDEC CODE —48— 1.95 ± 0.15 15° 2.94 ± 0.15 15° 0.24 ± 0.15 + 0.20 2.7 – 0.16 17.9 ± 0.2 65 0.8 41 64