CXD3605R
Timing Generator for Frame Readout CCD Image Sensor
Description
The CXD3605R is a timing generator IC which
generates the timing pulses for performing frame
readout using the ICX406 CCD image sensor.
Features
• Base oscillation frequency 36MHz
• High-speed/low-speed shutter function
• Supports draft (octuple speed)/AF(auto focus) drive
• Horizontal driver for CCD image sensor
• Vertical driver for CCD image sensor
Applications
Digital still cameras
Structure
Silicon gate CMOS IC
CKO
SSI
CKI
SCK
31
OSCO
SEN
32
OSCI
VD
33
MCKO
HD
34
VDD5
VSS6
Pin Configuration
35
Absolute Maximum Ratings
VSS – 0.3 to +7.0
• Supply voltage VDD
VL
–10.0 to VSS
VH
VL – 0.3 to +26.0
• Input voltage
VI
VSS – 0.3 to VDD + 0.3
• Output voltage VO1
VSS – 0.3 to VDD + 0.3
VO2
VO3
• Operating temperature
Topr
• Storage temperature
Tstg
Applicable CCD Image Sensors
ICX406 (Type 1/1.8, 3980K pixels)
36
48 pin LQFP (Plastic)
30
29
28
27
26
25
TEST1
37
24 VSS5
VM
38
23 ADCLK
V2
39
22 OBCLP
V4
40
21 VSS4
V1A
41
20 CLPDM
VH
42
19 PBLK
V1B
43
18 XRS
V3A
44
17 XSHD
1
2
3
4
5
6
7
8
9
10
11
12
VSS2
VSS3
H1
13 H2
RG
48
VDD1
TEST2
VDD2
14 VDD3
SSGSL
47
WEN
SUB
ID/EXP
15 VDD4
SNCSL
16 XSHP
46
RST
45
VSS1
VL
V3B
V
V
V
V
VL – 0.3 to VSS + 0.3
VL – 0.3 to VH + 0.3
V
V
V
–20 to +75
°C
–55 to +150
°C
Recommended Operating Conditions
• Supply voltage VDDb
3.0 to 5.25
VDDa, VDDc, VDDd 3.0 to 3.6
VM
0.0
VH
14.55 to 15.45
VL
–7.0 to –8.0
• Operating temperature
Topr
–20 to +75
V
V
V
V
V
°C
∗ Groups of pins enclosed in the figure indicate
sections for which power supply separation is
possible.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E00Z48
CXD3605R
OSCI
OSCO
CKI
VDD4
10
15 16 17 18 21
28
27
19 PBLK
20 CLPDM
1/2
26
22 OBCLP
Selector
23 ADCLK
Pulse Generator
CKO 25
MCKO 30
SNCSL
VSS4
VSS2
9
XRS
RG
XSHD
VDD2
XSHP
VSS3
8
H2
14 12 13 11
H1
VDD3
Block Diagram
3
24 VSS5
1/2
Latch
Selector
4
ID/EXP
5
WEN
41 V1A
43 V1B
SSI 31
39 V2
SCK 32
Register
44 V3A
SEN 33
6
RST
2
46 V3B
V Driver
Selector
SSGSL
SSG
40 V4
47 SUB
42 VH
TEST1 37
38 VM
TEST2 48
1
36
–2–
VDD5
VSS1
VSS6
35
34
VD
29
HD
7
VDD1
45 VL
CXD3605R
Pin Description
Pin
No.
Symbol
I/O
1
VSS1
—
2
RST
I
Internal system reset input.
Normally apply reset during power-on.
3
SNCSL
I
Control input used to switch sync system. High: CKI sync, Low: MCKO sync
With pull-down resistor
4
ID/EXP
O
Vertical direction line identification pulse output/exposure time identification pulse
output. Switching possible using the serial interface data. (Default: ID)
5
WEN
O
Memory write timing pulse output.
6
SSGSL
I
7
VDD1
—
3.3V power supply. (Power supply for common logic block)
8
VDD2
—
3.3V power supply. (Power supply for RG)
9
RG
O
CCD reset gate pulse output.
10
VSS2
—
GND
11
VSS3
—
GND
12
H1
O
CCD horizontal register clock output.
13
H2
O
CCD horizontal register clock output.
14
VDD3
—
3.3 to 5.0V power supply. (Power supply for H1/H2)
15
VDD4
—
3.3V power supply. (Power supply for CDS block)
16
XSHP
O
CCD precharge level sample-and-hold pulse output.
17
XSHD
O
CCD data level sample-and-hold pulse output.
18
XRS
O
Sample-and-hold pulse output for analog/digital conversion phase alignment.
19
PBLK
O
Pulse output for horizontal and vertical blanking period pulse cleaning.
20
CLPDM
O
CCD dummy signal clamp pulse output.
21
VSS4
—
GND
22
OBCLP
O
CCD optical black signal clamp pulse output.
The horizontal/vertical OB pattern can be changed using the serial interface data.
23
ADCLK
O
Clock output for analog/digital conversion IC.
Logical phase adjustment possible using the serial interface data.
24
VSS5
—
GND
25
CKO
O
Inverter output.
26
CKI
I
Inverter input.
27
OSCO
O
Inverter output for oscillation.
28
OSCI
I
Inverter input for oscillation.
29
VDD5
—
3.3V power supply. (Power supply for common logic block)
30
MCKO
O
System clock output for signal processing IC.
Description
GND
Internal SSG enable.
High: Normal operation, Low: Reset control
Schmitt trigger input
High: Internal SSG valid, Low: External sync valid.
With pull-down resistor
When not used, leave open or connect a capacitor.
When not used, fix low.
–3–
CXD3605R
Pin
No.
Symbol
31
SSI
I
32
SCK
I
33
SEN
I
34
VD
I/O
Vertical sync signal input/output.
35
HD
I/O
Horizontal sync signal input/output.
36
VSS6
—
GND
37
TEST1
38
VM
—
GND (GND for vertical driver)
39
V2
O
CCD vertical register clock output.
40
V4
O
CCD vertical register clock output.
41
V1A
O
CCD vertical register clock output.
42
VH
—
15.0V power supply. (Power supply for vertical driver)
43
V1B
O
CCD vertical register clock output.
44
V3A
O
CCD vertical register clock output.
45
VL
—
–7.5V power supply.(Power supply for vertical driver)
46
V3B
O
CCD vertical register clock output.
47
SUB
O
CCD electronic shutter pulse output.
48
TEST2
I
IC test pin 2; normally fixed to GND.
I/O
I
Description
Serial interface data input for internal mode settings.
Schmitt trigger input
Serial interface clock input for internal mode settings.
Schmitt trigger input
Serial interface strobe input for internal mode settings.
Schmitt trigger input
IC test pin 1; normally fixed to GND.
–4–
With pull-down resistor
With pull-down registor
CXD3605R
Electrical Characteristics
DC Characteristics
Item
Supply
voltage 1
Supply
voltage 2
Supply
voltage 3
Supply
voltage 4
(Within the recommended operating conditions)
Pins
Symbol
Conditions
Typ.
Max.
Unit
VDD2
VDDa
3.0
3.3
3.6
V
VDD3
VDDb
3.0
3.3
5.25
V
VDD4
VDDc
3.0
3.3
3.6
V
VDD1, VDD5
VDDd
3.0
3.3
3.6
V
Vt+
Vt–
TEST1, TEST2, VIH1
Input
voltage 2 ∗2 SNCSL, SSGSL VIL1
VIH2
VIL2
Input/output VD, HD
voltage
VOH1
VOL1
VOH2
Output
H1, H2
voltage 1
VOL2
VOH3
Output
RG
voltage 2
VOL3
0.8VDDd
RST, SSI, SCK,
Input
voltage 1 ∗1 SEN
0.2VDDd
0.7VDDd
0.2VDDd
0.8VDDd
0.2VDDd
Feed current where IOH = –1.2mA VDDd – 0.8
Pull-in current where IOL = 2.4mA
Feed current where IOH = –22.0mA VDDb – 0.8
Pull-in current where IOL = 14.4mA
Feed current where IOH = –3.3mA VDDa – 0.8
Pull-in current where IOL = 2.4mA
Output
voltage 3
XSHP, XSHD,
VOH4
XRS, PBLK,
OBCLP, CLPDM,
VOL4
ADCLK
Feed current where IOH = –3.3mA
Output
voltage 4
CKO
Output
voltage 5
MCKO
VOH5
VOL5
VOH6
Output
voltage 6
ID/EXP,
WEN
Output
current 1
V1A, V1B,
V3A, V3B,
V2, V4
Feed current where IOH = –6.9mA
Pull-in current where IOL = 4.8mA
Feed current where IOH = –3.3mA
Pull-in current where IOL = 2.4mA
Feed current where IOH = –2.4mA
Pull-in current where IOL = 4.8mA
V1A/B, V2, V3A/B, V4 = –8.25V
V1A/B, V2, V3A/B, V4 = –0.25V
V1A/B, V3A/B = 0.25V
V1A/B, V3A/B = 14.75V
SUB = –8.25V
SUB = 14.75V
Output
current 2
Min.
SUB
VOL6
VOH7
VOL7
IOL
IOM1
IOM2
IOH
IOSL
IOSH
Note) The above table indicates the condition for 3.3V drive.
–5–
0.4
0.4
V
V
V
V
V
V
V
V
VDDc – 0.8
Pull-in current where IOL = 2.4mA
∗1 This input pin is a schmitt trigger input.
∗2 This input pin is with pull-down registor in the IC.
0.4
V
V
V
V
V
0.4
VDDd – 0.8
0.4
VDDd – 0.8
0.4
VDDd – 0.8
0.4
10.0
–5.0
5.0
–7.2
5.4
–4.0
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
CXD3605R
Inverter I/O Characteristics for Oscillation
Item
Pins
Symbol
Logical Vth
OSCI
Input voltage
OSCI
Output
voltage
OSCO
Feedback
resistor
OSCI, OSCO RFB
Oscillation
frequency
OSCI, OSCO f
(Within the recommended operating conditions)
Min.
Conditions
LVth
Typ.
Max.
VDDd/2
V
0.7VDDd
VIH
V
VIL
0.3VDDd
VOH
Feed current where IOH = –3.6mA VDDd – 0.8
VOL
Pull-in current where IOL = 2.4mA
VIN = VDDd or VSS
500k
Unit
V
V
2M
20
0.4
V
5M
Ω
50
MHz
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment
(Within the recommended operating conditions)
Item
Pins
Logical Vth
Input voltage
Symbol
Conditions
Min.
LVth
CKI
Input amplitude
Typ.
VDDd/2
VIH
V
0.3VDDd
fmax 50MHz sine wave
Unit
V
0.7VDDd
VIL
VIN
Max.
0.3
V
Vp-p
Note) Input voltage is the input voltage characteristics for direct input from an external source. Input amplitude
is the input amplitude characteristics in the case of input through a capacitor.
Switching Characteristics
Item
Rise time
Fall time
Output noise voltage
(VH = 15.0V, VM = GND, VL = –7.5V)
Symbol
Conditions
Min.
Typ.
Max.
Unit
TTLM
VL to VM
200
350
500
ns
TTMH
VM to VH
200
350
500
ns
TTLH
VL to VH
30
60
90
ns
TTML
VM to VL
200
350
500
ns
TTHM
VH to VM
200
350
500
ns
TTHL
VH to VL
30
60
90
ns
VCLH
1.0
V
VCLL
1.0
V
VCMH
1.0
V
VCML
1.0
V
Note)
1) The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for
measures to prevent electrostatic discharge.
2) For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more) between
each power supply pin (VH, VL) and GND.
3) To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor.
–6–
CXD3605R
Switching Waveforms
TTMH
TTHM
VH
V1A (V1B, V3A, V3B)
TTLM
90%
90%
10%
10%
TTML
VM
90%
90%
10%
10%
TTML
TTLM
VL
VM
90%
90%
V2 (V4)
10%
10%
TTLH
TTHL
90%
VL
VH
90%
SUB
10%
10%
VL
Waveform Noise
VM
VCMH
VCML
VCLH
VCLL
VL
–7–
CXD3605R
Measurement Circuit
Serial interface data
CKI
VD
HD
C6
+3.3V
–7.5V
C6
+15.0V
36 35 34 33 32 31 30 29 28 27 26 25
R1
C2
C2
R1
R1
C1 C2
C1
C2
C2
R1
C2 C2
C2
C2
C1
C2
C1
C2
C2
C1
24
38
23
39
22
40
21
41
20
42
19
CXD3605R
43
C2
R1
C1
C2
R2
C2
37
C3
R1
18
44
17
45
16
46
15
47
14
48
13
1
2
3
4
5
6
7
8
9
10 11 12
C4
C1
R1
3300pF
30Ω
C2
R2
560pF
10Ω
C3
820pF
C4
8pF
–8–
C5
215pF
C6
C5
10pF
C6
C6
C6
C6
C6
C6
C6
C5
CXD3605R
AC Characteristics
AC characteristics between the serial interface clocks
0.8VDDd
SSI
0.2VDDd
0.8VDDd
SCK
ts1
SEN
th1
0.2VDDd
ts3
0.8VDDd
SEN
ts2
(Within the recommended operating conditions)
Symbol
ts1
th1
ts2
ts3
Definition
Min.
Typ.
Max.
Unit
SSI setup time, activated by the rising edge of SCK
20
ns
SSI hold time, activated by the rising edge of SCK
20
ns
SCK setup time, activated by the rising edge of SEN
20
ns
SEN setup time, activated by the rising edge of SCK
20
ns
Serial interface clock internal loading characteristics (1)
Example: During frame mode
VD
HD
V1A
Enlarged view
HD
0.2VDDd
V1A
ts1
SEN
th1
0.8VDDd
0.2VDDd
∗ Be sure to maintain a constantly high SEN logic level near the falling edge of the HD in the horizontal period
during which V1A/B and V3A/B values take the ternary value and during that horizontal period.
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
Typ.
Max.
Unit
SEN setup time, activated by the falling edge of HD
0
ns
SEN hold time, activated by the falling edge of HD
110
µs
–9–
CXD3605R
Serial interface clock internal loading characteristics (2)
Example: During frame mode
VD
HD
Enlarged view
VD
0.2VDDd
HD
ts1
th1
0.8VDDd
SEN
0.2VDDd
∗ Be sure to maintain a constantly high SEN logic level near the falling edge of VD.
(Within the recommended operating conditions)
Definition
Symbol
ts1
th1
Min.
Typ.
Max.
Unit
SEN setup time, activated by the falling edge of VD
0
ns
SEN hold time, activated by the falling edge of VD
200
ns
Serial interface clock output variation characteristics
Normally, the serial interface data is loaded to the CXD3605R at the timing shown in "Serial interface clock
internal loading characteristics (1)" above. However, one exception to this is when the data such as STB is
loaded to the CXD3605R and controlled at the rising edge of SEN. See "Description of Operation".
SEN
0.8VDDd
Output signal
tpdPULSE
(Within the recommended operating conditions)
Symbol
Definition
Min.
tpdPULSE Output signal delay, activated by the rising edge of SEN
– 10 –
5
Typ.
Max.
Unit
100
ns
CXD3605R
RST loading characteristics
RST
0.8VDDd
0.2VDDd
tw1
(Within the recommended operating conditions)
Definition
Symbol
tw1
Min.
RST pulse width
Typ.
Max.
Unit
ns
25
VD and HD phase characteristics
VD
0.2VDDd
0.2VDDd
ts1
th1
HD
0.2VDDd
(Within the recommended operating conditions)
Definition
Symbol
ts1
th1
Min.
VD setup time, activated by the falling edge of HD
Typ.
Max.
Unit
ns
100
VD hold time, activated by the falling edge of HD
20
ns
HD loading characteristics
HD
0.2VDDd
0.2VDDd
ts1
th1
0.8VDDd
MCKO
MCKO load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
ts1
th1
Definition
Min.
Typ.
Max.
Unit
HD setup time, activated by the rising edge of MCKO
20
ns
HD hold time, activated by the rising edge of MCKO
5
ns
– 11 –
CXD3605R
Output variation characteristics
0.8VDDd
MCKO
WEN, ID/EXP
tpd1
WEN and ID/EXP load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
tpd1
Definition
Min.
Time until the above outputs change after the rise of MCKO
20
– 12 –
Typ.
Max.
Unit
60
ns
CXD3605R
Description of Operation
Pulses output from the CXD3605R are controlled mainly by the RST pin and by the serial interface data. The
Pin Status Table is shown below, and the details of serial interface control are described on the following
pages.
Pin Status Table
Pin
No.
Symbol
CAM
SLP
STB
RST
—
Pin
No.
Symbol
CAM
SLP
STB
RST
25
CKO
ACT
ACT
L
ACT
L
26
CKI
ACT
ACT
ACT
ACT
ACT
ACT
27
OSCO
ACT
ACT
ACT
ACT
L
L
L
28
OSCI
ACT
ACT
ACT
ACT
ACT
L
L
L
29
VDD5
ACT
ACT
ACT
ACT
30
MCKO
ACT
ACT
L
ACT
—
31
SSI
ACT
ACT
ACT
DIS
—
32
SCK
ACT
ACT
ACT
DIS
33
ACT
ACT
ACT
DIS
34
SEN
VD∗1
ACT
L
L
H
35
HD∗1
ACT
L
L
H
ACT
36
VSS6
—
ACT
37
TEST1
—
—
38
VM
—
—
39
V2
ACT
VM
VM
VM
ACT
40
V4
ACT
VM
VM
VL
L
ACT
41
V1A
ACT
VH
VH
VM
L
L
ACT
42
VH
ACT
L
L
H
43
V1B
ACT
VH
VH
VM
ACT
L
L
H
44
V3A
ACT
VH
VH
VL
45
VL
H
46
V3B
ACT
VH
VH
VL
ACT
47
SUB
ACT
VH
VH
VL
48
TEST2
1
VSS1
2
RST
ACT
ACT
ACT
3
SNCSL
ACT
ACT
4
ID/EXP
ACT
5
WEN
6
SSGSL
7
VDD1
8
VDD2
9
RG
10
VSS2
—
11
VSS3
—
12
H1
ACT
L
L
13
H2
ACT
L
L
14
VDD3
15
VDD4
16
XSHP
ACT
L
L
17
XSHD
ACT
L
18
XRS
ACT
19
PBLK
20
CLPDM
21
VSS4
22
OBCLP
ACT
L
L
23
ADCLK
ACT
L
L
24
VSS5
ACT
L
L
ACT
—
—
—
—
—
—
∗1 It is for output. For input, all items are "ACT".
Note) ACT means that the circuit is operating, and DIS means that loading is stopped. L indicates a low
output level, and H a high output level in the controlled status.
Also, VH, VM and VL indicate the voltage levels applied to VH (Pin 42), VM (Pin 38) and VL (Pin 45),
respectively, in the controlled status.
– 13 –
CXD3605R
Serial Interface Control
The CXD3605R basically loads and reflects the serial interface data sent in the following format in the readout
portion at the falling edge of HD. Here, readout portion specifies the horizontal period during which V1A/B and
V3A/B, etc. take the ternary value.
Note that some items reflect the serial interface data at the falling edge of VD or the rising edge of SEN.
SSI
00
01
02
03
04
05
06
07
41
42
43
44
45
46
47
SCK
SEN
These are two categories of serial interface data: the CXD3605R drive control data (hereafter "control data")
and electronic shutter data (hereafter "shutter data").
The details of each data are described below.
– 14 –
CXD3605R
Control Data
Data
Symbol
Data = 0
Function
Data = 1
RST
D00
to
D07
CHIP
Chip enable
10000001 → Enabled
Other values → Disabled
All
0
D08
to
D09
CTG
Category switching
See D08 to D09 CTG.
All
0
D10
to
D12
MODE
Drive mode switching
See D10 to D12 MODE.
All
0
D13
SMD
D14
HTSG
D15
to
D16
D17
Electronic shutter mode switching∗1
HTSG control switching∗1
ON
0
OFF
ON
0
—
—
All
0
NTSC
PAL
0
—
—
—
All
0
OFF
ON
0
ID
EXP
0
—
—
SSG function switching
NTPL
D18
to
D31
OFF
—
D32
FGOB
Wide OBCLP generation switching
D33
EXP
ID/EXP output switching
D34
to
D35
PTOB
OBCLP waveform patterm switching
D36
to
D37
LDAD
ADCLK logic phase adjustment
D38
to
D39
STB
Standby control
D40
to
D47
See D34 to D35 PTOB.
All
0
1
—
See D36 to D37 LDAD.
See D38 to D39 STB.
—
—
∗1 See D13 SMD.
– 15 –
—
0
All
0
All
0
CXD3605R
Shutter Data
Data
Symbol
Function
Data = 0
Data = 1
RST
D00
to
D07
CHIP
Chip enable
10000001 → Enabled
Other values → Disabled
All
0
D08
to
D09
CTG
Category switching
See D08 to D09 CTG.
All
0
D10
to
D19
SVD
Electronic shutter vertical period
specification
See D10 to D19 SVD.
All
0
D20
to
D31
SHD
Electronic shutter horizontal period
specification
See D20 to D31 SHD.
All
0
D32
to
D41
SPL
High-speed shutter position
specification
See D32 to D41 SPL.
All
0
D42
to
D47
—
—
—
– 16 –
—
All
0
CXD3605R
Detailed Description of Each Data
Shared data: D08 to D09 CTG [Category]
Of the data provided to the CXD3605R by the serial interface, the CXD3605R loads D10 and subsequent
data to each data register as shown in the table below according to the combination of D08 and D09 .
D09
D08
Description of operation
0
0
Loading to control data register
0
1
Loading to shutter data register
1
X
Test mode
Note that the CXD3605R can apply these categories consecutively within the same vertical period. However,
care should be taken as the data is overwritten if the same category is applied.
Control data: D10 to D12 MODE [Drive mode]
The CXD3605R drive mode can be switched as follows. However, the drive mode bits are located to the
CXD3605R and reflected at the falling edge of VD.
D12
D11
D10
0
0
0
0
0
0
0
Description of operation
D12
D11
D10
Description of operation
Draft mode (default)
1
0
0
Draft mode
1
AF1 mode
1
0
1
Frame mode (A field read out)
1
0
AF2 mode
1
1
0
Frame mode (B field read out)
1
1
Frame mode
1
1
1
Test mode
Draft mode is the pulse eliminator drive mode called octuple speed mode in the ICX406. This is a high frame
rate drive mode that can be used for purposes such as monitoring and auto focus (AF).
AF1 and AF2 modes are the pulse eliminator drive modes called by the same names in the ICX406. These
drive modes are based on draft mode, and are used to increase the frame rate for auto focus (AF). In these
modes, the screen is swept in the vertical direction and the center portion lines are cut out.
Frame mode is the ICX406 drive mode in which the data for all lines are read. This drive mode is comprised of
A and B Fields, so when it is established, repeated drive is performed in the manner of A → B → A → and so
on.
Frame mode (A or B Field) is the drive mode in which each field can be specified separately.
Control data: D17 NTPL [SSG function switching]
The CXD3605R internal SSG output pattern can be switched as follows. However, the SSG function switching
bits are loaded to the CXD3605R and reflected at the falling edge of VD.
D17
Description of Operation
0
NTSC equivalent pattern output
1
PAL equivalent pattern output
VD period in each pattern is defined as follows.
NTSC equivalent pattern
PAL equivalent pattern
Frame mode
Draft mode
AF1 mode
AF2 mode
1012H + 1672ck
224H + 1372ck × 2
112H + 1372ck
56H + 686ck
944H + 464ck
269H + 2039ck
134H + 2354ck
67H + 1178ck
See the Timing Charts for the actual operation.
– 17 –
CXD3605R
Control data: D32 FGOB [Wide OBCLP generation]
This controls wide OBCLP generation during the vertical OPB period. See the Timing Charts for the actual
operation. The default is "OFF".
D32
Description of operation
0
Wide OBCLP generation OFF
1
Wide OBCLP generation ON
Control data: D34 to D35 PTOB [OBCLP waveform pattern]
This indicates the OBCLP waveform pattern. The default is "Normal".
D35
D34
Waveform pattern
0
0
(Normal)
0
1
(Shifted rearward)
1
0
(Shifted forward)
1
1
(Wide)
Control data: D36 to D37 LOAD [ADCLK logical phase]
This indicates the ADCLK logic phase adjustment data. The default is 90° relative to MCKO.
D37
D36
Degree of adjustment (°)
0
0
0
0
1
90
1
0
180
1
1
270
Control data: D38 to D39 STB [Standby]
The operating mode is switched as follows. However, the standby bits are loaded to the CXD3605R and
control is applied immediately at the rising edge of SEN.
D39
D38
Symbol
Operating mode
X
0
CAM
Normal operating mode
0
1
SLP
Sleep mode
1
1
STB
Standby mode
See the Pin Status Table for the pin status in each mode.
– 18 –
CXD3605R
Control data/shutter data: [Electronic shutter]
The CXD3605R realizes various electronic shutter functions by using control data D13 SMD and D14 HTSG
and shutter data D10 to D19 SVD, D20 to D31 SHD and D32 to D41 SPL.
These functions are described in detail below.
First, the various modes are shown below.
These modes are switched using control data D13 SMD.
D13
Description of operation
0
Electronic shutter stopped mode
1
Electronic shutter mode
The electronic shutter data is expressed as shown in the table below using D20 to D31 SHD as an example.
However, MSB (D31) is a reserve bit for the future specification, and it is handled as a dummy on this IC.
MSB
LSB
D31
D30
X
0
↓
1
D29
D28
D27
D26
0
1
1
1
↓
C
D25
D24
D23
D22
0
0
0
0
D21
D20
1
1
↓
3
SHD is expressed as 1C3h .
[Electronic shutter stopped mode]
During this mode, all shutter data items are invalid.
SUB is not output in this mode, so the shutter speed is the accumulation time for one field.
[Electronic shutter mode]
During this mode, the shutter data items have the following meanings.
Symbol
Data
Description
SVD
D10 to D19
Number of vertical periods specification (000h ≤ SVD ≤ 3FFh)
SHD
D20 to D31
Number of horizontal periods specification (000h ≤ SHD ≤ 7FFh)
SPL
D32 to D41
Vertical period specification for high-speed shutter operation (000h ≤ SPL ≤ 3FFh)
Note) The bit data definition area is assured in terms of the CXD3605R functions, and does not assure the
CCD characteristics.
The period during which SVD and SHD are specified together is the shutter speed. An image of the exposure
time calculation formula is shown below. In actual operation, the precise exposure time is calculated from the
operating frequency, VD and HD periods, decoding value during the horizontal period, and other factors.
(Exposure time) = SVD + {(number of HD per 1V) – (SHD + 1)}
Concretely, when specifying high-speed shutter, SVD is set to "000h". (See the figure.) During low-speed
shutter, or in other words when SVD is set to "001h" or higher, the serial interface data is not loaded until this
period is finished.
The vertical period indicated here corresponds to one field in each drive mode. In addition, the number of
horizontal periods applied to SHD can be considered as (number of SUB pulses – 1).
– 19 –
CXD3605R
VD
SVD
SHD
V1A
SUB
WEN
EXP
SMD
1
1
SVD
002h
000h
SHD
10Fh
050h
Exposure time
Further, SPL can be used during this mode to specify the SUB output at the desired vertical period during the
low-speed shutter period.
In the case below, SUB is output based on SHD at the SPL vertical period out of (SVD + 1) vertical periods.
SPL
000
001
VD
002
SVD
SHD
V1A
SUB
WEN
EXP
SMD
1
SPL
001h
000h
SVD
002h
000h
SHD
10Fh
0A3h
1
Exposure time
Incidentally, SPL is counted as "000h", "001h", "002h" and so on in conformance with SVD.
Using this function it is possible to achieve smooth exposure time transitions when changing from low-speed
shutter to high-speed shutter or vice versa.
– 20 –
CXD3605R
[HTSG control mode]
This mode controls the V1A/B and V3A/B ternary level outputs (readout pulse block) using D14 HTSG.
D14
Description of operation
0
Readout pulse (SG) normal operation
1
HTSG control mode
VD
V1A
SUB
Vck
WEN
EXP
HTSG
0
1
0
SMD
1
0
1
Exposure time
[EXP pulse]
The ID/EXP pin (Pin 4) output can be switched between the ID pulse or the EXP pulse using D33 EXP. The
default is the "ID" pulse. See the Timing Charts for the ID pulse. The EXP pulse indicates the exposure time
when it is high. The transition point is the last SUB pulse falling edge, and midpoint value (1338ck) of each
V1A/B and V3A/B ternary out put falling edge. When there is no SUB pulse, the later ternary output falling
edge (1416ck) is used. See the EXP pulse indicated in the explanatory diagrams under [Electronic shutter] for
an image of operation.
Note that the above specification is based on draft mode. For frame mode, the former value is 1260ck and the
latter value is 1416ck.
– 21 –
– 22 –
WEN
ID/EXP
CLPDM
OBCLP
PBLK
CCD OUT
V4
V3B
V3A
V2
V1B
V1A
SUB
HD
VD
C
High-speed sweep block
1013 1
A
75
82
1 3 5 7 9 11 1 3 5 7 9 11
A Field
MODE
Frame mode
1719
1547
1715
1713
1709
1711
1718
1716
1714
1712
943
C
1013 1
High-speed sweep block
• ICX406
B
74
B Field
82
2 4 6 8 10 12 2 4 6 8
Applicable CCD image sensor
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
∗ VD of this chart is NTSC equivalent pattern (1012H + 1672ck units). For PAL equivalent pattern, it is 944H + 464ck units.
943
Vertical Direction Timing Chart
1720
Chart-1
CXD3605R
– 23 –
WEN
ID/EXP
CLPDM
OBCLP
PBLK
CCD OUT
V4
V3B
V3A
V2
V1B
V1A
SUB
HD
VD
D
3
10 5 14 21 30 37 46
1 6 1 10 17 26 33 42
226 1
MODE
Draft mode
1713 1717
1706 1710
1706 1710
218
D
3
10 5 14 21 30 37 46
1 6 1 10 17 26 33 42
226 1
• ICX406
Applicable CCD image sensor
∗ The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
∗ ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
∗ VD of this chart is NTSC equivalent pattern (224H + 1372ck + 1372ck units). For PAL equivalent pattern, it is 269H + 2039ck units.
218
Vertical Direction Timing Chart
1713 1717
Chart-2
CXD3605R
– 24 –
WEN
ID/EXP
CLPDM
OBCLP
PBLK
CCD OUT
V4
V3B
V3A
V2
V1B
V1A
SUB
HD
VD
Chart-3
∗
∗
∗
∗
High-speed
sweep block
E
113
10
6
F Frame shift block
2
9
G
High-speed
sweep block
E
113
10
6
F Frame shift block
2
9
• ICX406
AF1 mode
106
Applicable CCD image sensor
MODE
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
240 stages are fixed for high-speed sweep block; 232 stages are fixed for frame shift block.
VD of this chart is NTSC equivalent pattern (112H + 1372ck units). For PAL equivalent pattern, it is 134H + 2354ck units.
G
106
Vertical Direction Timing Chart
CXD3605R
– 25 –
WEN
ID/EXP
CLPDM
OBCLP
PBLK
CCD OUT
V4
V3B
V3A
V2
V1B
V1A
SUB
HD
VD
Chart-4
∗
∗
∗
∗
High-speed sweep block
E
57
10
6
F
2
Frame shift block
12
MODE
AF2 mode
57
G High-speed sweep block E
47
10
6
F
2
Frame shift block
• ICX406
12
Applicable CCD image sensor
The number of SUB pulses is determined by the serial interface data. This chart shows the case where SUB pulses are output in each horizontal period.
ID/EXP of this chart shows ID. ID is low for lines where CCD OUT contains the R component, and high for lines where CCD OUT contains the B component.
360 stages are fixed for high-speed sweep block; 360 stages are fixed for frame shift block.
VD of this chart is NTSC equivalent pattern (56H + 686ck units). For PAL equivalent pattern, it is 67H + 1178ck units.
G
47
Vertical Direction Timing Chart
CXD3605R
– 26 –
∗
∗
∗
∗
∗
4
(2669)
0
16
16
24
32
42
50
50
58
58
58
60
60
60
92
100
124
124
124
Horizontal Direction Timing Chart
156
150
168
188
220
232
252
250
284
300
319
317
343
347
343
345 361 365
350
400
450
500
• ICX406
Frame mode
200
Applicable CCD image sensor
MODE
The HD of this chart indicates the actual CXD3605R load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-1.
WEN
ID/EXP
CLPDM
OBCLP
OBCLP (4)
OBCLP (3)
OBCLP (2)
OBCLP (1)
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HD
Chart-5
550
CXD3605R
HD
– 27 –
∗
∗
∗
∗
∗
4
(2669)
0
16
16
24
32
42
50
50
58
58
58
60
60
60
68
76
84
124
124
168
200
204
212
232
308
300
300
292
284
276
268
260
252
244
236
228
220
250
319
317
MODE
Draft mode, AF1 mode, AF2 mode
196
188
180
172
164
156
150
148
140
132
124
116
108
100
92
100
Horizontal Direction Timing Chart
343
347
343
345 361 365
350
400
• ICX406
450
Applicable CCD image sensor
500
The HD of this chart indicates the actual CXD3605R load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID. ID/EXP and WEN are output at the timing shown above at the position shown in Chart-2, 3 and 4.
WEN
ID/EXP
CLPDM
OBCLP
OBCLP (4)
OBCLP (3)
OBCLP (2)
OBCLP (1)
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
Chart-6
550
CXD3605R
– 28 –
∗
∗
∗
∗
∗
∗
4
(2669)
0
50
60
60
60
88
88
100
#1
116
116
Horizontal Direction Timing Chart
(High-speed sweep: C)
144
144
150
168
172
172
200
200
200
232
#2
228
228
256
256
250
MODE
Frame mode
284
284
300
312
312
317
#3
340
340
368
368
345 361 365
350
396
396
400
424
424
• ICX406
#4
452
452
450
480
480
508
508
500
Applicable CCD image sensor
536
536
The HD of this chart indicates the actual CXD3605R load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID.
High-speed sweep of V1A/B, V2, V3A/B, V4 is performed up to 72H of 2660ck (#1739).
WEN
ID/EXP
CLPDM
OBCLP
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HD
Chart-7
#5
550
564
564
CXD3605R
– 29 –
∗
∗
∗
∗
∗
∗
4
(2669)
0
24
50
50
60
60
60
68
76
84
#1
124
#2
168
204
232
#4
350
#5
#6
#7
500
556
550
#8
548
540
532
524
516
508
500
492
484
476
468
460
452
450
444
436
428
420
412
404
400
• ICX406
Applicable CCD image sensor
396
388
380
372
364
356
348
345 361 365
340
332
324
317
316
308
300
300
292
284
276
268
260
252
244
236
228
#3
212
220
250
MODE
AF1 mode, AF2 mode
200
196
188
180
172
164
156
150
148
140
132
124
116
108
100
92
100
Horizontal Direction Timing Chart
(Frame shift: F)
(High-speed sweep: G)
The HD of this chart indicates the actual CXD3605R load timing.
The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
SUB is output at the timing shown above when output is controlled by the serial interface data.
ID/EXP of this chart shows ID. PBLK, OBCLP, ID/EXP and WEN are output at the timing shown above at the position shown in Chart-2, 3 and 4.
Frame shift of V1A/B, V2, V3A/B and V4 is performed up to 7H 1563ck (#232) in AF1 mode and 10H 1688ck (#360) in AF2 mode.
In addition, high-speed sweep is performed up to 111H 2015ck (#240) in AF1 mode and 55H 1688ck (#360) in AF2 mode.
WEN
ID/EXP
CLPDM
OBCLP
PBLK
SUB
V4
V3A/B
V2
V1A/B
H2
H1
MCKO
HD
Chart-8
CXD3605R
– 30 –
V4
V3B
V3A
V2
V1B
V1A
V4
V3B
V3A
V2
V1B
V1A
HD
B
A
• ICX406
(2669)
0
124
1168
1136
1104
Applicable CCD image sensor
284
252
220
1292
1260
∗ The HD of this chart indicates the actual CXD3605R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
[B Field]
[A Field]
(2669)
0
1200 1202
MODE
Frame mode
156
Horizontal Direction Timing Chart
188
Chart-9
CXD3605R
– 31 –
D
1416
1356 1358
1324
1292
1260
1136
1104
(2669)
0
• ICX406
Applicable CCD image sensor
∗ The HD of this chart indicates the actual CXD3605R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
V4
V3B
V3A
V2
V1B
V1A
HD
(2669)
0
1168
MODE
Draft mode
1200 1202
Horizontal Direction Timing Chart
68
84
100
116
132
148
164
180
60
76
92
108
124
140
156
172
Chart-10
CXD3605R
– 32 –
E
1448
1464 1456
1480 1472
1496 1488
1512 1504
1528 1520
1544 1536
1560 1552
1568
1416
1292
1260
1200 1202
1168
1136
1104
(2669)
0
• ICX406
Applicable CCD image sensor
∗ The HD of this chart indicates the actual CXD3605R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
∗ The HD fall period should be between approximately 3.3 to 17.6µs (when the drive frequency is 18MHz). This chart shows a period of 115ck (6.4µs). Internal SSG is at this timing.
V4
V3B
V3A
V2
V1B
V1A
HD
(2669)
0
1324
MODE
AF1 mode, AF2 mode
1356 1358
Horizontal Direction Timing Chart
68
84
100
116
132
148
164
180
196
212
228
244
260
276
292
308
60
76
92
108
124
140
156
172
188
204
220
236
252
268
284
300
Chart-11
CXD3605R
– 33 –
XRS
XSHD
XSHP
RG
H2
H1
MCKO
ADCLK
CKO
CKI
HD'
HD
Chart-12
MODE
60
• ICX406
317
Applicable CCD image sensor
∗ HD' indicates the HD which is the actual CXD3605R load timing.
∗ The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse.
∗ The logical phase of ADCLK can be specified by the serial interface data.
1
High-Speed Phase Timing Chart
CXD3605R
– 34 –
1
050h
SMD
SHD
∗
∗
∗
∗
0
0
MODE
B
050h
1
0
B
C
050h
1
0
C
D
050h
1
0
E
Close
000h
0
3
E
MODE
Draft → Frame → Draft
This chart is a drive timing chart example of electronic shutter normal operation.
Data exposed at D includes the blooming component. For details, see the CCD image sensor data sheet.
The CXD3605R does not generate the pulse to control mechanical shutter operation.
The switching timing of drive mode and electronic shutter data is not the same.
050h
1
A
A
Vertical Direction Sequence Chart
CCD OUT
Exposure
time
Mechanical
shutter
SUB
V4
V3B
V3A
V2
V1B
V1A
VD
Chart-13
0
000h
3
E
• ICX406
1
0
050h
Open
F
Applicable CCD image sensor
050h
1
0
F
CXD3605R
CXD3605R
Application Circuit Block diagram
CCD OUT
V3A
V3B
V4
SUB
ADCLK
OBCLP
CLPDM
PBLK
XRS
XSHD
25
41
30
43
TG
CXD3605R
39
44
34
SSG
V-Dr
35
ID/EXP
WEN
CKO
MCKO
VD
HD
46
2
RST
40
3
SNCSL
47
6
SSGSL
37 48
OSCI
CKI
OSCO
26 27 28
Signal Processor Block
V2
9
31 32 33
SEN
V1B
5
SCK
V1A
13
SSI
RG
4
TEST2
H2
16 17 18 19 20 22 23
12
TEST1
H1
D OUT
CDS/ADC Block
XSHP
CCD
ICX406
Controller
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Notes for Power-on
Of the three –7.5V, +15.0V, –3.3V power supplies, be sure to start up the –7.5V and +15.0V power supplies in
the following order to prevent the SUB pin of the CCD image sensor from going to negative potential.
15.0V
t1
20%
0V
20%
t2
–7.5V
t2 ≥ t1
– 35 –
CXD3605R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 ± 0.2
∗
7.0 ± 0.1
36
S
25
13
48
B
(0.22)
0.5 ± 0.2
A
(8.0)
24
37
12
1
+ 0.05
0.127 – 0.02
0.5
+ 0.08
0.18 – 0.03
+ 0.2
1.5 – 0.1
0.13 M
0.1
S
0.5 ± 0.2
0.18 ± 0.03
0° to 10°
0.127 ± 0.04
0.1 ± 0.1
DETAIL B: PALLADIUM
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
SONY CODE
LQFP-48P-L01
LEAD TREATMENT
PALLADIUM PLATING
EIAJ CODE
P-LQFP48-7x7-0.5
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
– 36 –
Sony Corporation