CXL5005M/P CMOS-CCD 1H Delay Line for NTSC with PLL Description The CXL5005M/P are general-purpose CCD delay line ICs which provide 1H delay time of NTSC. CXL5005M 14 pin SOP (Plastic) CXL5005P 14 pin DIP (Plastic) Features • Low power consumption 90mW (Typ.) • Small size package (14-pin SOP, DIP) • Low differential gain DG = 3% (Typ.) • Input signal ampiitude 180 IRE (= 1.28Vp-p, max.) • Low input clock amplitude operation 200mVp-p (Min.) • Built-in triple PLL circuit • Built-in peripheral circuits (clock driver, timing generator, auto-bias and output circuits) Functions • 680-bit CCD register • Clock drivers • Autobias circuit • Sync tip clamp circuit • Sample-and-hold circuit • PLL (triple) Structure CMOS-CCD Absolute Maximum Ratings (Ta = 25°C) 11 V • Supply voltage VDD 6 V • Supply voltage VCL • Operating temperature Topr –10 to +60 °C • Storage temperature Tstg –55 to +150 °C • Allowable power dissipation PD CXL5005M 400 mW CXL5005P 800 mW Recommended Operating Conditions Supply voltage VDD 9 ± 5% V 5 ± 5% V VCL Recommended Clock Conditions • Input clock amplitude VCLK 200mVp-p to 1.0Vp-p (300mVp-p typ.) • Clock frequency fCLK 3.579545MHz Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. –1– E88Z40A79-PS CXL5005M/P IN AUTO FEED OUT NC CLK VCL Blook Diagram and Pin configuration 14 13 12 11 10 9 8 Auto-bias circuit Output & S/H (1 BIT) Phase comparator Clamp circuit 680 bit shift register 1/3 counter φ2 φ1 4 VCOIN VDD 5 6 7 VCOOUT 3 NC 2 VCL VSS 1 PCOUT Clock driver VCO Pin Description Pin No. Symbol Description Impedance [Ω] 1 VSS GND 2 VCL 5V power supply 3 VCOIN VCO input 4 VDD 9V power supply 5 PCOUT Phase comparator output ≈ 5k 6 NC 7 VCOOUT VCO output ≈ 5k 8 VCL 5V power supply 9 CLK Clock input ≈ 5k 10 NC 11 OUT Signal output 600 to 1k 12 FEED Feedback DC output > 100k 13 AUTO Autobias DC output ≈ 10k 14 IN Signal input > 100k > 100k –2– CXL5005M/P Electrical Characteristics (Ta = 25°C, VDD = 9.0V, VCL = 5.0V, fCLK = 3.58MHz, VCLK = 300mVp-p sine wave, See "Electrical Characteristics Test Circuit") Item Symbol SW condition Test condition Measuring point Min. A1 — 4.0 5.0 mA A2 — 9.0 12.0 mA a V1 –3.0 0.0 3.0 dB b, c b V1 –3.0 –2.1 — dB — 3.0 5.0 % e a S — 3.0 5.0 deg — — — 1.28 Vp-p V2 55 60 — dB V3 3.5 5.0 6.5 V V4 3.5 5.0 6.5 V V5 1.3 2.3 3.3 V V6 1.7 2.7 3.7 V 1 2 250kHz, 1.28Vp-p, sine wave input a a IG 250kHz, 1.28Vp-p, sine wave input IG = 20 log (Output voltage [Vp-p] / 1.28 [Vp-p]) a Frequency response fG Dissipation at 3.58MHz in relation to 250kHz fG = 20 log (V3.58MHz/ V250kHz) (Note 1) Differential gain DG 5-staircase wave input Y = 140 IRE (= 1.0Vp-p) Measure with vector scope (Note 2) Supply current Insertion gain IDD ICL Differential phase DP Allowable input amplitude Noise — — S: Input = 250kHz, 1.0Vp-p output (Vp-p) f a N: Input = DC GND output (Vrms) d a d a a a VIN-AC S/N VIN-DC DC output voltage VAUTO-DC VFEED-DC 250kHz, 1.28Vp-p, VOUT-DC sine wave input –3– Typ. Max. Unit f. 250kHz, 1.0Vp-p sine wave e. 5-staircase wave d. Ground c. 3.58MHz, 300mVp-p sine wave 0.1µF V3 1M a VBIAS 100k b SW2 –4– 5V A2 2 1 9V 0.1µF A1 56k 7 6 5 4 8 9 0.01µF 3 CXL5005M/P 10 11 12 13 14 1500 V6 2SA1175 5600 Note 4) Note 3) V1 BPF LPF 9V CLK fCLK = 3.58MHz VCLK = 300mVp-p sine wave VCOIN b. 250kHz, 300mVp-p sine wave SW1 V5 IN VDD a. 250kHz, 1.28Vp-p sine wave 0.1µF AUTO VSS FEED VCL OUT V4 0.1µF NC PCOUT CLK NC VCL VCOOUT Electrical Characteristics Test Circuit V2 Vector scope S CXL5005M/P CXL5005M/P Note 1) Frequency response test condition V3.58MHz (Output signal voltage [Vp-p] at 3.58MHz input) V250kHz (Output signal voltage [Vp-p] at 250kHz input) Set Pin 14 (IN) voltage [V] = VIN-DC + 640mV. [V] 3.58MHz, 300mVp-p sine wave 250kHz, 300mVp-p sine wave 640mV (adjust with VBIAS) VIN-DC Note 2) Differential gain and differential phase test condition 5-staircase wave signal Chroma 40 IRE 140 IRE (1.0Vp-p) 40 IRE 1H 63.5µs DG and DP are measured at output S point by vector scope. Note 3) LPF frequency response (Delay time [dB] Note 4) BPF frequency response 140ns) 0 –3 [dB] 0 –3 –50 –50 0 5.8 10.7 0 50 200 Frequency [MHz] 4.1M 10.7M Frequency [Hz] –5– CXL5005M/P fCLK = 3.58MHz CLK VCLK = 300mVp-p sine wave Application Circuit 9V 5600 0.1µF 0.01µF 0.1µF 0.1µF L. P. F 2SA1175 Composite video signal input 1H delay signal output Delay time 14 13 12 9 10 11 140ns 8 1M 5V CXL5005M/P 1 2 3 6 5 4 Example of Pin 7 (VCO output) usage 7 +9V 1500 56k 5V 5.6k 9V 2SC403 7 3 × fsc 5.6k 0.1µF Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. Example of Representative Characteristics Frequency response vs. Ambient temperature Input = 300mVp-p 3.58MHz, sine wave Input = 300mVp-p 3.58MHz, sine wave 0 fG – Frequency response [dB] 0 fG – Frequency response [dB] Frequency response vs. Supply voltage –1 –2 –3 –4 –1 –2 –3 –4 –20 0 20 40 60 4.7 Ta – Ambient temperature [°C] Input = 300mVp-p 3.58MHz, sine wave 1 IG – Insertion gain [dB] fG – Frequency response [dB] Insertion gain vs. Ambient temperature –1 –2 –3 –4 8.5 5.3 VCL – Supply voltage [V] Frequency response vs. Supply voltage 0 5.0 Input = 1.28Vp-p 250kHz, sine wave 0 –1 –2 –3 9.0 VDD – Supply voltage [V] 9.5 –20 –6– 0 20 40 60 Ta – Ambient temperature [°C] CXL5005M/P Insertion gain vs. Supply voltage Input = 1.28Vp-p 250kHz, sine wave 0 –1 –2 –3 0 –1 –2 –3 4.7 5.0 5.3 VCL – Supply voltage [V] 8.5 9.0 VDD – Supply voltage [V] Differential gain vs. Supply voltage 4 4 DG – Differential gain [%] DG – Differential gain [%] Differential gain vs. Ambient temperature 3 2 3 2 1 1 0 –20 Input = 1.28Vp-p 250kHz, sine wave 1 IG – Insertion gain [dB] 1 IG – Insertion gain [dB] Insertion gain vs. Supply voltage 0 20 40 0 60 4.7 Ta – Ambient temperature [°C] 5.0 5.3 VCL – Supply voltage [V] Differential gain vs. Supply voltage Frequency response 4 –1 Gain [dB] DG – Differential gain [%] 0 3 Ta = 25°C –2 –3 2 –4 10k 1 0 8.5 9.0 VDD – Supply voltage [V] 9.5 –7– 100k Frequency [Hz] 1M 9.5 CXL5005M/P Package Outline Unit: mm CXL5005M 14PIN SOP (PLASTIC) + 0.4 1.85 – 0.15 + 0.4 9.9 – 0.1 14 8 6.9 + 0.2 0.1 – 0.05 7 0.45 ± 0.1 0.5 ± 0.2 1 7.9 ± 0.4 + 0.3 5.3 – 0.1 0.15 + 0.1 0.2 – 0.05 1.27 0.24 M PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE SOP-14P-L01 LEAD TREATMENT SOLDER PLATING EIAJ CODE SOP014-P-0300 LEAD MATERIAL 42/COPPER ALLOY PACKAGE MASS 0.2g JEDEC CODE CXL5005P + 0.1 05 0.25 – 0. 14PIN DIP (PLASTIC) 8 7.62 14 + 0.3 6.4 – 0.1 + 0.4 19.2 – 0.1 1 0° to 15° 7 0.5 ± 0.1 + 0.4 3.7 – 0.1 3.0 MIN 0.5 MIN 2.54 1.2 ± 0.15 PACKAGE STRUCTURE PACKAGE MATERIAL EPOXY RESIN SONY CODE DIP-14P-01 LEAD TREATMENT SOLDER PLATING EIAJ CODE DIP014-P-0300 LEAD MATERIAL 42/COPPER ALLOY JEDEC CODE Similar to MO-001-AH PACKAGE MASS 0.9g –8–