CYPRESS CY24271ZXC

CY24271
Rambus® XDR™ Clock Generator
Features
■
Meets Rambus® Extended Data Rate (XDR™) clocking
requirements
■
25 ps typical cycle-to-cycle jitter
❐ 135 dBc/Hz typical phase noise at 20 MHz offset
■
100 or 133 MHz differential clock input
■
300–800 MHz high speed clock support
■
Quad (open drain) differential output drivers
■
Supports frequency multipliers: 3, 4, 5, 6, 8, 9/2, 15/2, and 15/4
■
Spread Aware™
■
2.5V operation
■
28-pin TSSOP package
Logic Block Diagram
/B Y P A S S
EN
EN
R egA
CLK0
C LK 0B
EN
R egB
CLK1
B ypass
MUX
C LK 1B
EN
R egC
PLL
R E F C L K ,R E F C L K B
CLK2
C LK 2B
EN
R egD
CLK3
C LK 3B
SCL
Cypress Semiconductor Corporation
Document Number: 001-00411 Rev. *B
SDA
•
ID 0
ID 1
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised July 23, 2007
[+] Feedback
CY24271
Pinouts
Figure 1. Pin Diagram - 28 Pin TSSOP
VD DP
VSS P
ISET
VSS
REFC LK
VDD C
V SSC
SC L
S DA
EN
ID0
ID 1
/BY PASS
CY24271
R EFC LKB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
CLK0
CLK0B
VSS
CLK1
CLK1B
VDD
V SS
CLK2
CLK2B
VSS
CLK3
CLK3B
VD D
Table 1. Pin Definition - 28 Pin TSSOP
Pin No.
Name
IO
Description
1
VDDP
PWR
2.5V power supply for phased lock loop (PLL)
2
VSSP
GND
Ground
3
ISET
I
4
VSS
GND
5
REFCLK
I
Reference clock input (connect to clock source)
6
REFCLKB
I
Complement of reference clock (connect to clock source)
7
VDDC
PWR
2.5V power supply for core
8
VSSC
GND
Ground
9
SCL
I
SMBus clock (connect to smbus)
10
SDA
I
SMBus data (connect to smbus)
11
EN
I
Output Enable (CMOS signal)
12
ID0
I
Device ID (CMOS signal)
Set clock driver current (external resistor)
Ground
13
ID1
I
Device ID (CMOS signal)
14
/BYPASS
I
REFCLK bypassing PLL (CMOS signal)
15
VDD
PWR
Power supply for outputs
16
CLK3B
O
Complement clock output
17
CLK3
O
18
VSS
GND
19
CLK2B
O
Complement clock output
20
CLK2
O
Clock output
Clock output
Ground
21
VSS
GND
Ground
22
VDD
PWR
Power supply for outputs
23
CLK1B
O
Complement clock output
24
CLK1
O
Clock output
25
VSS
GND
26
CLK0B
O
27
CLK0
O
28
VDD
PWR
Document Number: 001-00411 Rev. *B
Ground
Complement clock output
Clock output
Power supply for outputs
Page 2 of 13
[+] Feedback
CY24271
PLL Multiplier
Table 2 shows the frequency multipliers in the PLL, selectable by programming the SMBus registers MULT0, MULT1, and MULT2.
Default multiplier at power up is 4.
Table 2. PLL Multiplier Selection
Register
MULT2
MULT1
MULT0
0
0
0
Frequency Multiplier
Output Frequency (MHz)
[1]
REFCLK = 100 MHz , REFSEL = 0 REFCLK = 133 MHz[1], REFSEL = 1
3
300
400
533[3]
667
0
0
1
4
400[2]
0
1
0
5
500
0
1
1
6
600
800
1
0
0
8
800
1067[3]
1
0
1
9/2
450
600
1
1
0
15/2
750
1000[3]
1
1
1
15/4
375
500
Device ID and SMBus Device Address
The device ID (ID0 and ID1) is a part of the SMBus device 8-bit
address. The least significant bit of the address designates a
write or read operation. Table 3 shows the addresses for four
CY24271 devices on the same SMBus.
Modes of Operation
The modes of operation are determined by the logic signals
applied to the EN and /BYPASS pins and the values in the five
SMBus Registers: RegTest, RegA, RegB, RegC, and RegD.
Table 4 shows selection from one to all four of the outputs, the
Outputs Disabled Mode (EN = low), and Bypass Mode (EN =
high, /BYPASS = low). There is an option reserved for vendor
test. Disabled outputs are set to High Z.
At power up, the SMBus registers default to the last entry in
Table 4. The value at RegTest is 0. The values at RegA, RegB,
RegC, and RegD are all ‘1’. Thus, all outputs are controlled by
the logic applied to EN and /or BYPASS.
Table 3. SMBus Device Addresses for CY24271
XCG
Device
0
1
2
3
Operation
Hex
Address
Write
D8
Read
D9
Write
DA
Read
DB
Write
DC
Read
DD
Write
DE
Read
DF
8-bit SMBus Device Address Including Operation
Five Most Significant Bits
1
1
0
1
ID1
ID0
0
0
0
1
1
0
1
1
1
WR# / RD
0
1
0
1
0
1
0
1
Notes
1. Output frequencies shown in Table 2 are based on nominal input frequencies of 100 MHz and 133.3 MHz. The PLL multipliers are applicable to spread spectrum
modulated input clock with maximum and minimum input cycle time. The REFSEL bit in SMBus 81h is set correctly as shown.
2. Default PLL multiplier at power up.
3. Contact the factory if operation at these frequencies is required.
Document Number: 001-00411 Rev. *B
Page 3 of 13
[+] Feedback
CY24271
Table 4. Modes of Operation for CY24271
EN
/BYPASS RegTest RegA RegB RegC RegD CLK0/CLK0B
X
X
X
X
H
X
1
X
X
X
X
H
L
0
X
X
X
X
REFCLK/
REFCLKB[4]
REFCLK/
REFCLKB
REFCLK/
REFCLKB
REFCLK/
REFCLKB
H
H
0
0
0
0
0
High Z
High Z
High Z
High Z
H
H
0
0
0
0
1
High Z
High Z
High Z
CLK/CLKB
H
H
0
0
0
1
0
High Z
High Z
CLK/CLKB
High Z
H
H
0
0
0
1
1
High Z
High Z
CLK/CLKB
CLK/CLKB
H
H
0
0
1
0
0
High Z
CLK/CLKB
High Z
High Z
H
H
0
0
1
0
1
High Z
CLK/CLKB
High Z
CLK/CLKB
H
H
0
0
1
1
0
High Z
CLK/CLKB
CLK/CLKB
High Z
H
H
0
0
1
1
1
High Z
CLK/CLKB
CLK/CLKB
CLK/CLKB
H
H
0
1
0
0
0
CLK/CLKB
High Z
High Z
High Z
H
H
0
1
0
0
1
CLK/CLKB
High Z
High Z
CLK/CLKB
H
H
0
1
0
1
0
CLK/CLKB
High Z
CLK/CLKB
High Z
H
H
0
1
0
1
1
CLK/CLKB
High Z
CLK/CLKB
CLK/CLKB
H
H
0
1
1
0
0
CLK/CLKB
CLK/CLKB
High Z
High Z
H
H
0
1
1
0
1
CLK/CLKB
CLK/CLKB
High Z
CLK/CLKB
H
H
0
1
1
1
0
CLK/CLKB
CLK/CLKB
CLK/CLKB
High Z
H
0[5]
1[5]
1[5]
1[5]
1[5]
CLK/CLKB
CLK/CLKB
CLK/CLKB
CLK/CLKB
SMBus Protocol
The CY24271 is a slave receiver supporting operations in the
word and byte modes described in sections 5.5.4 and 5.5.5 of
the SMBus Specification 2.0.
DC specifications are modified to RAMBUS standard to support
1.8, 2.5, and 3.3 volt devices. Time-out detection and packet
error protocol SMBus features are not supported.
Input Clock Signal
The XCG receives either a differential (REFCLK/REFCLKB) or a
single-ended reference clocking input (REFCLK).
When the reference input clock is from a different clock source,
it must meet the voltage levels and timing requirements listed in
DC Operating Conditions on page 7 and AC Operating Conditions on page 8.
High Z
High Z
CLK2/CLK2B CLK3/CLK3B
X
H
X
CLK1/CLK1B
L
High Z
High Z
Reserved for Vendor Test
For a single-ended clock input, an external voltage divider and a
supply voltage, as shown in Figure 2, provide a reference
voltage VTH at the REFCLKB pin. This determines the proper trip
point of REFCLK. For the range of VTH specified in DC Operating
Conditions on page 7, the outputs also meet the DC and AC
Operating Conditions tables.
SMBus Data Byte Definitions
Three data bytes are defined for the CY24271. Byte 0 is for
programming the PLL multiplier registers and clock output
registers.
The definition of Byte 2 is shown in Table 5, Table 6, and Table 7
on page 5. The upper five bits are the revision numbers of the
device and the lower three bits are the ID numbers assigned to
the vendor by Rambus.
Notes
4. Bypass Mode: REFCLK bypasses the PLL to the output drivers.
5. Default mode of operation is at power up.
Document Number: 001-00411 Rev. *B
Page 4 of 13
[+] Feedback
CY24271
Table 5. Command Code 80h[6]
Bit
Register
POD
Type
Description
7
Reserved
0
RW
Reserved (no internal function)
6
MULT2
0
RW
PLL Multiplier Select
5
MULT1
0
RW
4
MULT0
1
RW
3
RegA
1
RW
Clock 0 Output Select
2
RegB
1
RW
Clock 1 Output Select
1
RegC
1
RW
Clock 2 Output Select
0
RegD
1
RW
Clock 3 Output Select
Table 6. Command Code 81h[6]
Bit
Register
POD
Type
7
Reserved
0
RW
6
Reserved
0
RW
5
Reserved
0
RW
4
Reserved
0
RW
3
Reserved
1
RW
Description
Reserved (no internal function)
Reserved (must be set to ‘1’ for proper operation)
2
REFSEL
0
RW
Reference Frequency Select (reference Table 2)
1
Reserved
0
RW
Reserved (must be set to ‘0’ for proper operation)
0
RegTest
0
RW
Reserved (must be set to ‘0’ for proper operation)
Table 7. Command Code 82h[6]
Bit
Register
POD
Type
7
Device
Revision
Number
?
RO
?
RO
?
RO
4
?
RO
3
?
RO
6
5
2
0
RO
1
Vendor ID
1
RO
0
0
RO
Description
Contact factory for Device Revision Number information.
RAMBUS assigned Vendor ID Code
Note
6. RW = Read and Write, RO = Read Only, POD = Power on default. See Table 2 for PLL multipliers and Table 4 for clock output selections.
Document Number: 001-00411 Rev. *B
Page 5 of 13
[+] Feedback
CY24271
Figure 2. Differential and Single-Ended Clock Inputs
Supply Voltage
V TH
REFCLKB
Input
Input
REFCLK
REFCLK
XDR Clock Generator
XDR Clock Generator
Differential Input
Single-ended Input
Absolute Maximum Conditions
Parameter
Description
Condition
Min
Max
Unit
–0.5
4.6
V
VDD
Clock Buffer Supply Voltage
VDDC
Core Supply Voltage
–0.5
4.6
V
VDDP
PLL Supply Voltage
–0.5
4.6
V
VIN
Input Voltage (SCL and SDA)
Relative to VSS
–0.5
4.6
V
Input Voltage (REFCLK/REFCLKB)
Relative to VSS
–0.5
VDD + 1.0
V
Input Voltage
Relative to VSS
–0.5
VDD + 0.5
V
TS
Temperature, Storage
Non-functional
–65
150
°C
TA
Temperature, Operating Ambient
Functional
0
70
°C
TJ
Temperature, Junction
Functional
–
150
°C
ESDHBM
ESD Protection (Human Body Model) MIL-STD-883, Method 3015
2000
–
V
Document Number: 001-00411 Rev. *B
Page 6 of 13
[+] Feedback
CY24271
DC Operating Conditions
Parameter
Description
Condition
Min
Max
Unit
2.375
2.625
V
VDDP
Supply Voltage for PLL
VDDC
Supply Voltage for Core
2.5V ± 5%
2.375
2.625
V
VDD
Supply Voltage for Clock Buffers
2.5V ± 5%
2.375
2.625
V
VIHCLK
Input High Voltage, REFCLK/REFCLKB
0.6
0.95
V
VILCLK
Input Low Voltage, REFCLK/REFCLKB
–0.15
+0.15
V
VIXCLK[7]
ΔVIXCLK[7]
Crossing Point Voltage, REFCLK/REFCLKB
200
550
mV
–
150
mV
VIH
Input Signal High Voltage at ID0, ID1, EN, and /BYPASS
1.4
2.625
V
VIL
Input Signal Low Voltage at ID0, ID1, EN, and /BYPASS
–0.15
0.8
V
VIH,SM
Input Signal High Voltage at SCL and SDA[8]
VIL,SM
Input Signal Low Voltage at SCL and SDA
VTH[9]
Input Threshold Voltage for single-ended REFCLK
VIH,SE
Input Signal High Voltage for single-ended REFCLK
VIL,SE
Input Signal Low Voltage for single-ended REFCLK
–0.15
VTH – 0.3
V
TA
Ambient Operating Temperature
0
70
°C
Difference in Crossing Point Voltage, REFCLK/REFCLKB
2.5V ± 5%
1.4
3.465
V
–0.15
0.8
V
0.35
0.5VDD
V
VTH + 0.3
2.625
V
Notes
7. Not 100% tested except VIXCLK and ΔVIXCLK. Parameters guaranteed by design and characterizations, not 100% tested in production.
8. This range of SCL and SDA input high voltage enables the 3.3V, 2.5V, or 1.8V SMBus voltages to use CY24271.
9. Single-ended operation guaranteed only when 0.8 < (VIH,SE – VTH)/(VTH – VIL,SE) < 1.2.
Document Number: 001-00411 Rev. *B
Page 7 of 13
[+] Feedback
CY24271
AC Operating Conditions
The AC operating conditions follow.[7]
Parameter
tCYCLE,IN
Description
Condition
REFCLK, REFCLKB input cycle time
Min
Max
Unit
REFSEL = 0, /BYPASS = High
9
11
ns
REFSEL = 1, /BYPASS = High
7
8
ns
/BYPASS = Low
4
–
ns
–
185
ps
Over 10,000 cycles
40%
60%
tCYCLE
Measured at 20%–80% of input
voltage for REFCLK and
REFCLKB inputs
175
700
ps
Rise and Fall Times Difference
–
150
ps
Modulation Index for triangular modulation
–
0.6
%
%
tJIT,IN(cc)
Input Cycle to Cycle Jitter[10]
tDCIN[11]
Input Duty Cycle
tRIN / tFIN
Rise and Fall Times
ΔtRIN / tFIN
pMIN[12]
Modulation Index for non-triangular modulation
–
0.5[13]
fMIN[12]
Input Frequency Modulation
30
33
kHz
tSR,IN
Input Slew Rate (measured at 20%–80% of
input voltage) for REFCLK
1
4
V/ns
CIN,REF
Capacitance at REFCLK inputs
–
7
pF
CIN,CMOS
Capacitance at CMOS inputs
–
10
pF
fSCL
SMBus clock frequency input in SCL pin
DC
100
kHz
Typ
Max
Unit
DC Electrical Specifications
Parameter
Description
Min
voltage[14]
VOX[7]
VCOS[7]
Differential output crossing point
0.9
1.0
1.1
V
Output voltage swing (peak-to-peak single-ended)[15]
300
325
350
mV
VOL,ABS
Absolute output low voltage at CLK[3:0], CLK[3:0]B[16]
0.85
–
–
V
VISET
Reference voltage for swing controlled current, IREF
0.98
1.0
1.02
V
IDD[7]
Power Supply Current at 2.625V, fref = 100 MHz, and fout = 300 MHz
–
–
85
mA
IDD[7]
Power Supply Current at 2.625V, fref = 133 MHz, and fout = 667 MHz
–
–
125
mA
IDD[7]
Power Supply Current at 2.625V, fref = 133 MHz, and fout = 800 MHz
–
–
130
mA
IOL/IREF
Ratio of output low current to reference current[17]
6.8
7.0
7.2
IOL,ABS
Minimum current at VOL,ABS[18]
45
–
–
mA
VOL,SDA
SDA output low voltage at test condition of SDA output low current = 4 mA
–
–
0.4
V
IOL,SDA
SDA output low voltage at test condition of SDA voltage = 0.8V
6
–
–
mA
IOZ
Current during High Z per pin at CLK[3:0], CLK[3:0]B
–
–
10
μA
1000
–
–
Ω
ZOUT
Output dynamic impedance when clock output signal is at VOL = 0.9V
[19]
Notes
10. Jitter measured at crossing points and is the absolute value of the worst case deviation.
11. Measured at crossing points.
12. If input modulation is used; input modulation is allowed but not required.
13. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew that cannot exceed the skew generated
by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.
14. VOX is measured on external divider network.
15. VCOS = (clock output high voltage – clock output low voltage), measured on the external divider network.
16. VOL_ABS is measured at the clock output pins of the package.
17. IREF is equal to VISET/RRC.
18. Minimum IOL,ABS is measured at the clock output pin with RRC = 148 ohms or less.
19. ZOUT is defined at the output pins as (0.94V – 0.90V)/(I0.94 – I0.90) under conditions specified for IOL, ABS.
Document Number: 001-00411 Rev. *B
Page 8 of 13
[+] Feedback
CY24271
AC Electrical Specification
The AC Electrical specifications follow. [7]
Parameter
tCYCLE
tJIT(cc)
Description
Min
Clock Cycle time[20]
Typ
1.25
[21]
Max
Unit
3.34
ns
Jitter over 1-6 clock cycles at 400–635 MHz
–
25
40
ps
Jitter over 1-6 clock cycles at 638–800 MHz
–
25
30
ps
L20
Phase noise SSB spectral purity L(f) at 20 MHz offset: 400–500 MHz
(In addition, device must not exceed L(f) = 10log[1+(50x106/f)2.4] –138 for
f = 1 MHz to 100 MHz except for the region near f = REFCLK/Q where Q is
the value of the internal reference divider.)
–
–135
–128
dBC/Hz
533 MHz and faster output
–
–
TBD
tJIT(hper,cc)
Cycle-to-cycle duty cycle error at 400–635 MHz
–
25
40
ps
Cycle-to-cycle duty cycle error at 636–800 MHz
–
25
30
ps
ΔtSKEW
Drift in tSKEW when ambient temperature varies between 0°C and 70°C and
supply voltage varies between 2.375V and 2.625V.[22]
–
–
15
ps
DC
Long term average output duty cycle
45%
50
55%
tCYCLE
tEER,SCC
PLL output phase error when tracking SSC
–100
–
100
ps
tCR,tCF
Output rise and fall times at 400–800 MHz (measured at 20%–80% of output
voltage)
120
–
300
ps
tCR,CF
Difference between output rise and fall times on the same pin of the single
device (20%–80%) of 400–800 MHz[23]
–
–
100
ps
Test and Measurement Setup
Figure 3. Clock Outputs
V TS
Measurement
R 1 Point
VT
CLK
R2
Swing Current
Control
Differential Driver
Z CH
RT
R3
ISET
V TS
Measurement
R 1 Point
VT
CLKB
R2
Z CH
RT
R3
Notes
20. Max and min output clock cycle times are based on nominal outputs frequency of 300 and 800 MHz, respectively. For spread spectrum modulated differential or
single-ended REFCLK, the output clock tracks the modulation of the input.
21. Output short term jitter spec is the absolute value of the worst case deviation.
22. tSKEW is the timing difference between any two of the four differential clocks and is measured at common mode voltage. ΔtSKEW is the change in tSKEW when the
operating temperature and supply voltage change.
23. tCR,CF applies only when appropriate RRC and output resistor network resistor values are selected to match pull up and pull down currents.
Document Number: 001-00411 Rev. *B
Page 9 of 13
[+] Feedback
CY24271
Example External Resistor Values
and Termination Voltages for a 50Ω Channel
Parameter
Value
Unit
R1
39.2
Ω
R2
66.5
Ω
R3
93.1
Ω
RT
49.9
Ω
RRC
200
Ω
VTS
2.5V
V
VT
1.2V
V
the 20% and 80% points of the voltage swing, with the swing
defined as VH–VL.
Figure 5 shows the definition of the output crossing point. The
nominal crossing point between the complementary outputs is
defined as the 50% point of the DC voltage levels. There are two
crossing points defined: Vx+ at the rising edge of CLK and Vx–
at the falling edge of CLK. For some waveforms, both Vx+ and
Vx– are below Vx,nom (for example, if tCR is larger than tCF).
Jitter
Signal Waveforms
A physical signal that appears at the pins of a device is deemed
valid or invalid depending on its voltage and timing relations with
other signals. Input and output voltage waveforms are defined as
shown in Figure 4. Both rise and fall times are defined between
This section defines the specifications that relate to timing uncertainty (or jitter) of the input and output waveforms. Figure 6
shows the definition of cycle-to-cycle jitter with respect to the
falling edge of the CLK signal. Cycle-to-cycle jitter is the
difference between cycle times of adjacent cycles. Equal requirements apply rising edges of the CLK signal. Figure 7 shows the
definition of cycle-to-cycle duty cycle error (tDC,ERR).
Cycle-to-cycle duty cycle is defined as the difference between
tPW+ (high times) of adjacent differential clock cycles. Equal
requirements apply to tPW-, low times of the differential click
cycles.
Figure 4. Input and Output Waveforms
VH
80%
V (t)
20%
VL
tF
tR
Figure 5. Crossing Point Voltage
CLK
Vx+
Vx.nom
Vx-
CLKB
Document Number: 001-00411 Rev. *B
Page 10 of 13
[+] Feedback
CY24271
Figure 6. Cycle-to-cycle Jitter
CLK
CLKB
tCYCLE,i
tCYCLE,i+1
tJ = tCYCLE,i - tCYCLE,i+1 over 10,000 consecutive cycles
Figure 7. Cycle-to-cycle Duty-cycle Error
CLK
CLKB
tPW-(i)
tCYCLE,(i)
tPW+(i)
tPW-(i+1)
tPW+(i+1)
tCYCLE,(i+1)
tDC,ERR = tPW-(i) - tPW-(i+1) and tPW-(i+1) - tPW+(i+1)
Document Number: 001-00411 Rev. *B
Page 11 of 13
[+] Feedback
CY24271
Ordering Information
Part Number
Package Type
Product Flow
Pb-Free
CY24271ZXC
28-pin TSSOP
Commercial, 0°C to 70°C
CY24271ZXCT
28-pin TSSOP – Tape and Reel
Commercial, 0°C to 70°C
Package Drawing and Dimension
Figure 8. 28-Pin Thin Shrunk Small Outline Package (4.40-mm Body) Z29
PIN 1 ID
1
4.30[0.169]
4.50[0.177]
6.25[0.246]
6.50[0.256]
28
0.65[0.025]
BSC.
0.19[0.007]
0.30[0.012]
1.10[0.043] MAX.
0.25[0.010]
BSC
GAUGE
PLANE
0°-8°
0.076[0.003]
0.85[0.033]
0.95[0.037]
9.60[0.378]
9.80[0.386]
0.05[0.002]
0.15[0.006]
SEATING
PLANE
0.50[0.020]
0.70[0.027]
0.09[[0.003]
0.20[0.008]
51-85120-*A
Document Number: 001-00411 Rev. *B
Page 12 of 13
[+] Feedback
CY24271
Document History Page
Document Title: CY24271 Rambus XDR Clock Generator
Document Number: 001-00411
REV.
ECN NO.
Issue
Date
Orig. of
Change
**
378263
See ECN
RGL
*A
492065
See ECN KKVTMP 1) New Pin definition table
2) Throughout the data sheet
Change all instances of VSSC from VSSC to VSS
Change all instances of VSSB from VSSB to VSSC
Change all instances of SCLK from SCLK to SCL
Change all instances of SDATA from SDATA to SDA
Change all instances of BYPASSB from BYPASSB to /BYPASS
Change all instances of VDDO from VDDO to VDD
Change all instances of VSSO from VSSO to VSS
Change all instances of VSSG from VSSG to VSS
*B
1333483
See ECN FGA/SFV Added IDD values in DC Electrical Specifications table
Description of Change
New data sheet
© Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any
circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical,
life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical
components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-00411 Rev. *B
Revised July 23, 2007
Page 13 of 13
PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered
trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the
Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. Spread Aware is a trademark of Cypress
Semiconductor Corporation. Rambus is a registered trademark, and XDR is a trademark, of Rambus Inc. All products and company names mentioned in this document may be the trademarks of their
respective holders.
[+] Feedback