CY28517 PCI Express Clock Generator Features ■ Four 100 MHz differential clocks ■ 48 MHz clock ■ Two 25 MHz clocks ■ 27 MHz Reference Clock ■ OE control per clock output ■ ■ Selectable, Triangle, and Lexmark profiles ■ SMbus support with readback capabilities ■ 3.3V power supply ■ Packages are Pb free and ROHS compliant ■ 28-pin TSSOP packages Selectable drive strength per output 100M 25M 27M 48M x4 x2 x1 x1 Logic Block Diagram OE_100_25 X1/CLK 27M XTAL OSC X2 100MT[A:D] PLL1 100MC[A:D] RSET 48M PLL2 25M[A:B] PLL3 SDATA SCLK SMBus Logic Cypress Semiconductor Corporation Document #: 001-42225 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 02, 2007 [+] Feedback CY28517 Pinouts Figure 1. Pin Diagram - 28 Pin TSSOP 1 28 2 27 SCLK X2 3 26 SDAT A VSSX 4 25 VSS48 VDD25M 5 24 48M 25MA 6 23 VDD48 25MB 7 22 VDD100 OE_100_25 8 VSS25 9 100MC_C CY28517 VDDX X1/ICLK 10 27M 21 VSS100 20 RSET 19 100MC_A 100MT _C 11 18 100MT _A VSS100 12 17 VDD100 100MC_D 13 16 100MC_B 100MT _D 14 15 100MT _B Table 1. Pin Definitions - 28 Pin TSSOP Pin No. Name Type Description 1 VDDX PWR 3.3V Power Supply for XTAL and REF 2 X1/ICLK I 27 MHz Crystal Input/ Clock Input 3 X2 O, SE 27 MHz Crystal Output 4 VSSX PWR Ground for XTAL and REF 5 VDD25 PWR 3.3V Power Supply for 25 MHz Outputs 6,7 25M[A:B] O, SE 25 MHz Clock 8 OE_100_25 I, PD Input for Enabling/Disabling 25 MHz [A:B] and 100 MHz [A:D] Clock. It is a high true signal and has an internal pull down resistor with value >100 KOhms. 9 VSS25 PWR Ground for 25 MHz Outputs 10, 11, 13, 14, 100MT/C[A:D] 15, 16, 18, 19 O, DIF Differential 100 MHz Clocks Intel Type-X buffer. 12, 21 VSS100 PWR Ground for 100 MHz Outputs 17, 22 VDD100 PWR 3.3V Power Supply for 100 MHz Outputs 20 RSET I A Precision resistor is attached to this pin, which is connected to the internal current reference 23 VDD48 PWR 3.3V Power Supply for 48 MHz Outputs 24 48M O, SE 48 MHz Clock 25 VSS25 PWR Ground for 48 MHz Outputs 26 SDATA IO SMBus Compatible SDATA 27 SCLK I SMBus Compatible SCLOCK 28 27M O, SE Reference Clock. 3.3V 27 MHz clock output Document #: 001-42225 Rev. *A Page 2 of 12 [+] Feedback CY28517 Serial Data Interface Data Protocol To enhance the flexibility and function of the clock synthesizer, a two signal serial interface is provided. Through the Serial Data Interface, various device functions, such as individual clock output buffers, can be individually enabled or disabled. The registers associated with the Serial Data Interface initialize to their default setting upon power up, and therefore use of this interface is optional. Clock device register changes are normally made upon system initialization, if any are required. This is a RAM based technology which does not keep its value when power is off or during a power transition. The clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. For block write or read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. For byte write and byte read operations, the system controller can access individually indexed bytes. The offset of the indexed byte is encoded in the command code, as described in Table 2. The block write and block read protocol is outlined in Table 3 while Table 4 on page 4 outlines the corresponding byte write and byte read protocol. The slave receiver address is 11010010 (D2h) for write and 11010011(D3h) for read. Table 2. Command Code Definition Bit 7 (6:0) Description 0 = Block read or block write operation, 1 = Byte read or byte write operation Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000' Table 3. Block Read and Block Write Protocol Block Write Protocol Bit Block Read Protocol Description Bit Description 1 Start 1 Start 2:8 Slave address – 7 bits 2:8 Slave address – 7 bits 9 Write 9 Write 10 Acknowledge from slave 10 Acknowledge from slave 11:18 Command Code – 8-bit ‘00000000’ stands for block 11:18 operation Command Code – 8-bit ‘00000000’ stands for block operation 19 Acknowledge from slave 19 Acknowledge from slave 20:27 Byte Count – 8 bits 20 Repeat start 28 Acknowledge from slave 21:27 Slave address – 7 bits 29:36 Data byte 0 – 8 bits 28 Read 37 Acknowledge from slave 29 Acknowledge from slave 38:45 Data byte 1 – 8 bits 30:37 Byte count from slave – 8 bits 46 Acknowledge from slave 38 Acknowledge Data Byte N/Slave Acknowledge... 39:46 Data byte from slave – 8 bits Data Byte N – 8 bits 47 Acknowledge Acknowledge from slave 48:55 Data byte from slave – 8 bits Stop 56 Acknowledge Data bytes from slave/Acknowledge Data byte N from slave – 8 bits Not Acknowledge Stop Document #: 001-42225 Rev. *A Page 3 of 12 [+] Feedback CY28517 Table 4. Byte Read and Byte Write Protocol Byte Write Protocol Bit Byte Read Protocol Description Bit Description 1 Start 1 Start 2:8 Slave address – 7 bits 2:8 Slave address – 7 bits 9 Write = 0 9 Write = 0 10 Acknowledge from slave 10 11:18 Command Code – 8 bits ‘1xxxxxxx’ stands for byte 11:18 operation, bits[6:0] of bits[6:0] the command code represents the offset of the byte to be accessed Acknowledge from slave Command Code – 8 bits ‘1xxxxxxx’ stands for byte operation, of the command code represents the offset of the byte to be accessed 19 Acknowledge from slave 19 Acknowledge from slave 20:27 Data byte from master – 8 bits 20 Repeat start 28 Acknowledge from slave 21:27 Slave address – 7 bits 29 Stop 28 Read = 1 29 Acknowledge from slave 30:37 Data byte from slave – 8 bits 38 Not Acknowledge 39 Stop Control Registers Byte 0:Control Register 0 Bit @Pup 7 1 27M Name 27M Output Enable 0 = Disable (Hi-Z), 1 = Enable Description 6 1 48M 48M Output Enable 0 = Disable (Hi-Z), 1 = Enable 5 1 25M_B 25M_B Output Enable 0 = Disable (Hi-Z), 1 = Enable 4 1 25M_A 25M_A Output Enable 0 = Disable (Hi-Z), 1 = Enable 3 1 100M[T/C]D 100M[T/C]D Output Enable 0 = Disable (Hi-Z), 1 = Enable 2 1 100M[T/C]C 100M[T/C]C Output Enable 0 = Disable (Hi-Z), 1 = Enable 1 1 100M[T/C]B 100M[T/C]B Output Enable 0 = Disable (Hi-Z), 1 = Enable 0 1 100M[T/C]A 100M[T/C]A Output Enable 0 = Disable (Hi-Z), 1 = Enable Byte 1: Control Register 1 Bit @Pup 7 1 100M_D_Drive Strength Name Choose 100M[A;D] RSET Multiplier 0 - 2X, 1 - 6X 6 0 Reserved Reserved, Set = 0 5 0 Reserved Reserved, Set = 0 4 0 Reserved Reserved, Set = 0 3 0 Reserved Reserved, Set = 0 Document #: 001-42225 Rev. *A Description Page 4 of 12 [+] Feedback CY28517 Byte 1: Control Register 1 (continued) Bit @Pup 2 0 1 0 0 0 Name Description Spread Control Bit2 Bit1 0 0 1 1 100M Spread Enable 0 1 0 1 Spread Value -0.35 Triangular -0.50 Triangular -0.35 Lexmark -0.50 Lexmark PLL1 Spread Spectrum Enable 0 = Spread off, 1 = Spread on Byte 2: Control Register 2 Bit @Pup 7 0 Reserved Name Reserved Description 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Byte 3: Control Register 3 Bit @Pup 7 0 Reserved Name Reserved Description 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Byte 4: Control Register 4 Bit @Pup 7 1 Reserved Name Reserved 6 1 Reserved Reserved 5 1 Reserved Reserved 4 1 Reserved Reserved 3 1 Reserved Reserved 2 1 VCO Frequency Control Must set this bit to 0 after power up to ensure proper operation of the device 1 0 Reserved Reserved 0 0 Reserved Reserved Document #: 001-42225 Rev. *A Description Page 5 of 12 [+] Feedback CY28517 Byte 5: Control Register 5 Bit @Pup Name Description 7 0 Reserved Reserved 6 0 Reserved Reserved 5 0 Reserved Reserved 4 0 Reserved Reserved 3 0 Reserved Reserved 2 0 Reserved Reserved 1 0 Reserved Reserved 0 0 Reserved Reserved Byte 6: Vendor ID Register Bit @Pup 7 0 Read Only Name Revision Code Bit 3 Description 6 0 Read Only Revision Code Bit 2 5 0 Read Only Revision Code Bit 1 4 0 Read Only Revision Code Bit 0 3 1 Read Only Vendor ID Bit 3 2 0 Read Only Vendor ID Bit 2 1 0 Read Only Vendor ID Bit 1 0 0 Read Only Vendor ID Bit 0 Crystal Recommendations The CY28517 requires a Parallel Resonance Crystal. Substituting a series resonance crystal causes the CY28517 to operate at the wrong frequency and violate the ppm specification. For most applications there is a 300 ppm frequency shift between series and parallel crystals due to incorrect loading. Table 5. Crystal Recommendations Frequency (Fund) Cut Load Cap Eff Series Rest Drive (Max) Tolerance (Max) Stability (Max) Aging (Max) 27.00 MHz Parallel 18 pF 30 Ohm 50 μW 30 ppm 10 ppm 5 ppm/Yr Crystal Loading Calculating Load Capacitors Crystal loading plays a critical role in achieving low ppm performance. To realize low ppm performance, the total capacitance of the crystal must be considered to calculate the appropriate capacitive loading (CL). In addition to the standard external trim capacitors, trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. Figure 2 on page 7 shows a typical crystal configuration using the two trim capacitors. An important clarification for the following discussion is that the trim capacitors are in series with the crystal not parallel. It’s a common misconception that load capacitors are in parallel with the crystal and must be approximately equal to the load capacitance of the crystal. This is not true. Document #: 001-42225 Rev. *A As mentioned previously, the capacitance on each side of the crystal is in series with the crystal. This means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (CL). While the capacitance on each side of the crystal is in series with the crystal, trim capacitors (Ce1,Ce2) must be calculated to provide equal capacitive loading on both sides. Page 6 of 12 [+] Feedback CY28517 Output Enable Figure 2. Crystal Loading Example The Output Enable (OE_100_25) signal is active HIGH input used for clean stopping and starting the selected 100M and 25M outputs. To recognize as a valid assertion or deassertion, the signal is a debounced signal in that its state must remain unchanged during two consecutive rising edges of 25 MHz. C lo c k C h ip C i2 C i1 P in 3 to 6 p The assertion and deassertion of this signal is absolutely asynchronous. X2 X1 C s1 C s2 Output Enable Deassertion T ra c e 2 .8 p F Upon deasserting the Output Enable pin (OE_100_25) all 100M/25M outputs are stopped after their next transition. The final state of all stopped 100M/25M signals is LOW. XTAL Ce1 Ce2 T r im 33pF Output Enable Assertion Use the following formulas to calculate the trim capacitor values for Ce1 and Ce2. Load Capacitance (each side) Ce = 2 * CL – (Cs + Ci) Total Capacitance (as seen by the crystal) CLe = 1 1 ( Ce1 + Cs1 + Ci1 + 1 Ce2 + Cs2 + Ci2 All 100 MHz/25 MHz outputs that were stopped resumes normal operation in a glitch free manner. The maximum latency from the assertion to active outputs is between 2–6 clock periods of 100 MHz/25 MHz with all 100M/25M outputs resuming simultaneously. Table 6. Output Enable Table Output Enable 27M 48M 0 On On Low Hi-Z 1 On On On On ) 25M[A:B] 100MT/C[A:D] CL ................................................... Crystal load capacitance CLe ......................................... Actual loading seen by crystal using standard value trim capacitors Ce ..................................................... External trim capacitors Cs ..............................................Stray capacitance (terraced) Ci .......................................................... Internal capacitance Absolute Maximum Conditions Parameter Description VDD Supply Voltage Condition Min Max Unit –0.5 4.6 V VIN Input Voltage Relative to VSS –0.5 VDD + 0.5 VDC TS Temperature, Storage Non-functional –65 150 °C TA Temperature, Operating Ambient Functional 5 65 °C TJ Temperature, Junction Functional – 150 °C TSOL Pb free Soldering Process Temperature – 260 °C – V ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 UL-94 Flammability Rating At 1/8 in. MSL Moisture Sensitivity Level 2000 V–0 1 Multiple Supplies: The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is NOT required. Document #: 001-42225 Rev. *A Page 7 of 12 [+] Feedback CY28517 DC Electrical Specifications Parameter Description Condition Min Max Unit V VDD 3.3V Operating Voltage 3.0 3.6 VILI2C Input Low Voltage SDATA, SCLK – 1.0 V VIHI2C Input High Voltage SDATA, SCLK 2.2 – V VIL Input Low Voltage –0.3 0.8 V VIH Input High Voltage 2.0 3.6 V IIL Input Low Leakage Current Except internal pull up resistors, 0 < VIN < VDD IIH Input High Leakage Current Except internal pull down resistors, 0 < VIN < VDD 5 μA VOL Output Low Voltage IOL = 1 mA V VOH Output High Voltage IOH = –1 mA IOZ High impedance Output Current μA –5 – 0.4 2.4 – V –10 10 μA CIN Input Pin Capacitance 2 5 pF COUT Output Pin Capacitance 3 6 pF LIN Pin Inductance – 7 nH VXIH Xin High Voltage 0.7VDD VDD V VXIL Xin Low Voltage 0 0.3VDD V IDD3.3V Dynamic Supply Current At max load and freq per Figure 4 – 225 mA IPD3.3V Power down Supply Current Outputs disabled and no power applied to VDD25 and VDD100 – 60 mA AC Electrical Specifications Parameter Description Condition Min Typ. Max Unit 27M Output Characteristics FCLOCK Clock Frequency 27 MHz TDC XIN Duty Cycle The device operates reliably with input duty cycles up to 30/70 but the REF clock duty cycle is not within specification 45 – 55 % TPERIOD XIN Period When XIN is driven from an external clock source 37.0259 – 37.0481 ns TR / TF XIN Rise and Fall Times Measured between 20% and 80% of VOD 1 – 3 ns TCCJ XIN Cycle to Cycle Jitter Measured at 1.5V –200 – 200 ps LLTJ Long term Jitter (peak-peak) Measured at 1.5V with 10 μs delay –250 – 250 ps TLOCK Clock Stabilization from Power up – – 2 ms VOH Voltage High Math average 2.4 – – V VOL Voltage Low Math average – – 0.4 V 100M Output Characteristics FCLOCK Clock frequency TPERIOD Clock period TJCC Cycle to Cycle jitter Peak value. Measured at crossing point with spread turned off –85 – 85 ps TJLT Long Term Jitter (p-p) Measured at crossing point with 10 μs delay and spread turned off –300 – 300 ps SPrange Spread range –0.5 – 0.0 % SPrate Spread rate – 32 SPprofile Spread profile – Triangular Document #: 001-42225 Rev. *A – – 100 MHz Without spread and without jitter 10.000 – – ns Including +0.0, –0.5% spread and jitter 9.915 10.025 10.136 ns KHz Page 8 of 12 [+] Feedback CY28517 AC Electrical Specifications Parameter (continued) Description Condition Min Typ. Max Unit Measured at crossing point of the differential signal 45 – 55 % 175 – 700 ps – – 20 % 250 – 550 mV TDC Duty Cycle TR/TF Rise and Fall Times Measured between 20% and 80% of the VOD TRFM Rise/Fall Matching[1] Determined as a fraction of 2*(TR-TF)/ (TR+TF) VOX Crossing Point Voltage at 0.7V Swing ΔVOX Total Variation of VOX over all edges VOH Voltage High[1] VOL [1] TSKEW – – 140 mV Math average 600 710 850 mv Voltage Low Math average –200 0.00 50 mv Output Skew Measured at crossing point VOX – – 250 ps TLOCK Clock stabilization from power up BWattn Closed loop BW attenuation – – 2 ms Measured at 500 KHz relative to corner frequency –20 – – dB 25M Output Characteristics FCLOCK Clock frequency – 25 TCCJ Cycle to Cycle jitter Peak value –200 – 200 ps MHz TJLT Long Term Jitter (p-p) Measured at 1.5V with 10 μs delay –400 – 400 ps TDC Duty Cycle Measured at 1.5V 45 – 55 % TR/TF Rise and Fall Times Measured between 20% and 80% of the VOD with 15 pF lumped capacitive load 1 – 3 ns TLOCK Clock stabilization from power up – – 2 ms VOH Voltage High Math average 2.4 – – V VOL Voltage Low Math average – – 0.4 V 48M Output Characteristics FCLOCK Clock frequency – 48 TCCJ Cycle to Cycle jitter Peak value –200 – 200 ps MHz TJLT Long Term Jitter (p-p) Measured at 1.5V with 10 μs delay –400 – 400 ps TDC Duty Cycle Measured at 1.5V 45 – 55 % TR/TF Rise and Fall Times Measured between 20% and 80% of the VOD with 15 pF lumped capacitive load 0.7 – 2 ns TLOCK Clock stabilization from power up – – 2 ms VOH Voltage High Math average 2.4 – – V VOL Voltage Low Note 1. Measured at VDD = 3.3V±5% Math average – – 0.4 V Document #: 001-42225 Rev. *A Page 9 of 12 [+] Feedback CY28517 Test and Measurement Set up For Single ended Signals The following diagram shows the test load configurations for the single ended output signals. Figure 3. Single-ended Load Configuration 15pF Lum ped Load (Including Trace) For Differential 100 MHz Output Signals The following diagram shows the test load configuration for the differential CPU and SRC outputs. Trace length is 5 in. Max Figure 4. 0.7V Single-ended Load Configuration 100MT 49.9Ω 100MC IREF Measurement Point 33Ω 5pF (max) 100Ω Differential Measurement Point 33Ω 49.9Ω 5pF (max) 470Ω Figure 5. Single-ended Output Signals (for AC Parameters Measurement) TR TF 80% 50% 20% T DC Document #: 001-42225 Rev. *A Page 10 of 12 [+] Feedback CY28517 Figure 6. Differential Output Signals (for AC Parameters Measurement) T R, T F 80% V OH , V IH V OD, V ID V OCM V ICM 20% V OL , V IL Ordering Information Part Number Package Type Product Flow Pb free CY28517ZXC 28 pin TSSOP Commercial, 5° to 65°C CY28517ZXCT 28 pin TSSOP – Tape and Reel Commercial, 5° to 65°C Package Drawing and Dimensions Figure 7. 28-Lead Thin Shrunk Small Outline Package (4.40-mm Body) Z28.173 DIMENSIONS IN MM[INCHES] MIN. MAX. PIN 1 ID 1 REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.16 gms 4.30[0.169] 4.50[0.177] 6.25[0.246] 6.50[0.256] PART # Z28.173 STANDARD PKG. ZZ28.173 LEAD FREE PKG. 28 0.65[0.025] BSC. 0.19[0.007] 0.30[0.012] 1.10[0.043] MAX. 0.25[0.010] BSC GAUGE PLANE 0°-8° 0.076[0.003] 0.85[0.033] 0.95[0.037] 9.60[0.378] 9.80[0.386] 0.05[0.002] 0.15[0.006] SEATING PLANE 0.50[0.020] 0.70[0.027] 0.09[[0.003] 0.20[0.008] 51-85120-*A Document #: 001-42225 Rev. *A Page 11 of 12 [+] Feedback CY28517 Document History Page Document Title: CY28517 PCI Express Clock Generator Document Number: 001-42225 REV. ECN NO. Issue Date ** 1664043 See ECN *A 1698623 See ECN Orig. of Change Description of Change WWZ/AESA New Data Sheet AESA Updated Copyright © Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document #: 001-42225 Rev. *A Revised November 02, 2007 Page 12 of 12 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback