MAXIM DS1248

19-6078; Rev 11/11
DS1248/DS1248P
1024K NV SRAM with Phantom Clock
FEATURES

PIN CONFIGURATIONS
Real-Time Clock (RTC) Keeps Track of
Hundredths of Seconds, Minutes, Hours,
Days, Date of the Month, Months, and Years

128K x 8 NV SRAM Directly Replaces
Volatile Static RAM or EEPROM

Embedded Lithium Energy Cell Maintains
Calendar Operation and Retains RAM Data

Watch Function is Transparent to RAM
Operation

Automatic Leap Year Compensation Valid
Up to 2100

Full 10% Operating Range

Over 10 Years of Data Retention in the
Absence of Power

Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time

DIP Module Only
TOP VIEW
RST
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
Underwriters Laboratories (UL) Recognized
(www.maxim-ic.com/qa/info/ul/)

PowerCap Module Board Only
Surface Mountable Package for Direct
Connection to PowerCap Containing
Battery and Crystal
Replaceable Battery (PowerCap)
Pin-for-Pin Compatible with DS1244P and
DS1251P
32
31
30
29
28
27
26
25
24
23
22
21
VCC
A15
N.C.
DQ0
13
20
DQ6
DQ1
DQ2
14
19
DQ5
15
18
DQ4
16
17
DQ3
A0
GND
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
Encapsulated DIP
(740-mil Flush)
Standard 32-Pin JEDEC Pinout

1
2
3 DS1248
4
5
6
7
8
9
10
11
12
RST
A15
A16
N.C.
VCC
WE
OE
CE
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DS1248P
X1
GND
VBAT
X2
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
PowerCap Module Board
(Uses DS9034PCX+ PowerCap)
1 of 19
N.C.
N.C.
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DS1248/DS1248P 1024K NV SRAM with Phantom Clock
ORDERING INFORMATION
PART
TEMP RANGE
VCC RANGE
DS1248Y-70+
DS1248Y-70IND+
DS1248YP-70+
DS1248W-120+
DS1248W-120IND+
DS1248WP-120+
DS1248WP-120IND+
0°C to +70°C
-40°C to +85°C
0°C to +70°C
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
5V ±10%
5V ±10%
5V ±10%
3.3V ±10%
3.3V ±10%
3.3V ±10%
3.3V ±10%
PIN-PACKAGE
32 EDIP
32 EDIP
34 PowerCap*
32 EDIP
32 EDIP
34 PowerCap*
34 PowerCap*
+ Denotes a lead(Pb)-free/RoHS-compliant package.
* DS9034PCX+ or DS9034I-PCX+ (PowerCap) required. Must be ordered separately.
DETAILED DESCRIPTION
The DS1248 1024K NV SRAM with phantom clock is a fully static, nonvolatile RAM (organized as
128K words by 8 bits) with a built-in real-time clock. The DS1248 has a self-contained lithium energy
source and control circuitry, which constantly monitors VCC for an out-of-tolerance condition. When such
a condition occurs, the lithium energy source is automatically switched on and writes protection is
unconditionally enabled to prevent garbled data in both the memory and real-time clock.
PACKAGES
The DS1248 is available in two packages: 32-pin DIP and 34-pin PowerCap module. The 32-pin DIP
style module integrates the crystal, lithium energy source, and silicon in one package. The 34-pin
PowerCap module board is designed with contacts for connection to a separate PowerCap (DS9034PCX)
that contains the crystal and battery. This design allows the PowerCap to be mounted on top of the
DS1248P after completion of the surface mount process. Mounting the PowerCap after the surface mount
process prevents damage to the crystal and battery because of the high temperatures required for solder
reflow. The PowerCap is keyed to prevent reverse insertion. The PowerCap module board and PowerCap
are ordered separately and shipped in separate containers.
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DS1248/DS1248P 1024K NV SRAM with Phantom Clock
PIN DESCRIPTION
EDIP
PIN
PowerCap
NAME
1
1
RST
2
3
4
5
6
7
8
9
10
11
12
23
25
26
27
28
31
13
14
15
17
18
19
20
21
22
24
29
30
32
16
3
32
30
25
24
23
22
21
20
19
18
28
29
27
26
31
2
16
15
14
13
12
11
10
9
8
7
6
4, 33, 34
5
17
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
A10
A11
A9
A8
A13
A15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
CE
OE
WE
N.C.
VCC
GND
FUNCTION
Active-Low Reset Input. This pin has an internal pullup resistor
connected to VCC.
Address Inputs
Data In/Data Out
Active-Low Chip-Enable Input
Active-Low Output-Enable Input
Active-Low Write-Enable Input
No Connect
Power-Supply Input
Ground
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DS1248/DS1248P 1024K NV SRAM with Phantom Clock
RAM READ MODE
The DS1248 executes a read cycle whenever WE (write enable) is inactive (high) and CE (chip enable) is
active (low). The unique address specified by the 17 address inputs (A0–A16) defines which of the 128k
bytes of data is to be accessed. Valid data will be available to the eight data-output drivers within tACC
(access time) after the last address input signal is stable, providing that CE and OE (output enable) access
times and states are also satisfied. If OE and CE access times are not satisfied, then data access must be
measured from the later occurring signal (CE or OE) and the limiting parameter is either tCO for CE or tOE
for OE, rather than address access.
RAM WRITE MODE
The DS1248 is in the write mode whenever the WE and CE signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of CE or WE will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of CEor WE. All address inputs must
be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
(tWR) before another cycle can be initiated. The OE control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output bus has been enabled (CE and OE active)
then WE will disable the outputs in tODW from its falling edge.
DATA RETENTION MODE
The 5V device is fully accessible and data can be written or read only when VCC is greater than VPF.
However, when VCC is below the power-fail point, VPF (point at which write protection occurs), the
internal clock registers and SRAM are blocked from any access. When VCC falls below the battery switch
point, VSO (battery supply level), device power is switched from the VCC pin to the backup battery. RTC
operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.
The 3.3V device is fully accessible and data can be written or read only when VCC is greater than VPF.
When VCC falls below VPF, access to the device is inhibited. If VPF is less than VBAT, the device power is
switched from VCC to the backup supply (VBAT) when VCC drops below VPF. If VPF is greater than VBAT,
the device power is switched from VCC to the backup supply (VBAT) when VCC drops below VBAT. RTC
operation and SRAM data are maintained from the battery until VCC is returned to nominal levels.
All control, data, and address signals must be powered down when VCC is powered-down.
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DS1248/DS1248P 1024K NV SRAM with Phantom Clock
PHANTOM CLOCK OPERATION
Communication with the phantom clock is established by pattern recognition on a serial bit stream of
64 bits, which must be matched by executing 64 consecutive write cycles containing the proper data on
DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
phantom clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of chip enable, output enable, and write enable. Initially, a read cycle to any memory location using the
CE and OE control of the phantom clock starts the pattern recognition sequence by moving a pointer to
the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the CE
and WE control of the SmartWatch. These 64 write cycles are used only to gain access to the phantom
clock. Therefore, any address to the memory in the socket is acceptable. However, the write cycles
generated to gain access to the phantom clock are also writing data to a location in the mated RAM. The
preferred
way
to
manage
this
requirement
is
to
set
aside
just
one address location in RAM as a phantom clock scratch pad. When the first write cycle is executed, it is
compared to bit 0 of the 64-bit comparison register. If a match is found, the pointer increments to the next
location of the comparison register and awaits the next write cycle. If a match is not found, the pointer
does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during
pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern
recognition continues for a total of 64 write cycles as described above until all the bits in the comparison
register have been matched (Figure 1). With a correct match for 64 bits, the phantom clock is enabled and
data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the phantom
clock to either receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin.
Cycles to other locations outside the memory block can be interleaved with CE cycles without
interrupting the pattern recognition sequence or data transfer sequence to the phantom clock.
PHANTOM CLOCK REGISTER INFORMATION
The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially
accessed 1 bit at a time after the 64-bit pattern recognition sequence has been completed. When updating
the phantom clock registers, each register must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 2.
Data contained in the phantom clock register is in binary-coded decimal format (BCD). Reading and
writing the registers is always accomplished by stepping through all eight registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.
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DS1248/DS1248P 1024K NV SRAM with Phantom Clock
Figure 1. Phantom Clock Register Definition
NOTE: THE PATTERN RECOGNITION IN HEX IS C5, 3A, A3, 5C, C5, 3A, A3, 5C. THE ODDS OF THIS PATTERN
BEING ACCIDENTALLY DUPLICATED AND CAUSING INADVERTENT ENTRY TO THE PHANTOM CLOCK IS
LESS THAN 1 IN 1019. THIS PATTERN IS SENT TO THE PHANTOM CLOCK LSB TO MSB.
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DS1248/DS1248P 1024K NV SRAM with Phantom Clock
Figure 2. Phantom Clock Register Definition
AM/PM/12/24-MODE
Bit 7 of the hours register is defined as the 12-hour or 24-hour mode-select bit. When high, the 12-hour
mode is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour
mode, bit 5 is the 20-hour bit (20–23 hours).
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the RST and oscillator functions. Bit 4 controls the
RST (pin 1). When the RST bit is set to logic 1, the RST input pin is ignored. When the RST bit is set to
logic 0, a low input on the RST pin will cause the phantom clock to abort data transfer without changing
data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the oscillator is off. When set
to logic 0, the oscillator turns on and the watch becomes operational. These bits are shipped from the
factory set to a logic 1.
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DS1248/DS1248P 1024K NV SRAM with Phantom Clock
ZERO BITS
Registers 1, 2, 3, 4, 5, and 6 contain one or more bits, which will always read logic 0. When writing these
locations, either a logic 1 or 0 is acceptable.
BATTERY LONGEVITY
The DS1248 has a lithium power source that is designed to provide energy for clock activity and clock
and RAM data retention when the VCC supply is not present. The capability of this internal power supply
is sufficient to power the DS1248 continuously for the life of the equipment in which it is installed. For
specification purposes, the life expectancy is 10 years at +25°C with the internal clock oscillator running
in the absence of VCC power. Each DS1248 is shipped from Maxim with its lithium energy source
disconnected, guaranteeing full energy capacity. When VCC is first applied at a level greater than VPF, the
lithium energy source is enabled for battery-backup operation. Actual life expectancy of the DS1248 will
be much longer than 10 years since no lithium battery energy is consumed when VCC is present.
See “Conditions of Acceptability” at www.maxim-ic.com/TechSupport/QA/ntrl.htm
CLOCK ACCURACY (DIP MODULE)
The DS1248 is guaranteed to keep time accuracy to within ±1 minute per month at +25°C. The clock is
calibrated at the factory by Maxim using special calibration nonvolatile tuning elements and does not
require additional calibration. For this reason, methods of field clock calibration are not available and not
necessary.
CLOCK ACCURACY (POWERCAP MODULE)
The DS1248P and DS9034PCX are each individually tested for accuracy. Once mounted together, the
module will typically keep time accuracy to within ±1.53 minutes per month (35ppm) at +25°C.
8 of 19
DS1248/DS1248P 1024K NV SRAM with Phantom Clock
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground
(5V product)………………………..-0.3V to +6.0V
(3.3V product)………………… …..-0.3V to +4.6V
Storage Temperature Range
EDIP ..........................................................................................................................-40ºC to +85ºC
PowerCap ................................................................................................................-55°C to +125°C
Lead Temperature (soldering, 10s) ................................................................................................... +260°C
Note: EDIP is wave or hand-soldered only.
Soldering Temperature (reflow, PowerCap) ......................................................................................+260°C
This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect
reliability.
OPERATING RANGE
TEMP RANGE
(NONCONDENSING)
0°C to +70°C
-40°C to +85°C
RANGE
Commercial
Industrial
VCC (V)
3.3 ±10% or 5 ±10%
3.3 ±10% or 5 ±10%
RECOMMENDED OPERATING CONDITIONS
Over the Operating Range
PARAMETER
Logic 1
Logic 0
VCC = 5V ±10%
VCC = 3.3V ±10%
VCC = 5V ±10%
VCC = 3.3V ±10%
SYMBOL
MIN
VIH
VIL
TYP
MAX
UNITS
NOTES
V
11
V
11
MAX
UNITS
NOTES
12
2.2
VCC + 0.3
2.0
VCC + 0.3
-0.3
-0.3
+0.8
+0.6
DC ELECTRICAL CHARACTERISTICS
Over the Operating Range (5V)
PARAMETER
Input Leakage Current
I/O Leakage Current
CE ≥ VIH ≤ VCC
Output Current at 2.4V
Output Current at 0.4V
Standby Current CE = 2.2V
SYMBOL
MIN
IIL
-1.0
+1.0
µA
IIO
-1.0
+1.0
µA
IOH
IOL
ICCS1
-1.0
2.0
5
10
mA
mA
mA
3.0
5.0
mA
4.37
85
4.50
mA
V
11
V
11
Standby Current
CE = VCC - 0.5V
ICCS2
Operating Current tCYC = 70ns
Write Protection Voltage
ICC01
VPF
Battery Switchover Voltage
VSO
4.25
TYP
VBAT
9 of 19
DS1248/DS1248P 1024K NV SRAM with Phantom Clock
DC ELECTRICAL CHARACTERISTICS
Over the Operating Range (3.3V)
PARAMETER
SYMBOL
Input Leakage Current
IIL
I/O Leakage Current
IIO
CE ≥ VIH ≤ VCC
Output Current at 2.4V
IOH
Output Current at 0.4V
IOL
Standby Current CE = 2.2V
ICCS1
Standby Current
ICCS2
CE = VCC - 0.5V
Operating Current tCYC = 70ns
ICC01
Write Protection Voltage
VPF
Battery Switchover Voltage
MIN
-1.0
TYP
MAX
+1.0
UNITS
+1.0
µA
5
7
mA
mA
mA
2.0
3.0
mA
50
2.97
mA
V
11
V
11
UNITS
pF
pF
NOTES
-1.0
-1.0
2.0
2.80
2.86
VBAT or
VPF
VSO
µA
NOTES
12
CAPACITANCE
(TA = +25°C)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
CIN
CI/O
MIN
TYP
5
5
MAX
10
10
MEMORY AC ELECTRICAL CHARACTERISTICS
Over the Operating Range (5V)
PARAMETER
Read Cycle Time
Access Time
OE to Output Valid
CE to Output Valid
OE or CE to Output Active
Output High-Z from Deselection
Output Hold from Address Change
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery Time
Output High-Z from WE
Output Active from WE
Data Setup Time
Data Hold Time from WE
SYMBOL
tRC
tACC
tOE
tCO
tCOE
tOD
tOH
tWC
tWP
tAW
tWR
tODW
tOEW
tDS
tDH
DS1248Y-70
MIN
MAX
70
70
35
70
5
25
5
70
50
0
0
25
5
30
5
10 of 19
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
5
5
3
5
5
4
4
DS1248/DS1248P 1024K NV SRAM with Phantom Clock
PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICS
Over the Operating Range (5V)
PARAMETER
Read Cycle Time
CE Access Time
OE Access Time
CE to Output Low-Z
OE to Output Low-Z
CE to Output High-Z
OE to Output High-Z
Read Recovery
Write Cycle Time
Write Pulse Width
Write Recovery
Data Setup Time
Data Hold Time
CE Pulse Width
RST Pulse Width
SYMBOL
MIN
tRC
tCO
tOE
tCOE
tOEE
tOD
tODO
tRR
tWC
tWP
tWR
tDS
tDH
tCW
tRST
65
TYP
MAX
55
55
5
5
25
25
10
65
55
10
30
0
60
65
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
5
5
3
10
4
4
POWER-DOWN/POWER-UP TIMING
Over the Operating Range (3.3V)
PARAMETER
SYMBOL
CE at VIH before Power-Down
MIN
TYP
MAX
UNITS
tPD
0
µs
tF
300
µs
tFB
10
µs
VCC Slew from VPF(max) to
VPF(min)(CE at VPF)
tR
0
µs
CE at VIH after Power-Up
tREC
1.5
SYMBOL
tDR
MIN
10
VCC Slew from VPF(max) to
VPF(min)( CE at VPF)
VCC Slew from VPF(min) to VSO
(TA = +25°C)
PARAMETER
Expected Data-Retention Time
TYP
2.5
ms
MAX
UNITS
years
NOTES
NOTES
9
Warning: Under no circumstances are negative undershoots of any amplitude allowed when device
is in battery-backup mode.
11 of 19
DS1248/DS1248P 1024K NV SRAM with Phantom Clock
MEMORY AC ELECTRICAL CHARACTERISTICS
Over the Operating Range (3.3V)
PARAMETER
Read Cycle Time
Access Time
OE to Output Valid
CE to Output Valid
OE or CE to Output Active
Output High-Z from Deselection
Output Hold from Address Change
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery Time
Output High-Z from WE
Output Active from WE
Data Setup Time
Data Hold Time from WE
SYMBOL
tRC
tACC
tOE
tCO
tCOE
tOD
tOH
tWC
tWP
tAW
tWR
tODW
tOEW
tDS
tDH
DS1248W-120
MIN
MAX
120
120
60
120
5
40
5
120
90
0
20
40
5
50
20
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
5
5
3
10
5
5
4
4
PHANTOM CLOCK AC ELECTRICALCHARACTERISTICS
Over the Operating Range (3.3V)
PARAMETER
Read Cycle Time
CE Access Time
OE Access Time
CE to Output Low-Z
OE to Output Low-Z
CE to Output High-Z
OE to Output High-Z
Read Recovery
Write Cycle Time
Write Pulse Width
Write Recovery
Data Setup Time
Data Hold Time
CE Pulse Width
RST Pulse Width
SYMBOL
tRC
tCO
tOE
tCOE
tOEE
tOD
tODO
tRR
tWC
tWP
tWR
tDS
tDH
tCW
tRST
12 of 19
MIN
120
5
5
20
120
100
20
45
0
105
120
TYP
MAX
100
100
40
40
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
5
5
3
10
4
4
DS1248/DS1248P 1024K NV SRAM with Phantom Clock
POWER-DOWN/POWER-UP TIMING
Over the Operating Range (3.3V)
PARAMETER
CE at VIH before Power-Down
VCC Slew from VPF(MAX) to
VPF(MIN)(CE at VIH)
VCC Slew from VPF(MAX) to
VPF(MIN)(CE at VIH)
CE at VIH after Power-Up
(TA = +25°C)
PARAMETER
Expected Data-Retention Time
SYMBOL
tPD
tF
MIN
0
300
tR
0
tREC
1.5
SYMBOL
MIN
tDR
10
TYP
MAX
UNITS
NOTES
µs
µs
µs
TYP
2.5
ms
MAX
UNITS
NOTES
years
9
Warning: Under no circumstances are negative undershoots, of any amplitude, allowed when
device is in battery-backup mode.
MEMORY READ CYCLE (Note 1)
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DS1248/DS1248P 1024K NV SRAM with Phantom Clock
MEMORY WRITE CYCLE 1 (Notes 2, 6, and 7)
MEMORY WRITE CYCLE 2 (Notes 2 and 8)
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DS1248/DS1248P 1024K NV SRAM with Phantom Clock
RESET FOR PHANTOM CLOCK
READ CYCLE TO PHANTOM CLOCK
WRITE CYCLE TO PHANTOM CLOCK
15 of 19
DS1248/DS1248P 1024K NV SRAM with Phantom Clock
POWER-DOWN/POWER-UP CONDITION (5V)
POWER-DOWN/POWER-UP CONDITION (3.3V)
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DS1248/DS1248P 1024K NV SRAM with Phantom Clock
AC TEST CONDITIONS
Output Load: 50pF + 1TTL Gate
Input Pulse Levels: 0 to 3V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
NOTES:
1) WE is high for a read cycle.
2) OE = VIH or VIL. If CE = VIH during write cycle, the output buffers remain in a high impedance state.
3) tWP is specified as the logical AND of CE and WE. tWP is measured from the latter of CE or WE going
low to the earlier of CE or WE going high.
4) tDH, tDS are measured from the earlier of CE or WE going high.
5) These parameters are sampled with a 50pF load and are not 100% tested.
6) If the CE low transition occurs simultaneously with or later than the WE low transition in Write Cycle
1, the output buffers remain in a high-impedance state during this period.
7) If the CE high transition occurs prior to or simultaneously with the WE high transition, the output
buffers remain in a high-impedance state during this period.
8) If WE is low or the WE low transition occurs prior to or simultaneously with the CE low transition,
the output buffers remain in a high impedance state during this period.
9) The expected tDR is defined as cumulative time in the absence of VCC with the clock oscillator
running.
10) tWR is a function of the latter occurring edge of WE or CE.
11) Voltages are referenced to ground.
12) RST (Pin 1) has an internal pullup resistor.
13) RTC modules can be successfully processed through conventional wave-soldering techniques as long
as temperature exposure to the lithium energy source contained within does not exceed +85°C. Postsolder cleaning with water-washing techniques is acceptable, provided that ultrasonic vibration is not
used. See the PowerCap package drawing for details regarding the PowerCap package.
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DS1248/DS1248P 1024K NV SRAM with Phantom Clock
PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a
different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE
32 EDIP
34 PWRCP
PACKAGE CODE
MDT32+2
PC2+3
OUTLINE NO.
21-0245
21-0246
18 of 19
LAND PATTERN NO.
—
—
DS1248/DS1248P 1024K NV SRAM with Phantom Clock
REVISION HISTORY
REVISION
DATE
11/11
DESCRIPTION
Updated the Features, Ordering Information, AM/PM/12/24-MODE,
Absolute Maximum Ratings, and Package Information sections
PAGES
CHANGED
1, 2, 7, 9, 18
19 of 19
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reserves the right to change the circuitry and specifications without notice at any time.
M a x i m I n t e g r a t e d P r o d u c t s , 1 2 0 S a n G a b r i e l D r iv e , S u n n y v a le , C A 9 4 0 8 6 4 0 8- 7 3 7 - 7 6 0 0
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