NSC DS90C363BMT

August 2005
DS90C363B
+3.3V Programmable LVDS Transmitter 18-Bit Flat Panel
Display (FPD) Link -65 MHz
General Description
Features
The DS90C363B transmitter converts 21 bits of CMOS/TTL
data into three LVDS (Low Voltage Differential Signaling)
data streams. A phase-locked transmit clock is transmitted in
parallel with the data streams over a fourth LVDS link. Every
cycle of the transmit clock 21 bits of input data are sampled
and transmitted. At a transmit clock frequency of 65 MHz, 18
bits of RGB data and 3 bits of LCD timing and control data
(FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455
Mbps per LVDS data channel. Using a 65 MHz clock, the
data throughput is 170 Mbytes/sec. The DS90C363B transmitter can be programmed for Rising edge strobe or Falling
edge strobe through a dedicated pin. A Rising edge or
Falling edge strobe transmitter will interoperate with a Falling
edge strobe Receiver (DS90CF366) without any translation
logic.
n No special start-up sequence required between
clock/data and /PD pins. Input signal (clock and data)
can be applied either before or after the device is
powered.
n Support Spread Spectrum Clocking up to 100kHz
frequency modulation & deviations of ± 2.5% center
spread or −5% down spread.
n "Input Clock Detection" feature will pull all LVDS pairs to
logic low when input clock is missing and when /PD pin
is logic high.
n 18 to 68 MHz shift clock support
n Best–in–Class Set & Hold Times on TxINPUTs
n Tx power consumption < 130 mW (typ) @65MHz
Grayscale
n 40% Less Power Dissipation than BiCMOS Alternatives
n Tx Power-down mode < 37µW (typ)
n Supports VGA, SVGA, XGA and Dual Pixel SXGA.
n Narrow bus reduces cable size and cost
n Up to 1.3 Gbps throughput
n Up to 170 Megabytes/sec bandwidth
n 345 mV (typ) swing LVDS devices for low EMI
n PLL requires no external components
n Compatible with TIA/EIA-644 LVDS standard
n Low profile 48-lead TSSOP package
n Improved replacement for:
SN75LVDS84, DS90C363A
This chipset is an ideal means to solve EMI and cable size
problems associated with wide, high speed TTL interfaces.
Block Diagram
DS90C363B
20098601
Order Number DS90C363BMT
See NS Package Number MTD48
TRI-STATE ® is a registered trademark of National Semiconductor Corporation.
© 2005 National Semiconductor Corporation
DS200986
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DS90C363B +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz
PRELIMINARY
DS90C363B
Absolute Maximum Ratings (Note 1)
Package Derating:
DS90C363B
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Supply Voltage (VCC)
ESD Rating
(HBM, 1.5 kΩ, 100 pF)
7 kV
(EIAJ, 0Ω, 200 pF)
500V
−0.3V to +4V
CMOS/TTL Input Voltage
−0.3V to (VCC + 0.3V)
LVDS Driver Output Voltage
−0.3V to (VCC + 0.3V)
LVDS Output Short Circuit
Duration
Recommended Operating
Conditions
Continuous
Junction Temperature
+150˚C
Storage Temperature
−65˚C to +150˚C
16 mW/˚C above +25˚C
Supply Voltage (VCC)
Min
Nom
Max
Units
3.0
3.3
3.6
V
−10
+25
+70
˚C
200
mVPP
68
MHz
Max
Units
Operating Free Air
Lead Temperature
(Soldering, 4 sec)
Temperature (TA)
+260˚C
Supply Noise Voltage
(VCC)
Maximum Package Power Dissipation Capacity @ 25˚C
MTD48 (TSSOP) Package:
DS90C363B
TxCLKIN frequency
1.98 W
18
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
CMOS/TTL DC SPECIFICATIONS
VIH
High Level Input Voltage
2.0
VCC
V
VIL
Low Level Input Voltage
GND
0.8
V
VCL
Input Clamp Voltage
ICL = −18 mA
−0.79
−1.5
V
IIN
Input Current
V
IN
= 0.4V, 2.5V or VCC
+1.8
+10
µA
V
IN
= GND
−10
0
250
345
µA
LVDS DC SPECIFICATIONS
VOD
Differential Output Voltage
∆VOD
Change in VOD between
complimentary output states
VOS
Offset Voltage (Note 4)
∆VOS
Change in VOS between
complimentary output states
IOS
Output Short Circuit Current
VOUT = 0V, RL = 100Ω
IOZ
Output TRI-STATE ® Current
Power Down = 0V,
VOUT = 0V or V CC
RL = 100Ω
450
mV
35
mV
1.38
V
35
mV
−3.5
−5
mA
±1
± 10
µA
f = 25MHz
29
40
mA
f = 40 MHz
34
45
mA
f = 65 MHz
42
55
mA
1.13
1.25
TRANSMITTER SUPPLY CURRENT
ICCTW
Transmitter Supply Current
Worst Case
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RL = 100Ω,
CL = 5 pF,
Worst Case Pattern
(Figures 1, 4 ) " Typ "
values are given for V
CC = 3.6V and T A =
+25˚C, " Max " values
are given for V CC =
3.6V and T A = −10˚C
2
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
f = 25 MHz
28
40
mA
f = 40 MHz
32
45
mA
f = 65 MHz
39
50
mA
Power Down = Low
Driver Outputs in TRI-STATE ® under
Power Down Mode
11
150
µA
TRANSMITTER SUPPLY CURRENT
ICCTG
ICCTZ
Transmitter Supply Current
16 Grayscale
RL = 100Ω,
CL = 5 pF,
16 Grayscale Pattern
(Figures 2, 4 ) " Typ "
values are given for V
CC = 3.6V and T A =
+25˚C, " Max " values
are given for V CC =
3.6V and T A = −10˚C
Transmitter Supply Current
Power Down
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the device
should be operated at these limits. The tables of “Electrical Characteristics” specify conditions for device operation.
Note 2: Typical values are given for VCC = 3.3V and T A = +25˚C unless specified otherwise.
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground unless otherwise
specified (except VOD and ∆VOD ).
Note 4: VOS previously referred as VCM.
Recommended Transmitter Input Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
TCIT
TxCLK IN Transition Time (Figure 5 )
TCIP
TxCLK IN Period (Figure 6 )
Min
Typ
14.7
Max
Units
5
ns
50
ns
T
TCIH
TxCLK IN High Time (Figure 6 )
0.35T
0.5T
0.65T
ns
TCIL
TxCLK IN Low Time (Figure 6 )
0.35T
0.5T
0.65T
ns
TXIT
TxIN, and Power Down pin transition Time
6.0
ns
TXPD
Minimum pulse width for Power Down pin signal
1.5
1
us
Transmitter Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified
Typ
Max
Units
LLHT
Symbol
LVDS Low-to-High Transition Time (Figure 4 )
Parameter
Min
0.75
1.4
ns
LHLT
LVDS High-to-Low Transition Time (Figure 4 )
0.75
1.4
ns
TPPos0
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)
TPPos1
Transmitter Output Pulse Position for Bit 1
TPPos2
TPPos3
TPPos4
Transmitter Output Pulse Position for Bit 4
8.59
TPPos5
Transmitter Output Pulse Position for Bit 5
10.79
TPPos6
Transmitter Output Pulse Position for Bit 6
12.99
13.19
TPPos0
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)
TPPos1
Transmitter Output Pulse Position for Bit 1
TPPos2
f = 65
MHz
−0.20
0
0.20
ns
2.00
2.20
2.40
ns
Transmitter Output Pulse Position for Bit 2
4.20
4.40
4.60
ns
Transmitter Output Pulse Position for Bit 3
6.39
6.59
6.79
ns
8.79
8.99
ns
10.99
11.19
ns
13.39
ns
−0.25
0
0.25
ns
3.32
3.57
3.82
ns
Transmitter Output Pulse Position for Bit 2
6.89
7.14
7.39
ns
TPPos3
Transmitter Output Pulse Position for Bit 3
10.46
10.71
10.96
ns
TPPos4
Transmitter Output Pulse Position for Bit 4
14.04
14.29
14.54
ns
TPPos5
Transmitter Output Pulse Position for Bit 5
17.61
17.86
18.11
ns
TPPos6
Transmitter Output Pulse Position for Bit 6
21.18
21.43
21.68
ns
3
f = 40
MHz
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DS90C363B
Electrical Characteristics
DS90C363B
Transmitter Switching Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless otherwise specified
Symbol
Parameter
Min
Typ
Max
−0.450
0
+0.450
ns
5.26
5.71
6.16
ns
Transmitter Output Pulse Position for Bit 2
10.98
11.43
11.83
ns
TPPos3
Transmitter Output Pulse Position for Bit 3
16.69
17.14
17.54
ns
TPPos4
Transmitter Output Pulse Position for Bit 4
22.41
22.86
23.26
ns
TPPos5
Transmitter Output Pulse Position for Bit 5
28.12
28.57
28.97
ns
TPPos6
Transmitter Output Pulse Position for Bit 6
33.84
34.29
34.69
ns
TSTC
TxIN Setup to TxCLK IN (Figure 6 )
2.5
ns
THTC
TxIN Hold to TxCLK IN (Figure 6 )
0.5
ns
TCCD
TxCLK IN to TxCLK OUT Delay (Figure 7 ) 50% duty cycle input
clock is assumed, T A= −10˚C, and 65MHz for ” Min ”, T A= 70˚C,
and 25MHz for ” Max ”, VCC= 3.6V, R_FB = VCC
3.340
7.211
ns
TxCLK IN to TxCLK OUT Delay (Figure 7 ) 50% duty cycle input
clock is assumed, T A= −10˚C, and 65MHz for ” Min ”, T A= 70˚C,
and 25MHz for ” Max ”, VCC= 3.6V, R_FB = GND
3.011
6.062
ns
TPPos0
Transmitter Output Pulse Position for Bit 0 (Figure 11 ) (Note 5)
TPPos1
Transmitter Output Pulse Position for Bit 1
TPPos2
SSCG
Spread Spectrum Clock support; Modulation frequency with a
linear profile (Note 6)
f = 25
MHz
f = 25
MHz
100kHz ±
2.5%/−5%
f = 40
MHz
100kHz ±
2.5%/−5%
f = 65
MHz
100kHz ±
2.5%/−5%
Units
TPLLS
Transmitter Phase Lock Loop Set (Figure 8 )
10
ms
TPDD
Transmitter Power Down Delay (Figure 10 )
100
ns
Note 5: The Minimum and Maximum Limits are based on statistical analysis of the device performance over process, voltage, and temperature ranges. This
parameter is functionality tested only on Automatic Test Equipment (ATE).
Note 6: Care must be taken to ensure TSTC and THTC are met so input data are sampling correctly. This SSCG parameter only shows the performance of tracking
Spread Spectrum Clock applied to TxCLK IN pin, and reflects the result on TxCLKOUT+ and TxCLK− pins.
AC Timing Diagrams
20098604
FIGURE 1. “Worst Case” Test Pattern
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4
DS90C363B
AC Timing Diagrams
(Continued)
20098605
FIGURE 2. “16 Grayscale” Test Pattern (Notes 7, 8, 9, 10)
Note 7: The worst case test pattern produces a maximum toggling of digital circuits, LVDS I/O and CMOS/TTL I/O.
Note 8: The 16 grayscale test pattern tests device power consumption for a “typical” LCD display pattern. The test pattern approximates signal switching needed
to produce groups of 16 vertical stripes across the display.
Note 9: Figures 1, 2 show a falling edge data strobe (TxCLK IN/RxCLK OUT).
Note 10: Recommended pin to signal mapping. Customer may choose to define differently.
20098630
FIGURE 3. DS90C363B (Transmitter) LVDS Output Load
20098606
FIGURE 4. DS90C363B (Transmitter) LVDS Transition Times
5
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DS90C363B
AC Timing Diagrams
(Continued)
20098608
FIGURE 5. DS90C363B (Transmitter) Input Clock Transition Time
20098610
FIGURE 6. DS90C363B (Transmitter) Setup/Hold and High/Low Times (Falling Edge Strobe)
20098612
FIGURE 7. DS90C363B (Transmitter) Clock In to Clock Out Delay (Falling Edge Strobe)
20098614
FIGURE 8. DS90C363B (Transmitter) Phase Lock Loop Set Time
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6
DS90C363B
AC Timing Diagrams
(Continued)
20098617
FIGURE 9. 21 Parallel TTL Data Inputs Mapped to LVDS Outputs
20098618
FIGURE 10. Transmitter Power Down Delay
7
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DS90C363B
AC Timing Diagrams
(Continued)
20098626
FIGURE 11. Transmitter LVDS Output Pulse Position Measurement
DS90C363B Pin Descriptions — FPD Link Transmitter
I/O
No.
TxIN
Pin Name
I
21
TTL level input. This includes: 6 Red, 6 Green, 6 Blue, and 3 control lines — FPLINE,
FPFRAME and DRDY (also referred to as HSYNC, VSYNC, Data Enable).
TxOUT+
O
3
Positive LVDS differentiaI data output.
TxOUT−
O
3
Negative LVDS differential data output.
FPSHIFT IN
I
1
TTL Ievel clock input. The falling edge acts as data strobe. Pin name TxCLK IN.
R_FB
I
1
Programmable strobe select (See Table 1).
TxCLK OUT+
O
1
Positive LVDS differential clock output.
TxCLK OUT−
O
1
Negative LVDS differential clock output.
PWR DOWN
I
1
TTL level input. Assertion (low input) TRI-STATES the outputs, ensuring low current at power
down. See Applications Information section.
VCC
I
3
Power supply pins for TTL inputs.
GND
I
4
Ground pins for TTL inputs.
PLL VCC
I
1
Power supply pin for PLL.
PLL GND
I
2
Ground pins for PLL.
LVDS VCC
I
1
Power supply pin for LVDS outputs.
LVDS GND
I
3
Ground pins for LVDS outputs.
1
No connect
NC
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Description
8
The DS90C363B are backward compatible with the
DS90C363/DS90CF363, DS90C363A/DS90CF363A and
are a pin-for-pin replacement.
This device may also be used as a replacement for the
DS90CF563 (5V, 65MHz) and DS90CF561 (5V, 40MHz)
FPD-Link Transmitters with certain considerations/
modifications:
1. Change 5V power supply to 3.3V. Provide this supply to
the VCC, LVDS VCC and PLL VCC of the transmitter.
2.
To implement a falling edge device for the DS90C363B,
the R_FB pin (pin 14) may be tied to ground OR left
unconnected (an internal pull-down resistor biases this
pin low). Biasing this pin to Vcc implements a rising edge
device.
SPREAD SPECTRUM CLOCK SUPPORT
The DS90C363B can support Spread Spectrum Clocking
signal type inputs. The DS90C383B outputs will accurately
track Spread Spectrum Clock/Data inputs with modulation
frequencies of up to 100kHz (max.)with either center spread
of ± 2.5% or down spread -5% deviations.
TRANSMITTER INPUT PINS
The DS90C363B transmitter input and control inputs accept
3.3V LVTTL/LVCMOS levels. They are not 5V tolerant.
TRANSMITTER INPUT CLOCK/DATA SEQUENCING
The DS90C363B does not require any special requirement
for sequencing of the input clock/data and PD (PowerDown)
signal. The DS90C363B offers a more robust input sequencing feature where the input clock/data can be inserted after
the release of the PD signal. In the case where the clock/
data is stopped and reapplied, such as changing video mode
within Graphics Controller, it is not necessary to cycle the PD
POWER SOURCES SEQUENCE
In typical applications, it is recommended to have VCC, LVDS
VCC and PLL VCC from the same power source with three
separate de-coupling bypass capacitor groups. There is no
requirement on which VCC entering the device first.
Pin Diagram
DS90C363B
20098623
Typical Application
20098603
9
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DS90C363B
signal. However, there are in certain cases where the PD
may need to be asserted during these mode changes. In
cases where the source (Graphics Source) may be supplying an unstable clock or spurious noisy clock output to the
LVDS transmitter, the LVDS Transmitter may attempt to lock
onto this unstable clock signal but is unable to do so due the
instability or quality of the clock source. The PD signal in
these cases should then be asserted once a stable clock is
applied to the LVDS transmitter. Asserting the PWR DOWN
pin will effectively place the device in reset and disable the
PLL, enabling the LVDS Transmitter into a power saving
standby mode. However, it is still generally a good practice
to assert the PWR DOWN pin or reset the LVDS transmitter
whenever the clock/data is stopped and reapplied but it is
not mandatory for the DS90C363B.
Applications Information
DS90C363B
Pin Diagram
(Continued)
TABLE 1. Programmable Transmitter (DS90C363B)
Pin
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Condition
Strobe Status
R_FB
R_FB = VCC
Rising edge strobe
R_FB
R_FB = GND or NC
Falling edge strobe
10
DS90C363B
Physical Dimensions
inches (millimeters) unless otherwise noted
48-Lead Molded Thin Shrink Small Outline Package, JEDEC
Order Number DS90C363BMT
NS Package Number MTD48
11
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DS90C363B +3.3V Programmable LVDS Transmitter 18-Bit Flat Panel Display (FPD) Link -65 MHz
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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