EMIF02-MIC03M6 2-line IPAD™, EMI filter and ESD protection for microphone Features Pin 1 ■ ■ ■ ■ ■ ■ ■ ■ EMI symmetrical (I/O) low-pass filter High efficiency in EMI filtering Very low PCB space consumption: 1.0 mm x 1.45 mm Very thin package: 0.6 mm max High efficiency in ESD suppression High reliability offered by monolithic integration High reduction of parasitic elements through integration and wafer level packaging. Lead-free and halogen-free package Micro QFN 6 leads 1.45 mm x 1.00 mm (bottom view) Figure 1. Pin configuration (top view) Complies with following standards ■ IEC 61000-4-2 level 4, input and output pins – 8 kV (contact discharge) Application ■ Mobile phones MICR in 1 6 MICR out GND 2 5 GND MICL in 3 4 MICL out Description The EMIF02-MIC03M6 is a 2-line highly integrated device designed to suppress EMI/RFI noise in all systems exposed to electromagnetic interference. Figure 2. This filter includes ESD protection circuitry, which prevents damage to the application when subjected to ESD surges up to 8 kV on all pins. Basic cell configuration Low-pass filter Input Output GND GND GND R = 68 Ω, Cline = 45 pF typ. TM: IPAD is a trademark of STMicroelectronics February 2008 Rev 1 1/10 www.st.com Characteristics EMIF02-MIC03M6 1 Characteristics Table 1. Absolute ratings (limiting values at Tamb = 25 °C unless otherwise specified) Symbol Parameter VPP Value Unit 8 kV 125 °C ESD discharge IEC61000-4-2 contact discharge Junction temperature Tj Top Operating temperature range -40 to + 85 °C Tstg Storage temperature range -55 to +150 °C Table 2. Electrical characteristics (Tamb = 25 °C) Symbol Parameter I VBR Breakdown voltage IRM Leakage current @ VRM VRM Stand-off voltage VCL Clamping voltage Rd Dynamic resistance IPP Peak pulse current RI/O Series resistance between Input & Output Cline Input capacitance per line Symbol IPP IR IRM VCL VBR VRM IRM IR Test conditions VRM VBR VCL V IPP Min. Typ. 6 8 Max. Unit VBR IR = 1 mA IRM VRM = 3 V per line RI/O Tolerance ± 20% 68 Ω VR = 0 V, F = 1 MHz, VOSC = 30 mV 45 pF Cline (1) V 500 nA 1. Tolerance ±20% Figure 3. 0.00 S21 attenuation measurement dB Figure 4. 0.00 -5.00 -10.00 -10.00 -20.00 -15.00 -30.00 Analog cross talk measurements (MIC R / MIC L) dB -40.00 -20.00 -50.00 -25.00 -60.00 -30.00 -80.00 300.0k -40.00 300.0k 2/10 1.0M 3.0M 10.0M 30.0M 100.0M 300.0M 1.0G F (Hz) -70.00 F (Hz) -35.00 3.0G 1.0M 3.0M Xtalk R- L 10.0M 30.0M 100.0M 300.0M 1.0G Xtalk L-R 3.0G EMIF02-MIC03M6 Figure 5. Ordering information scheme ESD response to IEC 61000-4-2 (+8 kV air discharge) on MIC lines Figure 6. ESD response to IEC 61000-4-2 (-8 kV air discharge) on MIC lines vi = 20 V/d vi = 20 V/d Input Input vo = 10 V/d vo = 10 V/d Output Output 20 ns/d 2 20 ns/d Ordering information scheme Figure 7. Ordering information scheme EMIF yy - xxx zz Mx EMI Filter Number of lines Information xxx = application zz = version Package Mx = Micro QFN x leads 3/10 Package information 3 EMIF02-MIC03M6 Package information ● Epoxy meets UL94, V0 In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at www.st.com. Table 3. Micro QFN 1.45 x 1.00 6L dimensions Dimensions D N Ref. Millimeters Inches E 1 2 A A1 1 2 L k Min. Typ. Max. Min. Typ. A 0.50 0.55 0.60 0.020 0.022 0.024 A1 0.00 0.02 0.05 0.000 0.001 0.002 b 0.18 0.25 0.30 0.007 0.010 0.012 D 1.45 0.057 E 1.00 0.039 e 0.50 0.020 Max. b e Figure 8. Footprint in mm [inches] 0.50 [0.020] 0.25 [0.010] 0.60 [0.023] 0.30 1.60 [0.012] [0.063] 4/10 K 0.20 L 0.30 Figure 9. 0.008 0.35 0.40 0.012 0.014 0.016 Marking Dot : Pi n 1 Identification L EMIF02-MIC03M6 Package information Figure 10. Tape and reel specification Dot identifying pin 1 location 3.5 +/- 0.03 1.65 8.0 +/- 0.3 0.75 All dimensions in mm Note: φ 1.5 +/- 0.1 4.00+/-0.1 1.75 +/- 0.1 2.0+/-0.05 L L 1.20 L 4.00 User direction of unreeling Product marking may be rotated by 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. 5/10 Recommendation on PCB assembly EMIF02-MIC03M6 4 Recommendation on PCB assembly 4.1 Stencil opening design 1. General recommendation on stencil opening design a) Stencil opening dimensions: L (Length), W (Width), T (Thickness). Figure 11. Stencil opening dimensions L T b) W General design rule Stencil thickness (T) = 75 ~ 125 µm W Aspect Ratio = ----- ≥ 1.5 T L× W Aspect Area = ---------------------------- ≥ 0.66 2T ( L + W ) 2. Reference design a) Stencil opening thickness: 100 µm b) Stencil opening for leads: Opening to footprint ratio is 90%. Figure 12. Recommended stencil window position 7 µm 7 µm 620 µm 650 µm 15 µm 236 µm 15 µm 250 µm Footprint Stencil window Footprint 6/10 EMIF02-MIC03M6 4.2 4.3 4.4 Recommendation on PCB assembly Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed. 4. Solder paste with fine particles: powder particle size is 20-45 µm. Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. 7/10 Recommendation on PCB assembly 4.5 EMIF02-MIC03M6 Reflow profile Figure 13. ST ECOPACK® recommended soldering reflow profile for PCB mounting Temperature (°C) 260°C max 255°C 220°C 180°C 125 °C 2°C/s recommended 2°C/s recommended 6°C/s max 6°C/s max 3°C/s max 3°C/s max 0 0 1 2 3 4 5 10-30 sec 90 to 150 sec Note: 8/10 6 7 Time (min) 90 sec max Minimize air convection currents in the reflow oven to avoid component movement. EMIF02-MIC03M6 5 Ordering information Ordering information Table 4. Ordering information Order code Marking Package Weight Base qty Delivery mode EMIF02-MIC03M6 L(1) Micro QFN 2.2 mg 3000 Tape and reel (7”) 1. The marking can be rotated by 90° to differentiate assembly location 6 Revision history Table 5. Document revision history Date Revision 13-Feb-2008 1 Changes Initial release 9/10 EMIF02-MIC03M6 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. 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