EP53F8QI 1500 mA Synchronous Buck PWM DC-DC Converter with Integrated Inductor RoHS Compliant; Halogen Free Description Application The EP53F8QI provides high efficiency in a very small footprint. Featuring integrated inductor, the device delivers up to 1500mA of continuous output current. Total solution footprint can be as little as 40mm2. • Wireless wide area networking data cards. • Replacement of inefficient LDOs • Noise Sensitive Applications such as RF, Audio and Video, and high speed IO Output voltage is programmed via an external resistor divider providing a wide range of flexibility while maintaining a very small footprint. • Computing, Computer Peripherals, Storage, Networking, and Instrumentation • USB, DSL, STB, DVR, DTV, and iPC Integration of the inductor reduces conducted and radiated noise providing excellent compatibility with sensitive RF and high speed data applications. Features Integrated Inductor Technology • Total Solution Footprint as Small as 40 mm2 • 3 mm x 3 mm x 1.1 mm QFN Package • Solution Power Density up to 140mW/mm2 • 1500 mA Continuous Output Current • High Efficiency, up to 94 % • Low Ripple Voltage; 8 mVP-P Typical • Power OK Signal with 5 mA Sink Capability • 2.4V to 5.5V Input Voltage Range • Fast Transient Response • 4 MHz Fixed Switching Frequency • Low Dropout Operation: 100 % Duty Cycle • Under Voltage Lockout, Over Current, Short Circuit, and Thermal Protection • Figure 1: Typical Application Circuit Product Performance 95 85 75 Efficiency (%) • 65 55 45 35 25 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 Load Current (A) RoHS Compliant; MSL 3 260 °C Reflow Figure 2: Efficiency, VIN=5V, VOUT=3.7V www.enpirion.com 01542 4/3/2009 Rev:A EP53F8QI Ordering Information Pin Assignments (Top View) Temp Rating Package (°C) -40 to +85 16-pin QFN T&R QFN Evaluation Board Part Number EP53F8QI-T EP53F8QI-E Figure 3: Pin Diagram (Top View) Pin Description PIN NAME FUNCTION 1, 15,16 NC(SW) No Connect. These pins are internally connected to the common drain output of the internal MOSFETs. NC(SW) pins are not to be electrically connected to any external signal, ground, or voltage. However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage. 2-3, PGND Input/Output Power Ground. Connect these pins to the ground electrode of the input and output filter capacitors. Refer to Layout Considerations section for details. 4 AVIN2 Analog input voltage. Connect to AVIN1 only. 5 VFB Feedback Pin for External Voltage Divider Network. Connect a resistor divider to this pin to set the output voltage. Use 100 kΩ, 1% or better for the upper resistor. 6 NC No Connect. 7,8 VOUT Voltage and Power Output. Connect these pins to output capacitor(s). 9 AGND Analog Ground for the Controller Circuits 10 AVIN1 Analog Voltage Input for the Controller Circuits. Connect this pin to PVIN with a 10Ω resistor. Connect a 1 uF capacitor between this pin and AGND. Connect AVIN2 to this pin. 11 POK 12 ENABLE 13-14 PVIN Power OK with an Open Drain Outp t. Refer to Power OK section. Input Enable. A logic high signal on this pin enables the output and initiates a soft start. A logic low signal disables the output and discharges the output to GND. This pin must not be left floating. Input Power Supply. Connect to input supply. Decouple with input capacitor(s) to PGND. ©Enpirion 2009 all rights reserved, E&OE 01542 2 4/3/2009 www.enpirion.com Rev:A EP53F8QI Absolute Maximum Ratings CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended operating conditions is not implied. Stress beyond the absolute maximum ratings may cause permanent damage to the device. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. Absolute Maximum Electrical Ratings MIN MAX Voltages on: PVIN, AVIN, VOUT -0.3 V 6.5 V Voltages on: ENABLE, POK -0.3 V VIN Voltage on: VFB -0.3 V 2.7 V ESD Rating (Human Body Model) 2 kV ESD Rating (Charge Device Model) 500 V Absolute Maximum Thermal Ratings MIN MAX Ambient Operating Range -40 °C +85 °C Storage Temperature Range -65 °C +150 °C Reflow Peak Body Temperature MSL3 (10 s) +260 °C Recommended Operating Conditions PARAMETER SYMBOL MIN MAX VIN 2.4 5.5 Input Voltage Range † UNITS V † Output Voltage Range VOUT 0.6 VIN - VDROPOUT V Output Current ILOAD 0 1500 mA Operating Junction Temperature TJ -40 +125 °C Operating Ambient Temperature TA -40 +85 °C VDROPOUT is defined as (ILOAD x Dropout Resistance) including temperature effect Thermal Characteristics PARAMETER SYMBOL Thermal Shutdown (Junction Temperature) Thermal Shutdown Hysteresis Thermal Resistance: Junction to Ambient (0 LFM) †† TYP MAX UNITS TSD 155 °C TSDH 15 °C θJA 55 °C/W Based on a 2 oz. copper board and proper thermal design in line with JEDEC EIJ/JESD51 standards ©Enpirion 2009 all rights reserved, E&OE 01542 †† MIN 3 4/3/2009 www.enpirion.com Rev:A EP53F8QI Electrical Characteristics Typical values for VIN = 5V and TA =25°C, unless otherwise noted. PARAMETER SYMBOL TEST CONDITIONS MIN TYP UNITS 5.5 V Operating Input Voltage VIN Under Voltage Lockout VUVLO VIN going low to high 2.2 V Under Voltage Lockout VUVLO VIN going high to low 2.1 V VFB TA = 25 °C; VIN = 5V ILOAD = 100 mA VFB Voltage Initial Accuracy 2.4 MAX 0.588 0.600 0.612 V Line Regulation 2.4 V ≤ VIN ≤ 5.5V 0.0031 %/V Load Regulation ILOAD = 0 to 1.5A 0.420 %/A Temperature Variation -40°C ≤ TA ≤ +85°C 0.0012 %/°C Soft Start Slew Rate 0.975 VFB, ENABLE, Pin Input Current (Note 1) 1.5 2.025 V/ms -40°C ≤ TA ≤ +85°C -40 +40 nA ENABLE Voltage Threshold Logic Low 0.0 0.4 V Logic High 1.4 VIN V POK Upper Threshold VOUT Rising 111 % POK Upper Threshold VOUT Falling 102 % POK Lower Threshold VOUT Rising; percent of VOUT Nominal 92 % POK Lower Threshold VOUT Falling; percent of VOUT Nominal 90 % POK Low Voltage ISINK = 5 mA, -40°C ≤ TA ≤ +85°C POK Pin VOH Leakage Current POK High, -40°C ≤ TA ≤ +85°C Shutdown Current ENABLE Low Current Limit Threshold 2.4 V ≤ VIN ≤ 5.5 V, -40°C ≤ TA ≤ +85°C 2.0 Dropout Resistance Operating Frequency 0.15 V 500 nA 14 μA 3.2 A 250 FOSC 0.4 4 360 mΩ MHz Note 1: VFB, ENABLE pin input current specification is guaranteed by design. ©Enpirion 2009 all rights reserved, E&OE 01542 4 4/3/2009 www.enpirion.com Rev:A EP53F8QI 95 95 85 85 75 75 Efficiency (%) Efficiency (%) Typical Performance Characteristics††† 65 55 65 55 45 45 35 35 25 25 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5 Load Current (A) Load Current (A) Efficiency vs. Load Current: VIN = 5.0V, VOUT (from top to bottom) = 3.7, 2.5V, 1.8V, 1.2V Efficiency vs. Load Current: VIN = 3.3V, VOUT (from top to bottom) = 2.5V, 1.8V, 1.2V 20 MHz BW limit 500 MHz BW Output Ripple: VIN = 5V, VOUT = 3.7V, ILOAD = 900mA Output Ripple: VIN = 5V, VOUT = 3.7V, ILOAD = 900mA 20 MHz BW limit 500 MHz BW Output Ripple: VIN = 3.3V, VOUT = 1.8V, ILOAD = 900mA Output Ripple: VIN = 3.3V, VOUT = 1.8V, ILOAD = 900mA ©Enpirion 2009 all rights reserved, E&OE 5 01542 4/3/2009 www.enpirion.com Rev:A EP53F8QI Transient Response: VIN = 3.3V, VOUT = 1.8V Load Step 0 to 1.5A Transient Response: VIN = 5.0V, VOUT = 1.2V Load Step 0 to 1.5A ENABLE ENABLE VOUT VOUT POK POK Startup and Shutdown Waveform VIN = 5.0V, VOUT = 3.7V, ILOAD = 0mA Startup and Shutdown Waveform VIN = 5.0V, VOUT = 3.7V, ILOAD = 900mA ††† Application Circuit in Figure 1 used for typical performance characteristics. ©Enpirion 2009 all rights reserved, E&OE 01542 6 4/3/2009 www.enpirion.com Rev:A EP53F8QI Functional Block Diagram PVIN POK UVLO POK Thermal Limit Current Limit ENABLE NC (SW) Soft Start P-Drive (-) Logic VOUT PWM Comp (+) N-Drive PGND Sawtooth Generator Compensation Network (-) VFB Error Amp (+) DAC VREF BIAS Package Boundary AVIN Figure 4: Functional Block Diagram Functional Description The EP53F8QI leverages advanced CMOS technology to provide high switching frequency, while also maintaining high efficiency. it is within ±10% of nominal. Protection features include under voltage lockout (UVLO), over current protection, short circuit protection, and thermal overload protection. Packaged in a 3 mm x 3 mm x 1.1 mm QFN, the EP53F8QI provides a high degree of flexibility in circuit design while maintaining a very small footprint. High switching frequency allows for the use of very small MLCC input and output filter capacitors. Stability over Wide Range of Operating Conditions The converter uses voltage mode control to provide high noise immunity, low output impedance and excellent load transient response. Most compensation components are integrated into the device, requiring only a single external compensation capacitor. Output voltage is programmed via an external resistor divider. Output voltage can be programmed from 0.6V to VIN-VDROPOUT. POK monitors the output voltage and signals if ©Enpirion 2009 all rights reserved, E&OE 01542 The EP53F8QI utilizes an internal compensation network and is designed to provide stable operation over a wide range of operating conditions. To improve transient performance or reduce output voltage ripple with dynamic loads you have the option to add supplementary capacitance to the output. The EP53F8QI is stable with up to 60 µF of output capacitance without compensation adjustment. Additional output capacitance above 60 µF can be accommodated with compensation adjustment depending on the application. The high switching frequency allows for a wide control loop bandwidth. 7 4/3/2009 www.enpirion.com Rev:A EP53F8QI Soft Start The internal soft start circuit limits inrush current when the device starts up from a power down condition or when the ENABLE pin is asserted “high”. Digital control circuitry sets the VOUT ramp rate to minimize input voltage ripple and inrush current to ensure a glitch-free start up. The soft start ramp rate can be found in the electrical characteristics table. Over Current/Short Circuit Protection When an over current condition occurs, VOUT is pulled low. This condition is maintained for a period of 1.2 ms and then a normal soft start cycle is initiated. If the over current condition still persists, this cycle will repeat. Under Voltage Lockout An under voltage lockout circuit will hold off switching during initial power up until the input voltage reaches sufficient level to ensure proper operation. If the voltage drops below the UVLO threshold the lockout circuitry will again disable switching. Hysteresis is included to prevent chattering between UVLO high and low states. shutdown junction temperature and hysteresis can be found in the thermal characteristics table Power OK The EP53F8QI provides an open drain output to indicate if the output voltage stays within 92% to 111% of the set value. Within this range, the POK output is allowed to be pulled high. Outside this range, POK remains low. However, during transitions such as power up, power down, and dynamic voltage scaling, the POK output will not change state until the transition is complete for enhanced noise immunity. The POK has 5 mA sink capability for events where it needs to feed a digital controller with standard CMOS inputs. When POK is pulled high, the pin leakage current is as low as 500 nA maximum over temperature. This allows a large pull up resistor such as 100 kΩ to be used for minimal current consumption in shutdown mode. The POK output can also be conveniently used as an ENABLE input of the next stage for power sequencing of multiple converters. Enable The ENABLE pin provides means to shut down the converter or initiate normal operation. A logic high will enable the converter to go through the soft start cycle and regulate the output voltage to the desired value. A logic low will allow the device to discharge the output and go into shutdown mode for minimal power consumption. When the output is discharged, an auxiliary NFET turns on and limits the discharge current to 300 mA or below. The ENABLE pin must not be left floating. Thermal Shutdown When excessive power is dissipated in the device, its junction temperature rises. Once the junction temperature exceeds the thermal shutdown temperature, the thermal shutdown circuit turns off the converter, allowing the device to cool. When the junction temperature decreases to a safe operating level, the device will be re-enabled and go through a normal startup process. The specific thermal ©Enpirion 2009 all rights reserved, E&OE 01542 8 4/3/2009 www.enpirion.com Rev:A EP53F8QI Application Information Setting the Output Voltage AVIN Decoupling AVIN should be connected to PVIN using a 10Ω resistor. An 0402 or smaller case size is recommended for this resistor. A 1 µF, 10 V, 0402 MLC capacitor should be connected from AVIN to AGND to provide high frequency decoupling for the control circuitry supply for optimal performance. POK Pull Up Resistor Selection Figure 5: Typical Application Circuit The EP53F8QI uses a simple resistor divider to program the output voltage. Referring to Figure 5, use 237 kΩ, 1% or better for the upper resistor (Ra). The value of the bottom resistor (Rb) in kΩ is given as: Rb = 142.2 kΩ VOUT − 0.6 Where VOUT is the output voltage. Rb should also be a 1% or better resistor. A 5.0pF MLCC capacitor is required in parallel with Ra for compensation. If the POK signal is required for the application. The POK pin must be pulled up through a resistor to any voltage source that can be as high as VIN. The simplest way is to connect POK to the power input of the converter through a resistor. A 100 kΩ pull up resistor is recommended for most applications for minimal current drain from the voltage source and good noise immunity. POK can sink up to 5mA. Layout Recommendation Please refer to the EP53F8QI product page at www.enpirion.com for the most current device layout recommendation, Gerber files, and other manufacturing guidelines. Input and Output Capacitor Selection Low ESR MLC capacitors with X5R or X7R or equivalent dielectric should be used for input and output capacitors. Y5V or equivalent dielectrics lose too much capacitance with frequency, DC bias, and temperature. Therefore, they are not suitable for switchmode DC-DC converter filtering, and must be avoided. The input filter capacitor requirement is a 10 µF, 10V 0805 MLCC capacitor in parallel with a 680pF MLCC capacitor. The 680pF capacitor provides additional high frequency decoupling and is manditory. The 680pF capacitor must be placed closest to the EP53F8QI as shown in Figure 5. The output filter capacitor requirement is a 22 µF, 6.3V, 0805 MLCC for most applications. The output ripple can be reduced by using 2 x 22 µF, 6.3V, 0805 MLC capacitors. ©Enpirion 2009 all rights reserved, E&OE 01542 9 4/3/2009 www.enpirion.com Rev:A EP53F8QI Recommended PCB Footprint Figure 6: EP53F8QI Package PCB Footprint ©Enpirion 2009 all rights reserved, E&OE 01542 10 4/3/2009 www.enpirion.com Rev:A EP53F8QI Package and Mechanical Figure 7: EP53F8QI Package Dimensions Contact Information Enpirion, Inc. 685 Route 202/206 Suite 305 Bridgewater, NJ 08807 Phone: 908-575-7550 Fax: 908-575-0775 Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment used in hazardous environment without the express written authority from Enpirion. ©Enpirion 2009 all rights reserved, E&OE 01542 11 4/3/2009 www.enpirion.com Rev:A