IRF FA57SA50LC

PD - 91650A
FA57SA50LC
HEXFET® Power MOSFET
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Fully Isolated Package
Easy to Use and Parallel
Low On-Resistance
Dynamic dv/dt Rating
Fully Avalanche Rated
Simple Drive Requirements
Low Gate Charge Device
Low Drain to Case Capacitance
Low Internal Inductance
D
VDSS = 500V
RDS(on) = 0.08Ω
G
ID = 57A
S
Description
Third Generation HEXFETs from International Rectifier
provide the designer with the best combination of fast
switching, ruggedized device design, low on-resistance
and cost-effectiveness.
The SOT-227 package is universally preferred for all
commercial-industrial applications at power dissipation
levels to approximately 500 watts. The low thermal
resistance of the SOT-227 contribute to its wide acceptance
throughout the industry.
S O T -2 2 7
Absolute Maximum Ratings
ID @ TC = 25°C
ID @ TC = 100°C
IDM
PD @TC = 25°C
VGS
EAS
IAR
EAR
dv/dt
TJ
TSTG
VISO
Parameter
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current 
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Single Pulse Avalanche Energy‚
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt ƒ
Operating Junction and
Storage Temperature Range
Insulation Withstand Voltage (AC-RMS)
Mounting torque, M4 srew
57
36
228
625
5.0
± 20
725
57
62.5
3.0
-55 to + 150
Units
W
W/°C
V
mJ
A
mJ
V/ns
°C
2.5
1.3
kV
N•m
A
Thermal Resistance
Parameter
RθJC
RθCS
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Junction-to-Case
Case-to-Sink, Flat, Greased Surface
Typ.
Max.
Units
–––
0.05
0.20
–––
°C/W
1
2/1/99
FA57SA50LC
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
Gate Threshold Voltage
gfs
Forward Transconductance
V(BR)DSS
IDSS
Drain-to-Source Leakage Current
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ls
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Internal Source Inductance
Ciss
Coss
Crss
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
IGSS
Min.
500
–––
–––
2.0
43
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.62
–––
–––
–––
–––
–––
–––
–––
225
51
98
32
152
108
118
5.0
Max. Units
Conditions
–––
V
VGS = 0V, ID = 1.0mA
––– V/°C Reference to 25°C, ID = 1mA
0.08
Ω
VGS = 10V, ID = 34A „
4.0
V
V DS = VGS, ID = 250µA
–––
S
VDS = 50V, ID = 34A
50
VDS = 500V, VGS = 0V
µA
500
VDS = 400V, VGS = 0V, TJ = 125°C
200
V GS = 20V
nA
-200
VGS = -20V
338
ID = 57A
77
nC VDS = 400V
147
VGS = 10V, See Fig. 6 and 13 „
–––
VDD = 250V
–––
ID = 57A
ns
–––
R G =2.0Ω (Internal)
–––
RD = 4.3Ω, See Fig. 10 „
–––
nH Between lead,
and center of die contact
––– 10000 –––
VGS = 0V
––– 1500 –––
pF
VDS = 25V
–––
50 –––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
ISM
V SD
t rr
Q rr
ton
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
Forward Turn-On Time
Min. Typ. Max. Units
Conditions
MOSFET symbol
57
––– –––
showing the
A
integral reverse
––– ––– 228
p-n junction diode.
––– ––– 1.3
V
TJ = 25°C, IS = 57A, VGS = 0V „
––– 901 1351
ns
TJ = 25°C, IF = 57A
––– 15
23
µC
di/dt = 100A/µs „
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Notes:
 Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
‚ Starting TJ = 25°C, L = 446µH
ƒ ISD ≤ 57A, di/dt ≤ 200A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 150°C
„ Pulse width ≤ 300µs; duty cycle ≤ 2%.
RG = 25Ω, IAS = 57A. (See Figure 12)
2
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FA57SA50LC
1000
1000
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
100
100
10
4.5V
1
20µs PULSE WIDTH
TJ = 25 °C
0.1
0.1
1
10
4.5V
10
3.0
R DS(on) , Drain-to-Source On Resistance
(Normalized)
TJ = 150 ° C
100
TJ = 25 ° C
10
1
V DS = 50V
20µs PULSE WIDTH
5
6
7
8
9
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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10
100
Fig 2. Typical Output Characteristics
1000
4
1
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
0.1
20µs PULSE WIDTH
TJ = 150 °C
1
0.1
100
VDS , Drain-to-Source Voltage (V)
I D , Drain-to-Source Current (A)
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
TOP
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
TOP
10
ID = 57A
2.5
2.0
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
3
FA57SA50LC
VGS = 0V,
f = 1MHz
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
12000
C, Capacitance (pF)
Ciss
9000
6000
C oss
3000
VGS , Gate-to-Source Voltage (V)
20
15000
ID = 57 A
VDS = 400V
VDS = 250V
VDS = 100V
16
12
8
4
Crss
0
FOR TEST CIRCUIT
SEE FIGURE 13
0
1
10
100
0
-VDS , Drain-to-Source Voltage (V)
60
120
180
240
300
360
QG , Total Gate Charge (nC)
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
1000
1000
TJ = 150 ° C
100
I D , Drain Current (A)
ISD , Reverse Drain Current (A)
OPERATION IN THIS AREA LIMITED
BY RDS(on)
100
TJ = 25 ° C
10
10us
100us
10
1ms
1
0.1
0.2
V GS = 0 V
0.8
1.4
2.0
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
TC = 25 °C
TJ = 150 ° C
Single Pulse
1
2.6
1
10
10ms
100
1000
10000
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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FA57SA50LC
60.0
RD
VDS
VGS
50.0
D.U.T.
I D , Drain Current (A)
RG
+
-VDD
40.0
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
30.0
Fig 10a. Switching Time Test Circuit
20.0
VDS
10.0
90%
0.0
25
50
75
100
125
150
TC , Case Temperature ( ° C)
10%
VGS
Fig 9. Maximum Drain Current Vs.
Case Temperature
td(on)
tr
t d(off)
tf
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJC )
1
0.1
D = 0.50
0.20
0.10
P DM
0.05
0.01
0.02
0.01
0.001
0.00001
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJC + TC
0.0001
0.001
0.01
0.1
1
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
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5
FA57SA50LC
1 5V
L
VDS
D .U .T
RG
IA S
20V
TOP
BOTTOM
1200
D R IV E R
+
V
- DD
0 .0 1 Ω
tp
EAS , Single Pulse Avalanche Energy (mJ)
1500
Fig 12a. Unclamped Inductive Test Circuit
A
ID
25A
35A
57A
900
600
300
0
25
50
75
100
125
150
Starting TJ , Junction Temperature ( °C)
V (B R )D SS
tp
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
IAS
Current Regulator
Same Type as D.U.T.
Fig 12b. Unclamped Inductive Waveforms
50KΩ
QG
12V
.2µF
.3µF
10 V
QGS
+
V
- DS
VGS
VG
3mA
Charge
Fig 13a. Basic Gate Charge Waveform
6
D.U.T.
QGD
IG
ID
Current Sampling Resistors
Fig 13b. Gate Charge Test Circuit
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FA57SA50LC
Peak Diode Recovery dv/dt Test Circuit
+
D.U.T
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
ƒ
+
‚
-
-
„
+

•
•
•
•
RG
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
D=
Period
+
-
VDD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 14. For N-Channel HEXFETS
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7
FA57SA50LC
SOT-227 Package Details
3 8 .3 0 ( 1.5 08 )
3 7 .8 0 ( 1.4 88 )
4 .4 0 (.17 3 )
4 .2 0 (.16 5 )
C HAM FER
2 .0 0 ( .0 7 9 ) X 45 7
L E A D A S S IG M E N T S
E
-A 4
C
S
4
1
3
G
E
IG B T
2 5 .7 0 ( 1.0 12 )
2 5 .2 0 ( .9 9 2 )
6.2 5 ( .24 6 )
1 2.50 ( .4 92 )
A1
-B 1
D
R FULL
7 .50 ( .29 5 )
1 5.00 ( .5 90 )
2
S
G
HEXFET
K2
3
4
1
2
3
2
K1 A2
H E XF R E D
3 0 .2 0 ( 1 .1 89 )
2 9 .8 0 ( 1 .1 73 )
4X
2 .1 0 ( .0 82 )
1 .9 0 ( .0 75 )
8.10 ( .3 19 )
7.70 ( .3 03 )
0 .25 ( .01 0 ) M C A M B M
2 .10 ( .08 2 )
1 .90 ( .07 5 )
12 .3 0 ( .4 84 )
11 .8 0 ( .4 64 )
-C 0.1 2 ( .00 5 )
Tube
QUANTITY PER TU BE IS 1 0
M4 SREW AND W ASHE R IN CLUDED
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Data and specifications subject to change without notice. 2/99
8
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