INTERSIL HA7210Y

HA7210
Data Sheet
February 1999
10kHz to 10MHz, Low Power Crystal
Oscillator
Features
• Single Supply Operation at 32kHz . . . . . . . . . . . . 2V to 7V
The HA7210 is a very low power crystal-controlled oscillators
that can be externally programmed to operate between 10kHz
and 10MHz. For normal operation it requires only the addition
of a crystal. The part exhibits very high stability over a wide
operating voltage and temperature range.
The HA7210 also features a disable mode that switches the
output to a high impedance state. This feature is useful for
minimizing power dissipation during standby and when
multiple oscillator circuits are employed.
• Operating Frequency Range . . . . . . . . . 10kHz to 10MHz
• Supply Current at 32kHz . . . . . . . . . . . . . . . . . . . . . . 5µA
• Supply Current at 1MHz . . . . . . . . . . . . . . . . . . . . . 130µA
• Drives 2 CMOS Loads
• Only Requires an External Crystal for Operation
Applications
• Battery Powered Circuits
Ordering Information
PART NUMBER
(BRAND)
File Number 3389.8
• Remote Metering
TEMP.
RANGE (oC)
PACKAGE
PKG.
NO.
• Embedded Microprocessors
HA7210IP
-40 to 85
8 Ld PDIP
E8.3
• Palm Top/Notebook PC
HA7210IB
(H7210I)
-40 to 85
8 Ld SOIC
M8.15
HA7210Y
-40 to 85
DIE
• Related Literature
- AN9334, Improving HA7210 Start-Up Time
Typical Application Circuit
Pinout
HA7210
(PDIP, SOIC)
TOP VIEW
0.1µF
VDD
1
VDD
1
8
ENABLE
OSC IN
2
7
FREQ 2
OSC OUT
3
6
FREQ 1
VSS
4
5
OUTPUT
8
2
32.768kHz
CRYSTAL
7
(NOTE 1)
HA7210
3
6
4
5
32.768kHz
CLOCK
32.768kHz MICROPOWER CLOCK OSCILLATOR
NOTE:
1. Internal pull-up resistors provided on EN, FREQ1, and FREQ2
inputs.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
HA7210
Simplified Block Diagram
VDD
(NOTE 2)
1
8
ENABLE
EXTERNAL CRYSTAL
OSC IN 2
VDD
3 OSC OUT
RF
15pF
S1B
S1A
VDD - 1.4V
S1C
VDD
OUTPUT
LEVEL
SHIFTER
+
S3
VDD - 3.0V
VDD
VRN
S2
VDD - 2.2V
VDD
15pF
5
BUFFER
-
VRN
S4
VDD - 3.8V
4
BUFFER AMP
IBIAS
VSS
1 OF 4
DECODE
VDD
VDD
(NOTE 2)
P
6
IN
FREQ 1
VDD
RF
(NOTE 2)
OUT
N
P
7
VRN
FREQ 2
OSCILLATOR
FREQUENCY SELECTION TRUTH TABLE
ENABLE
FREQ 1
FREQ 2
SWITCH
1
1
1
S1A, S1B, S1C
10kHz - 100kHz
1
1
0
S2
100kHz - 1MHz
1
0
1
S3
1MHz - 5MHz
1
0
0
S4
5MHz - 10MHz+
0
X
X
X
High Impedance
NOTE:
2. Logic input pull-up resistors are constant current source of 0.4µA.
2
OUTPUT RANGE
HA7210
Absolute Maximum Ratings
Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10V
Voltage (Any Pin) . . . . . . . . . . . . . . . . . . . . VSS -0.3V to VDD +0.3V
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . .4000V
Thermal Resistance (Typical, Note 4)
θJA (oC/W)
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
125
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
170
Maximum Junction Temperature (Plastic Package) . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
Operating Conditions
Temperature Range (Note 3) . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. This product is production tested at 25oC only.
4. θJA is measured with the component mounted on an evaluation PC board in free air.
VSS = GND, TA = 25oC, Unless Otherwise Specified
Electrical Specifications
VDD = 5V
PARAMETER
TEST CONDITIONS
VDD = 3V
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
VDD Supply Range
fOSC = 32kHz
2
5
7
-
-
-
V
IDD Supply Current
fOSC = 32kHz, EN = 0 (Standby)
-
5.0
9.0
-
-
-
µA
fOSC = 32kHz, CL = 10pF (Note 5),
EN = 1, Freq1 = 1, Freq2 = 1
-
5.2
10.2
-
3.6
6.1
µA
fOSC = 32kHz, CL = 40pF, EN = 1,
Freq1 = 1, Freq2 = 1
-
10
15
-
6.5
9
µA
fOSC = 1MHz, CL = 10pF (Note 5),
EN = 1, Freq1 = 0, Freq2 = 1
-
130
200
-
90
180
µA
fOSC = 1MHz, CL = 40pF, EN = 1,
Freq1 = 0, Freq2 = 1
-
270
350
-
180
270
µA
VOH Output High Voltage
IOUT = -1mA
4.0
4.9
-
-
2.8
-
V
VOL Output Low Voltage
IOUT = 1mA
-
0.07
0.4
-
0.1
-
V
IOH Output High Current
VOUT ≥ 4V
-
-10
-5
-
-
-
mA
IOL Output Low Current
VOUT ≤ 0.4V
5.0
10.0
-
-
-
-
mA
Three-State Leakage Current
VOUT = 0V, 5V, TA = 25oC, -40oC
VOUT = 0V, 5V, TA = 85oC
-
0.1
-
-
-
-
nA
-
10
-
-
-
-
nA
IIN Enable, Freq1, Freq2 Input Current
VIN = VSS to VDD
-
0.4
1.0
-
-
-
µA
VIH Input High Voltage Enable, Freq1, Freq2
2.0
-
-
-
-
-
V
VIL Input Low Voltage Enable, Freq1, Freq2
-
-
0.8
-
-
-
V
Enable Time
CL = 18pF, RL = 1kΩ
-
800
-
-
-
-
ns
Disable Time
CL = 18pF, RL = 1kΩ
-
90
-
-
-
-
ns
tr Output Rise Time
10% - 90%, fOSC = 32kHz, CL = 40pF
-
12
25
-
12
-
ns
tf Output Fall Time
10% - 90%, fOSC = 32kHz, CL = 40pF
-
12
25
-
14
-
ns
Duty Cycle, Packaged Part Only (Note 6)
CL = 40pF, fOSC = 1MHz
40
54
60
-
-
-
%
Duty Cycle, (See Typical Curves)
CL = 40pF, fOSC = 32kHz
-
41
-
-
44
-
%
Frequency Stability vs Supply Voltage
fOSC = 32kHz, VDD = 5V, CL = 10pF
-
1
-
-
-
-
ppm/V
Frequency Stability vs Temperature
fOSC = 32kHz, VDD = 5V, CL = 10pF
-
0.1
-
-
-
-
ppm/oC
Frequency Stability vs Load
fOSC = 32kHz, VDD = 5V, CL = 10pF
-
0.01
-
-
-
-
ppm/pF
NOTES:
5. Calculated using the equation IDD = IDD (No Load) + (VDD) (fOSC)(CL)
6. Duty cycle will vary with supply voltage, oscillation frequency, and parasitic capacitance on the crystal pins.
3
HA7210
Test Circuit
0.1µF
1VP-P
+5V
8 ENABLE
1
7 FREQ 2
2
50Ω
1000pF
HA7210
3
4
6 FREQ 1
5
CL
VOUT
18pF
FIGURE 1.
In production the HA7210 is tested with a 32kHz and a
1MHz crystal. However for characterization purposes data
was taken using a sinewave generator as the frequency
determining element, as shown in Figure 1. The 1VP-P input
is a smaller amplitude than what a typical crystal would
generate so the transitions are slower. In general the
Generator data will show a “worst case” number for IDD,
duty cycle, and rise/fall time. The Generator test method is
useful for testing a variety of frequencies quickly and
provides curves which can be used for understanding
performance trends. Data for the HA7210 using crystals has
also been taken. This data has been overlaid onto the
generator data to provide a reference for comparison.
Application Information
Theory Of Operation
The HA7210 is a Pierce Oscillator optimized for low power
consumption, requiring no external components except for a
bypass capacitor and a Parallel Mode Crystal. The Simplified
Block Diagram shows the Crystal attached to pins 2 and 3, the
Oscillator input and output. The crystal drive circuitry is detailed
showing the simple CMOS inverter stage and the P-channel
device being used as biasing resistor RF. The inverter will
operate mostly in its linear region increasing the amplitude of
the oscillation until limited by its transconductance and voltage
rails, VDD and VRN. The inverter is self biasing using RF to
center the oscillating waveform at the input threshold. Do not
interfere with this bias function with external loads or excessive
leakage on pin 2. Nominal value for RF is 17MΩ in the lowest
frequency range to 7MΩ in the highest frequency range.
The HA7210 optimizes its power for 4 frequency ranges
selected by digital inputs Freq1 and Freq2 as shown in the
Block Diagram. Internal pull up resistors (constant current
0.4µA) on Enable, Freq1 and Freq2 allow the user simply to
leave one or all digital inputs not connected for a
corresponding “1” state. All digital inputs may be left open for
10kHz to 100kHz operation.
A current source develops 4 selectable reference voltages
through series resistors. The selected voltage, VRN , is
buffered and used as the negative supply rail for the
oscillator section of the circuit. The use of a current source in
the reference string allows for wide supply variation with
minimal effect on performance. The reduced operating
4
voltage of the oscillator section reduces power consumption
and limits transconductance and bandwidth to the frequency
range selected. For frequencies at the edge of a range, the
higher range may provide better performance.
The OSC OUT waveform on pin 3 is squared up through a series
of inverters to the output drive stage. The Enable function is
implemented with a NAND gate in the inverter string, gating the
signal to the level shifter and output stage. Also during Disable
the output is set to a high impedance state useful for minimizing
power during standby and when multiple oscillators are OR’ed to
a single node.
Design Considerations
The low power CMOS transistors are designed to consume
power mostly during transitions. Keeping these transitions
short requires a good decoupling capacitor as close as
possible to the supply pins 1 and 4. A ceramic 0.1µF is
recommended. Additional supply decoupling on the circuit
board with 1µF to 10µF will further reduce overshoot, ringing
and power consumption. The HA7210, when compared to a
crystal and inverter alone, will speed clock transition times,
reducing power consumption of all CMOS circuitry run from
that clock.
Power consumption may be further reduced by minimizing the
capacitance on moving nodes. The majority of the power will
be used in the output stage driving the load. Minimizing the
load and parasitic capacitance on the output, pin 5, will play
the major role in minimizing supply current. A secondary
source of wasted supply current is parasitic or crystal load
capacitance on pins 2 and 3. The HA7210 is designed to work
with most available crystals in its frequency range with no
external components required. Two 15pF capacitors are
internally switched onto crystal pins 2 and 3 on the HA7210 to
compensate the oscillator in the 10kHz to 100kHz frequency
range.
The supply current of the HA7210 may be approximately
calculated from the equation:
IDD = IDD(Disabled) + VDD × fOSC × CL where:
IDD = Total supply current
VDD = Total voltage from VDD (pin 1) to VSS (pin 4)
fOSC = Frequency of Oscillation
CL = Output (pin 5) load capacitance
EXAMPLE #1:
VDD = 5V, fOSC = 100kHz, CL = 30pF
IDD(Disabled) = 4.5µA (Figure 10)
IDD = 4.5µA + (5V)(100kHz)(30pF) = 19.5µA
Measured IDD = 20.3µA
EXAMPLE #2:
VDD = 5V, fOSC = 5MHz, CL = 30pF
IDD (Disabled) = 75µA (Figure 9)
IDD = 75µA + (5V)(5MHz)(30pF) = 825µA
Measured IDD = 809µA
HA7210
Crystal Selection
For general purpose applications, a Parallel Mode Crystal is
a good choice for use with the HA7210. However for
applications where a precision frequency is required, the
designer needs to consider other factors.
Crystals are available in two types or modes of oscillation,
Series and Parallel. Series Mode crystals are manufactured
to operate at a specified frequency with zero load
capacitance and appear as a near resistive impedance when
oscillating. Parallel Mode crystals are manufactured to
operate with a specific capacitive load in series, causing the
crystal to operate at a more inductive impedance to cancel
the load capacitor. Loading a crystal with a different
capacitance will “pull” the frequency off its value.
The HA7210 has 4 operating frequency ranges. The higher
three ranges do not add any loading capacitance to the
oscillator circuit. The lowest range, 10kHz to 100kHz,
automatically switches in two 15pF capacitors onto OSC IN
and OSC OUT to eliminate potential start-up problems.
These capacitors create an effective crystal loading
capacitor equal to the series combination of these two
capacitors. For the HA7210 in the lowest range, the effective
loading capacitance is 7.5pF. Therefore the choice for a
crystal, in this range, should be a Parallel Mode crystal that
requires a 7.5pF load.
In the higher 3 frequency ranges, the capacitance on OSC
IN and OSC OUT will be determined by package and layout
parasitics, typically 4 to 5pF. Ideally the choice for crystal
should be a Parallel Mode set for 2.5pF load. A crystal
manufactured for a different load will be “pulled” from its
nominal frequency (see Crystal Pullability).
frequency. In Method two these two goals can be at odds
with each other; either the oscillator is trimmed to frequency
by de-tuning the load circuit, or stability is increased at the
expense of absolute frequency accuracy.
Method one allows these two conditions to be met
independently. The two fixed capacitors, C1 and C2 , provide
the optimum load to the oscillator and crystal. C3 adjusts the
frequency at which the circuit oscillates without appreciably
changing the load (and thus the stability) of the system.
Once a value for C3 has been determined for the particular
type of crystal being used, it could be replaced with a fixed
capacitor. For the most precise control over oscillator
frequency, C3 should remain adjustable.
This three capacitor tuning method will be more accurate
and stable than method two and is recommended for 32kHz
tuning fork crystals; without it they may leap into an overtone
mode when power is initially applied.
Method two has been used for many years and may be
preferred in applications where cost or space is critical. Note
that in both cases the crystal loading capacitors are
connected between the oscillator and VDD ; do not use VSS
as an AC ground. The Simplified Block Diagram shows that
the oscillating inverter does not directly connect to VSS but is
referenced to VDD and VRN . Therefore VDD is the best AC
ground available.
+5V
C1
XTAL
2
OSC IN
C2
3
OSC OUT
1
VDD
+
-
+5V
VREG
HA7210
C1
C2
2 XTAL
C3
OSC IN
FIGURE 3.
3
1
OSC OUT
VDD
+
-
VREG
HA7210
FIGURE 2.
Frequency Fine Tuning
Two Methods will be discussed for fine adjustment of the
crystal frequency. The first and preferred method (Figure 2),
provides better frequency accuracy and oscillator stability
than method two (Figure 3). Method one also eliminates
start-up problems sometimes encountered with 32kHz
tuning fork crystals.
For best oscillator performance, two conditions must be met:
the capacitive load must be matched to both the inverter and
crystal to provide ideal conditions for oscillation, and the
frequency of the oscillator must be adjustable to the desired
5
Typical values of the capacitors in Figure 2 are shown below.
Some trial and error may be required before the best
combination is determined. The values listed are total
capacitance including parasitic or other sources. Remember
that in the 10kHz to 100kHz frequency range setting the
HA7210 switches in two internal 15pF capacitors.
CRYSTAL
FREQUENCY
LOAD CAPS
C1, C2
TRIMMER CAP
C3
32kHz
33pF
5pF to 50pF
1MHz
33pF
5pF to 50pF
2MHz
25pF
5pF to 50pF
4MHz
22pF
5pF to 100pF
HA7210
Crystal Pullability
Layout Considerations
Figure 4 shows the basic equivalent circuit for a crystal and
its loading circuit.
Due to the extremely low current (and therefore high
impedance) the circuit board layout of the HA7210 must be
given special attention. Stray capacitance should be
minimized. Keep the oscillator traces on a single layer of the
PCB. Avoid putting a ground plane above or below this layer.
The traces between the crystal, the capacitors, and the OSC
pins should be as short as possible. Completely surround
the oscillator components with a thick trace of VDD to
minimize coupling with any digital signals. The final
assembly must be free from contaminants such as solder
flux, moisture, or any other potential source of leakage. A
good solder mask will help keep the traces free of moisture
and contamination over time.
CM
VDD
RM
LM
C1
2
OSC IN
C2
3
OSC OUT
C0
FIGURE 4.
Where:
CM = Motional Capacitance
LM = Motional Inductance
RM = Motional Resistance
C0 = Shunt Capacitance
Further Reading
1
C CL = --------------------------- = Equivalent Crystal Load
1
1
 ------ + -------
C

1 C2
Al Little “HA7210 Low Power Oscillator: Micropower Clock
Oscillator and Op Amps Provide System Shutdown for Battery
Circuits”. Harris Semiconductor Application Note AN9317.
Robert Rood “Improving Start-Up Time at 32kHz for the
HA7210 Low Power Crystal Oscillator”. Harris Semiconductor
Application Note AN9334.
If loading capacitance is connected to a Series Mode
Crystal, the new Parallel Mode frequency of resonance may
be calculated with the following equation:
S. S. Eaton “Timekeeping Advances Through COS/MOS
Technology”. Harris Semiconductor Application Note
ICAN-6086.
CM
f P = f S 1 + ---------------------------------2(C + C )
E. A. Vittoz, et. al. “High-Performance Crystal Oscillator
Circuits: Theory and Application”. IEEE Journal of SolidState Circuits, Vol. 23, No. 3, June 1988, pp774-783.
Where:
fP = Parallel Mode Resonant Frequency
fS = Series Mode Resonant Frequency
M. A. Unkrich, et. al. “Conditions for Start-Up in Crystal
Oscillators”. IEEE Journal of Solid-State Circuits, Vol. 17,
No. 1, Feb. 1982, pp87-90.
In a similar way, the Series Mode resonant frequency may
be calculated from a Parallel Mode crystal and then you may
calculate how much the frequency will “pull” with a new load.
Marvin E. Frerking “Crystal Oscillator Design and
Temperature Compensation”. New York: Van NostrandReinhold, 1978. Pierce Oscillators Discussed pp56-75.
0
CL
6
HA7210
Typical Performance Curves
CL = 40pF, fOSC = 5MHz, VDD = 5V, VSS = GND
1.0V/DIV.
CL = 18pF, fOSC = 5MHz, VDD = 5V, VSS = GND
20.0ns/DIV.
1.0V/DIV.
FIGURE 5. OUTPUT WAVEFORM (CL = 40pF)
FIGURE 6. OUTPUT WAVEFORM (CL = 18pF)
26
1050
fIN = 5MHz, EN = 1, F1 = 0, F2 = 0, CL = 30pF, VDD = 5V
EN = 1, F1 = 1, F2 = 1, fIN = 100kHz, CL = 30pF, VDD = 5V
25
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
1000
GENERATOR (1VP-P) (NOTE)
950
900
850
XTAL AT 25oC
800
24
GENERATOR (1VP-P) (NOTE)
23
22
21
20
XTAL AT 25oC
19
750
-100
-50
0
50
100
18
-100
150
-50
TEMPERATURE (oC)
50
100
150
FIGURE 8. SUPPLY CURRENT vs TEMPERATURE
350
7.5
fIN = 5MHz, EN = 0, F1 = 0, F2 = 0, VDD = 5V
EN = 0, F1 = 1, F2 = 1, fIN = 100kHz, VDD = 5V
300
7
250
GENERATOR (1VP-P) (NOTE)
200
150
XTAL AT 25oC
100
50
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
0
TEMPERATURE (oC)
FIGURE 7. SUPPLY CURRENT vs TEMPERATURE
6.5
6
GENERATOR (1VP-P) (NOTE)
5.5
5
XTAL AT 25oC
4.5
0
-100
-50
0
50
100
150
TEMPERATURE (oC)
FIGURE 9. DISABLE SUPPLY CURRENT vs TEMPERATURE
NOTE:
20.0ns/DIV.
Refer to Test Circuit (Figure 1).
7
4
-100
-50
0
50
100
150
TEMPERATURE (oC)
FIGURE 10. DISABLE SUPPLY CURRENT vs TEMPERATURE
HA7210
Typical Performance Curves
(Continued)
1400
3000
EN = 1, F1 = 0, F2 =1, CL = 18pF, GENERATOR (1VP-P) (NOTE)
EN = 1, F1 = 0, F2 = 0, CL = 18pF, GENERATOR (1VP-P) (NOTE)
1200
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
2500
VDD = +8V
2000
1500
VDD = +5V
1000
500
VDD = +8V
1000
800
VDD = +5V
600
VDD = +3V
400
200
0
0
4
5
6
7
8
9
10
11
0
1
2
FREQUENCY (MHz)
EN = 1, F1 = 0, F2 = 0, CL = 18pF, GENERATOR (1VP-P) (NOTE)
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
250
VDD = +8V
200
VDD = +5V
150
100
VDD = +3V
50
40
VDD = +8V
30
VDD = +5V
20
10
VDD = +3V
0
0
0
100 200 300 400 500 600 700 800 900 1000 1100
0
10
20
FREQUENCY (kHz)
30
40
50
60
70
80
90
100 110
FREQUENCY (kHz)
FIGURE 13. SUPPLY CURRENT vs FREQUENCY
FIGURE 14. SUPPLY CURRENT vs FREQUENCY
EN = 0, F1 = 0, F2 = 0, CL = 18pF, GENERATOR (1VP-P) (NOTE)
EN = 0, F1 = 0, F2 = 1, CL = 18pF, GENERATOR (1VP-P) (NOTE)
120
VDD = +8V
110
VDD = +5V
100
200
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
6
50
EN = 1, F1 = 0, F2 = 0, CL = 18pF, GENERATOR (1VP-P) (NOTE)
150
100
50
VDD = +8V
VDD = +5V
90
80
70
60
VDD = +3V
50
40
VDD = +3V
30
4
5
6
7
8
FREQUENCY (MHz)
9
10
11
FIGURE 15. DISABLED SUPPLY CURRENT vs FREQUENCY
NOTE:
5
FIGURE 12. SUPPLY CURRENT vs FREQUENCY
300
0
4
FREQUENCY (MHz)
FIGURE 11. SUPPLY CURRENT vs FREQUENCY
250
3
Refer to Test Circuit (Figure 1).
8
0
1
2
3
4
5
FREQUENCY (MHz)
FIGURE 16. DISABLE SUPPLY CURRENT vs FREQUENCY
6
HA7210
Typical Performance Curves
(Continued)
EN = 0, F1 = 1, F2 = 1, CL = 18pF, GENERATOR (1VP-P) (NOTE)
EN = 0, F1 = 1, F2 = 0, CL = 18pF, GENERATOR (1VP-P) (NOTE)
35
11
VDD = +5V
25
20
VDD = +8V
10
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
VDD = +8V
30
VDD = +3V
15
9
8
7
VDD = +5V
6
5
4
VDD = +3V
10
3
5
2
0
100 200 300 400 500 600 700 800 900 1000 1100
0
10
20
30
FIGURE 17. DISABLE SUPPLY CURRENT vs FREQUENCY
3000
40
50
60
70
80
90
100 110
FREQUENCY (kHz)
FREQUENCY (kHz)
FIGURE 18. DISABLE SUPPLY CURRENT vs FREQUENCY
EN = 1, F1 = 0, F2 = 1, VDD = +5V, GENERATOR (1VP-P) (NOTE)
EN = 1, F1 = 0, F2 = 0, VDD = +5V, GENERATOR (1VP-P) (NOTE)
1400
CL = 40pF
1200
2500
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
CL = 40pF
2000
1500
CL = 18pF
1000
1000
800
CL = 18pF
600
400
200
500
0
4
5
6
7
8
9
10
0
11
1
2
FREQUENCY (MHz)
3
FIGURE 19. SUPPLY CURRENT vs FREQUENCY
6
EN = 1, F1 = 1, F2 = 1, VDD = +5V, GENERATOR (1VP-P) (NOTE)
EN = 1, F1 = 1, F2 = 0, VDD = +5V, GENERATOR (1VP-P) (NOTE)
35
CL = 40pF
CL = 40pF
30
250
200
150
CL = 18pF
100
50
SUPPLY CURRENT (µA)
SUPPLY CURRENT (µA)
5
FIGURE 20. SUPPLY CURRENT vs FREQUENCY
300
25
20
CL = 18pF
15
10
5
0
0
100 200 300 400 500 600 700 800 900 1000 1100
FREQUENCY (kHz)
FIGURE 21. SUPPLY CURRENT vs FREQUENCY
NOTE:
4
FREQUENCY (MHz)
Refer to Test Circuit (Figure 1).
9
0
0
10
20
30
40
50
60
70
FREQUENCY (kHz)
80
90
100 110
FIGURE 22. SUPPLY CURRENT vs FREQUENCY
HA7210
Typical Performance Curves
(Continued)
fIN = 100kHz, F1 = 1, F2 = 1, CL = 30pF, VDD = 5V
fIN = 5MHz, F1 = 0, F2 = 0, CL = 30pF, VDD = 5V
60
70
55
60
XTAL AT 25oC
DUTY CYCLE (%)
DUTY CYCLE (%)
GENERATOR (1VP-P) (NOTE)
50
45
40
XTAL AT 25oC
50
40
30
GENERATOR (1VP-P) (NOTE)
35
20
30
-100
-50
0
50
100
10
-100
150
-50
0
TEMPERATURE (oC)
FIGURE 23. DUTY CYCLE vs TEMPERATURE
F1 = F2 = 0, VDD = 5V, CL = 18pF, C1 = C2 = 0
DATA COLLECTED USING CRYSTALS
AT EACH FREQUENCY
DATA COLLECTED USING CRYSTALS
AT EACH FREQUENCY
65
DUTY CYCLE (%)
DUTY CYCLE (%)
150
F1 = 0, F2 = 1, VDD = 5V, CL = 18pF, C1 = C2 = 0
70
60
55
50
60
55
50
45
F1 = 0, F2 = 0 RECOMMENDED FOR 5MHz TO 10MHz RANGE
F1 = 0, F2 = 1 RECOMMENDED FOR 1MHz TO 5MHz RANGE
45
40
0
5
10
FREQUENCY (MHz)
15
20
0
FIGURE 25. DUTY CYCLE vs FREQUENCY
1
2
3
4
5
6
FREQUENCY (MHz)
7
8
9
FIGURE 26. DUTY CYCLE vs FREQUENCY
F1 = 1, F2 = 0, VDD = 5V, CL = 18pF, C1 = C2 = 0
F1 = F2 = 1, VDD = 5V, CL = 18pF, C1 = C2 = 0
47
65
DATA COLLECTED USING CRYSTALS
AT EACH FREQUENCY
DATA COLLECTED USING CRYSTALS
AT EACH FREQUENCY
46
DUTY CYCLE (%)
60
DUTY CYCLE (%)
100
FIGURE 24. DUTY CYCLE vs TEMPERATURE
70
65
50
TEMPERATURE (oC)
55
50
45
44
43
42
45
41
F1 = 1, F2 = 1 RECOMMENDED
FOR 10kHz TO 100kHz RANGE
F1 = 1, F2 = 0 RECOMMENDED FOR 100kHz TO 1MHz RANGE
40
40
0
500
1000
1500
2000
2500
3000
FREQUENCY (kHz)
FIGURE 27. DUTY CYCLE vs FREQUENCY
NOTE:
Refer to Test Circuit (Figure 1).
10
3500
0
50
100
150
FREQUENCY (kHz)
FIGURE 28. DUTY CYCLE vs FREQUENCY
200
HA7210
Typical Performance Curves
(Continued)
30
20
6
10MHz
15
10
5
0
-5
-10
-15
EDGE JITTER (% OF PERIOD)
FREQUENCY CHANGE (PPM)
VDD = 5V, CL = 30pF, GENERATOR (1VP-P) (NOTE)
32kHz
1MHz
5MHz
25
5
4
fIN = 5MHz, F1 = 0, F2 = 0
3
2
1
fIN = 100kHz, F1 = 1, F2 = 1
DEVIATION FROM FREQUENCY AT 5.0V
-20
2
4
VDD SUPPLY VOLTAGE (V)
0
-100
6
FIGURE 29. FREQUENCY CHANGE vs VDD
-50
fIN = 5MHz, F1 = 0, F2 = 0, CL = 30pF, VDD = 5V
150
fIN = 100kHz, F1 = 1, F2 = 1, CL = 30pF, VDD = 5V
12
12
tf GENERATOR (1VP-P) (NOTE)
11
tf GENERATOR (1VP-P) (NOTE)
11
RISE/FALL TIME (ns)
10
10
9
8
tf XTAL AT 25oC
7
6
tr GENERATOR (1VP-P) (NOTE)
5
tr XTAL AT 25oC
4
3
2
-100
tr GENERATOR (1VP-P) (NOTE)
9
8
tf XTAL AT 25oC
7
6
5
tr XTAL AT 25oC
4
3
-50
0
50
100
2
-100
150
-50
0
TEMPERATURE (oC)
50
100
150
TEMPERATURE (oC)
FIGURE 31. RISE/FALL TIME vs TEMPERATURE
FIGURE 32. RISE/FALL TIME vs TEMPERATURE
VDD = 5V, GENERATOR (1VP-P) (NOTE)
CL = 18pF, GENERATOR (1VP-P) (NOTE)
30
15
tf (fIN = 100kHz)
tf (fIN = 5MHz)
14
13
25
tf (fIN = 5MHz)
tr
(fIN = 5MHz)
20
tr (fIN = 100kHz)
15
10
RISE/FALL TIME (ns)
RISE/FALL TIME (ns)
100
FIGURE 30. EDGE JITTER vs TEMPERATURE
13
RISE/FALL TIME (ns)
0
50
TEMPERATURE (oC)
tf (fIN = 100kHz)
12
tr (fIN = 5MHz)
11
tr (fIN = 100kHz)
10
9
8
7
6
5
5
10
20
30
40
50
60
70
80
CL (pF)
FIGURE 33. RISE/FALL TIME vs CL
NOTE:
Refer to Test Circuit (Figure 1).
11
90
100 110
4
2
3
4
5
6
VDD (+V)
7
FIGURE 34. RISE/FALL TIME vs VDD
8
9
HA7210
Typical Performance Curves
(Continued)
F1 = 0, F2 = 0
540
436.5µA/V
460
420
180
380
170
178o
1µF
1000pF
340
2
300
160
3
150
100Ω
50Ω
HA7210
260
140
F1 = 0, F2 = 1
460
420
380
311.6µA/V
340
300
180
260
1000pF
2
50Ω
170
177o
1µF
160
3
150
100Ω
HA7210
140
130
10K
100K
1M
FREQUENCY (Hz)
10K
10M
VDD = 5V, VSS = GND
240
VDD = 5V, VSS = GND
20
F1 = 1, F2 = 0
200
156.7µA/V
180
160
176.6o
140
120
180
1000pF
170
1µF
100
160
2
50Ω
10K
F1 = 1, F2 = 1
15
TRANSCONDUCTANCE (µA/V)
220
3
150
100Ω
HA7210
140
130
10M
100K
1M
FREQUENCY (Hz)
10M
FIGURE 36. TRANSCONDUCTANCE vs FREQUENCY
PHASE (DEGREES)
TRANSCONDUCTANCE (µA/V)
FIGURE 35. TRANSCONDUCTANCE vs FREQUENCY
100K
1M
FREQUENCY (Hz)
6.56µA/V
10
5
180
0
170
1000pF
160
150
140
2
3
100Ω
50Ω
HA7210
10K
FIGURE 37. TRANSCONDUCTANCE vs FREQUENCY
166o
1µF
100K
FREQUENCY (Hz)
130
120
PHASE (DEGREES)
500
PHASE (DEGREES)
TRANSCONDUCTANCE (µA/V)
580
VDD = 5V, VSS = GND
500
PHASE (DEGREES)
TRANSCONDUCTANCE (µA/V)
VDD = 5V, VSS = GND
620
110
1M
FIGURE 38. TRANSCONDUCTANCE vs FREQUENCY
F1 = F2 = 1, VDD = 5V, CL = 18pF, TA = 25oC, fOSC = 32.768kHz
60
DUTY CYCLE (%)
55
EPSON PART #
C-001R32.768K-A
50
XTAL
45
NDK PART #
MX-38
RS
3
OSC OUT
2
OSC IN
40
HA7210
35
0
20
40
60
RS (kΩ)
80
100
120
NOTE: Figure 39 (Duty Cycle vs RS at 32kHz) should only be used for 32kHz crystals. RS may be used at other frequencies to adjust Duty Cycle
but experimentation will be required to find an appropriate value. The RS value will be proportional to the effective series resistance of the crystal
being used.
NOTE:
Refer to Test Circuit (Figure 1).
12
FIGURE 39. DUTY CYCLE vs RS at 32kHz
HA7210
Die Characteristics
SUBSTRATE POTENTIAL:
VSS
DIE DIMENSIONS:
PASSIVATION:
68 mils x 64 mils x 14 mils
Type: Nitride (Si3N4) Over Silox (SiO2, 3% Phos)
Silox Thickness: 7kÅ ±1kÅ
Nitride Thickness: 8kÅ ±1kÅ
METALLIZATION:
Type: SiAl
Thickness: 10kÅ ±1kÅ
Metallization Mask Layout
(1) VDD
(8) ENABLE
HA7210
(7) FREQ 2
CRYSTAL (2)
13
OUTPUT (5)
(6) FREQ 1
VSS (4)
CRYSTAL (3)
HA7210
Dual-In-Line Plastic Packages (PDIP)
E8.3 (JEDEC MS-001-BA ISSUE D)
N
8 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AE
D
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8, 10
eA
C
0.008
0.014
0.204
C
D
0.355
0.400
9.01
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between
English and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section
2.2 of Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated
in JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch
(0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions.
Dambar protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3,
E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch
(0.76 - 1.14mm).
14
MILLIMETERS
e
0.100 BSC
eA
0.300 BSC
eB
-
L
0.115
N
8
0.355
10.16
2.54 BSC
7.62 BSC
0.430
-
0.150
2.93
10.92
3.81
8
5
6
7
4
9
Rev. 0 12/93
HA7210
Small Outline Plastic Packages (SOIC)
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
N
INDEX
AREA
H
0.25(0.010) M
B M
E
INCHES
-B-
1
2
SYMBOL
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
α
A1
B
0.25(0.010) M
C
C A M
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.1890
0.1968
4.80
5.00
3
E
0.1497
0.1574
3.80
4.00
4
e
0.10(0.004)
MILLIMETERS
MIN
H
0.050 BSC
1.27 BSC
-
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
8o
0o
N
α
8
0o
8
7
8o
Rev. 0 12/93
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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15
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