HCMS-2919, HCMS-2976 High Performance CMOS 5x7 AlphaNumeric GaN Blue Display Data Sheet Description Features These products are high performance, easy to use dot matrix displays driven by on-board CMOS IC. Each display can be directly interfaced with a microprocessor, thus eliminating the need for cumbersome interface components. The serial IC interface allows higher character count information displays with a minimum of data lines. The 5x7 pixel format allows the user great freedom to generate userdefined characters. These displays are stackable in the x- and y-directions, making them ideal for high character count displays • Easy to Use • Interfaces Directly with Microprocessors • 0.15" and 0.20" Character Height in 8 Character Package • Rugged X- and Y-Stackable Package • Serial Input • Convenient Brightness Controls • Wave Solderable • Low Power CMOS Technology • TTL Compatible Applications • Telecommunications Equipment • Portable Data Entry Devices • Computer Peripherals • Medical Equipment • Test Equipment • Business Machines • Avionics • Industrial Controls Package Dimensions 35.56 (1.400) MAX. 2.22 (0.087) SYM. 4.45 (0.175) TYP. PIN FUNCTION ASSIGNMENT TABLE 26 3.71 (0.146) TYP. 0 1 2 3 4 5 6 10.16 (0.400) MAX. 7 3 2.11 (0.083) TYP. DATE CODE (YEAR, WEEK) PIN # 1 IDENTIFIER INTENSITY CATEGORY COLOR BIN PART NUMBER COUNTRY OF ORIGIN HCMS-291X YYWW 0.51 (0.020) X Z COO 0.25 (0.010) 5.08 (0.200) 4.32 (0.170) TYP. 2.54 (0.100) SYM. 0.51 ± 0.13 TYP. (0.020 ± 0.005) 1.27 SYM. (0.050) PIN # FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 NO PIN NO PIN V LED NO PIN NO PIN NO PIN GND LED NO PIN NO PIN V LED NO PIN NO PIN NO PIN DATA IN RS NO PIN CLOCK CE BLANK GND LOGIC SEL V LOGIC NO PIN RESET OSC DATA OUT 7.62 (0.300) 2.54 ± 0.13 (0.100 ± 0.005) TYP. (NON ACCUM.) NOTES: 1. DIMENSIONS ARE IN mm (INCHES). 2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH). 3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY. Figure 1. HCMS-2919 package dimension 42.93 (1.690) MAX. 2.67 (0.105) SYM. 5.36 (0.211) TYP. PIN FUNCTION ASSIGNMENT TABLE 26 4.57 (0.180) TYP. 1 2 3 4 5 6 7 8 11.43 (0.450) MAX. 3 2.54 (0.100) TYP. PIN # 1 IDENTIFIER DATE CODE (YEAR, WEEK) INTENSITY CATEGORY COLOR BIN COUNTRY OF ORIGIN PART NUMBER 0.51 (0.020) HCMS-297X YYWW X Z COO 0.25 (0.010) 5.31 (0.209) 3.71 (0.146) TYP. 6.22 (0.245) SYM. 0.51 ± 0.13 (0.020 ± 0.005) TYP. 2.54 ± 0.13 TYP. (0.100 ± 0.005) (NON ACCUM.) NOTES: 1. DIMENSIONS ARE IN mm (INCHES). 2. UNLESS OTHERWISE SPECIFIED, TOLERANCE ON DIMENSIONS IS ± 0.38 mm (0.015 INCH). 3. LEAD MATERIAL: SOLDER PLATED COPPER ALLOY. Figure 2. HCMS-2976 package dimensions 2 1.90 (0.075) SYM. 7.62 (0.300) PIN # FUNCTION 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 NO PIN NO PIN V LED NO PIN NO PIN NO PIN GND LED NO PIN NO PIN V LED NO PIN NO PIN NO PIN DATA IN RS NO PIN CLOCK CE BLANK GND LOGIC SEL V LOGIC NO PIN RESET OSC DATA OUT Device Selection Guide Description 8 Digit 0.15" Character Height HCMS-2919 8 Digit 0.20" Character Height HCMS-2976 Absolute Maximum Ratings Logic Supply Voltage, VLOGIC to GNDLOGIC -0.3V to 7.0V LED Supply Voltage, VLED to GNDLED -0.3V to 5.5V Input Voltage, Any Pin to GND -0.3V to VLOGIC +0.3V Free Air Operating Temperature Range TA -40°C to +85°C Relative Humidity (non-condensing) 85% Storage Temperature, TS -55°C to 100°C Maximum Solder Temperature Solder Dipping Wave Soldering 260°C for 5 sec 250°C for 3 sec ESD Protection @ 1.5 kΩ, 100pF (each pin) Class 1, 0-1999V TOTAL Package Power Dissipation at TA=25°C 2.4 W Notes: For operation in high ambient temperatures, see Appendix A, Thermal Considerations. Recommend Operating Conditions Over Temperature Range (-40°C to +85°C) Parameter Logic Supply Voltage LED Supply Voltage GNDLED to GNDLOGIC [1] [1] Symbol Min. Max. Units VLOGIC 3.0 5.5 V VLED 4.5 5.5 V - -0.3 +0.3 V Notes: For further description, see Appendix B, Electrical Considerations, “VLOGIC and VLED Considerations”. 3 Electrical Characteristics Over Operating Temperature Range (-40°C to +85°C) TA = 25°C, VLOGIC = 5.0V -40°C< TA<85°C 3.0V<VLOGIC<5.5V Typ Max Typ Max Units Test Conditions +15 -5.0 +100 µA VIN = 0 TO VLOGIC Parameter Symbol Input Leakage Current II ILOGIC OPERATING ILOGIC (OPT) 0.8 5 10 mA VIN = VLOGIC ILOGIC SLEEP ILOGIC (SLP) 10 30 50 µA VIN = VLOGIC ILED BLANK ILED (BL) 4.0 8.0 8.0 mA BL = 0 V ILED SLEEP ILED (SLP) 15.0 50 100 µA Peak Pixel Current [2] IPIXEL 20 23 mA VLED = 5.5 V All pixels ON, Average value per pixel HIGH level input voltage Vih V 4.5V<VLOGIC<5.5V [1] [1] 14.0 2.0 3.0V<VLOGIC<4.5V 0.8 VLOGIC LOW level input voltage Vil HIGH level output voltage Voh LOW level output voltage Vol Thermal Resistance RθJ-P 0.8 V 3.0V<VLOGIC<4.5V 0.2 VLOGIC 2.0 4.5V<VLOGIC<5.5V V VLOGIC = 4.5V, Ioh = -40µA 3.0V<VLOGIC<4.5V 0.8 VLOGIC 0.4 V 3.0V<VLOGIC<4.5V 0.2 VLOGIC 70 VLOGIC = 4.5V, Ioh = -40µA °C/W IC junction to pin Notes: 1. In SLEEP mode, the internal oscillator and reference current for LED drivers are off. 2. Average peak pixel current is measured at the maximum drive current set by Control Register 0. Individual pixels may exceed this value. Optical Characteristics at 25 ± 1 °C [1] VLED = 5.5V, 100% Peak Current, 100% Pulse Width Luminous Intensity per LED [2] Character Average (µcd) Display Color Min Typical Peak Wavelength λPeak (nm) Typ. Blue 29 170 428 Dominant Wavelength λd [3] (nm) Typ. 460 Notes: 1. Refers to the initial case temperature of the device immediately prior to measurement. 2. Measured with all LEDs illuminated in a digit. 3. Dominant wavelength, ld, is derived from the CIE Chromaticity diagram and represents the single wavelength which defines the perceived LED color. 4 Electrical Description Pin Function Description RESET (RST) Sets Control Register bits to logic low. The Dot Register contents are unaffected by the Reset pin. (logic low = reset; logic high = normal operation) DATA IN (DIN) Serial Data input for Dot or Control Register data. Data is entered on the rising edge of the Clock input. DATA OUT (DOUT) Serial Data out put for Dot or Control Register data. This pin is used for cascading multiple displays. CLOCK (CLK) Clock input for writing Dot or Control Register data. When Chip Enable is logic low, data is entered on the rising Clock edge. REGISTER SELECT (RS) Selects Dot Register (RS = logic low) or Control Register (RS = logic high) as the destination for serial data entry. The logic level of RS is latched on the falling edge of the Chip Enable input. CHIP ENABLE (CE) This input must be a logic low to write data to the display. When CE returns to logic high and CLK is logic low, data is latched to either the LED output drivers or a Control Register. OSCILLATOR SELECT Selects either an internal or external display oscillator source. (SEL) (logic low = External Display Oscillator; logic high = Internal Display Oscillator). OSCILLATOR (OSC) Output for the Internal Display Oscillator (SEL = logic high) or input for an External Display Oscillator (SEL = logic low). BLANK (BL) Blanks the display when logic high. May be modulated for brightness control. GNDLED Ground for LED drivers GNDLOGIC Ground for logic. VLED Positive supply for LED drivers VLOGIC Positive supply for logic. 5 AC Timing Characteristics Over Temperature Range (-40 to +85°C) Timing Diagram Ref. Number Description Symbol Min 1 Register Select Setup Time to Chip Enable trss 10 10 ns 2 Register Select Hold Time to Chip Enable trsh 10 10 ns 3 Rising Clock Edge to Falling Chip Enable Edge tclkce 20 20 ns 4 Chip Enable Setup Time to Rising Clock Edge tces 35 55 ns 5 Chip Enable Hold Time to Rising Clock Edge tceh 20 20 ns 6 Data Setup Time to Rising Clock Edge tds 10 10 ns 7 Data Hold Time after Rising Clock Edge tdh 10 10 ns tdout 10 4.5V<VLOGIC<5.5V [1] Max 40 VLOGIC = 3V Min 10 Max Units 65 ns 18 30 ns 25 45 ns 8 Rising Clock Edge to DOUT 9 Propagation Delay DIN to DOUT Simultaneous Mode for one IC [1,2] tdoutp 10 CE Falling Edge to DOUT Valid tcedo 11 Clock High Time tclkh 80 100 ns 12 Clock Low Time tclkl 80 100 ns Reset Low Time trstl 50 50 ns Clock Frequency Fcyc Internal Display Oscillator Frequency Finosc 80 210 Internal Refresh Frequency Frf 150 External Display Oscillator Frequency Prescaler = 1 Prescaler = 8 Fexosc 51.2 410 5 4 MHz 80 210 kHz 410 150 410 Hz 1000 8000 51.2 410 1000 8000 kHz kHz Notes: 1. Timing specifications increase 0.3ns per pf of capacitive loading above 15pF. 2. This parameter is valid for Simultaneous Mode data entry of the Control Register. Display Overview Reset The HCMS-29xx blue LED displays are driven by onboard CMOS ICs. The LEDs are configured as 5x7 font characters and are driven in groups of 4 characters per IC. Each IC consists of a 160-bit shift register (the Dot Register), two 7-bit Control Words, and refresh circuitry. The Dot Register contents are mapped on a one-toone basis to the display. Thus, an individual Dot Register bit uniquely controls a single LED. Reset initializes the Control Register (sets all Control Register bits to logic low) and places the display in the sleep mode. The Reset pin shoud be connected to the system power on reset circuit. The Dot Registers are not cleared upon power-on or by Reset. After poweron, the Dot Register contents are random; however, Reset will put the display in sleep mode, thereby blanking the LEDs. The Control Register and the Control Words are cleared to all zeros by Reset. 8-character displays have two ICs that are cascaded. The Data Out line of the first IC is internally connected to the Data In line of the second IC forming a 320-bit Dot Register. The display’s other control and power lines are connected directly to both ICs. 6 To operate the display after being Reset, load the Dot Register with logic lows. Then load Control Word 0 with the desired brightness level and set the sleep mode bit to logic high. Dot Register Table 1. Register Truth Table The Dot Register holds the pattern to be displayed by the LEDs. Data is loaded into the Dot Register according to the procedure shown in Table 1 and Figure 3. Function CLK CE Select Dot Register Not Rising ↓ Load Dot Register DIN = HIGH, LED = "ON" DIN = LOW, LED = "OFF" ↑ L X Copy Data from Dot Register to Dot Latch L H X Select Control Register Not Rising ↓ H ↑ L X L H X First RS is brought low, then CE is brought low. Next, each successive rising CLK edge will shift in the data at the DIN pin. Loading a logic high will turn the corresponding LED on; a logic low turns the LED off. When all 160 bits have been loaded (or 320 bits in an 8-digit display), CE is brought to logic high. When CLK is next brought to logic low, new data is latched into the display dot drivers. Loading data into the Dot Register takes place while the previous data is displayed and eliminates the need to blank the display while loading data. Load Control Register [1,3] Latch Data to Control Word [2] RS Notes: 1. Bit D0 of Control Word 1 must have been preciously set to Low for serial mode or High for simultaneous mode. 2. Selection of Control Word 1 or Control Word 0 is set by D7 of the Control Shift Register. The unselected control word retains its previous value. 3. Control Word data is loaded Most Significant Bit (D7) first. RS TRSS 1 TRSH 2 CE T CLKCE T CES T CLKH 3 4 11 TCLKL 12 T CEH 5 CLK T DS 6 T DH NEW DATA LATCHED HERE [1] 7 D IN T CEDO TDOUT 10 8 D OUT(SERIAL) T DOUTP 9 D OUT (SIMULTANEOUS) LED OUTPUTS, CONTROL REGISTERS PREVIOUS DATA NOTE: 1. DATA IS COPIED TO THE CONTROL REGISTER OR THE DOT LATCH AND LED OUTPUTS WHEN CE IS HIGH AND CLK IS LOW. Figure 3. Write Cycle Timing Diagram 7 NEW DATA Pixel Map DATA FROM PREVIOUS CHARACTER PIXEL DATA TO NEXT CHARACTER In a 4-character display, the 160-bits are arranged as 20 columns by 8 rows. This array can be conceptualized as four 5x8 dot matrix character locations, but only 7 of the 8 rows have LEDs (see Figure 4 & 5). The bottom row (row 0) is not used. Thus, latch location 0 is never displayed. Column 0 controls the left-most column. Data from Dot Latch locations 0-7 determine whether or not pixels in Column 0 are turned-on or turned off. Therefore, the lower left pixel is turned-on when a logic high is stored in Dot Latch location 3. Characters are loaded in serially, with the left-most character being loaded first and the right-most character being loaded last. By loading one character at a time and latching the data before loading the next character, the figures will appear to scroll from right to left. ROW 7 ROW 6 ROW 5 ROW 4 ROW 3 Control Register ROW 2 The Control Register allows software modification of the IC’s operation and consists of two independent 7bit control words. Bit D7 in the shift register selects one of the two 7-bit control words. Control Word 0 performs pulse width modulation brightness control, peak pixel current brightness control, and sleep mode. Control Word 1 sets serial/simultaneous data out mode, and external oscillator prescaler. Each function is independent of others. ROW 1 ROW 0 (NOT USED) Figure 4. Pixel Map DATA OUT RS (LATCHED) H L DATA IN L CLK H H SER/PAR MODE CHIP ENABLE DATA IN REGISTER SELECT CONTROL REGISTER CLR D Q L DI 40 BIT S.R. DO DATA OUT DI 40 BIT S.R. DO DI 40 BIT S.R. DO DOT REGISTERS AND LATCHES RS (LATCHED) V LED + REFRESH CONTROL CURRENT REFERENCE ANODE CURRENT SOURCES RST RESET PWM BRIGHTNESS CONTROL H L DOT REGISTER BIT # 159 CATHODE FIELD DRIVERS ÷8 OSC 3:8 DECODER PRESCALE VALUE ROW 7 0xx xx H xxx xx xxx xx CHAR 1 CHAR 2 COLUMN 0 H CHAR 0 OSC SELECT GND (LED) BLANK Figure 5. Block diagram ROW 1 x x x x x ROW 0 (NO LEDS) L OSCILLATOR L 8 DI 40 BIT S.R. DO COLUMN 19 CHAR 3 Control Register Data Loading Data is loaded into the Control Register, MSB first, according to the procedure shown in Table 1 and Figure 3. First, RS is brought to logic high and then CE is brought to logic low. Next, each successive rising CLK edge will shift in the data on the DIN pin. Finally, when 8 bits have been loaded, the CE line is brought to logic high. When CLK goes to logic low, new data is copied into the selected control word. Loading data into the Control Register takes place while the previous control word configures the displays. Control Word 0 Loading the Control Register with D7- = Logic Low selects Control Word 0 (see Table 2). Bits D0-D3 adjust the display brightness by pulse width modulating the LED on time, while Bits D4 -D5 adjusts the display brightness by changing the peak pixel current. Bit D6 selects normal operation or sleep mode. Sleep mode (Control Word 0, bit D6 = Low) turns off the Internal Display Oscillator and the LED pixel drivers. This mode is used when the IC needs to be powered up, but does not need to be active. Current draw in sleep mode is nearly zero. Data in the Dot Register and Control Words are retained during sleep mode. Control Word 1 Loading the Control Register with D7 = Logic High selects Control Word 1. This control Word performs two functions: serial/simultaneous data out mode and external oscillator prescale select (see Table 2). Table 2. Control Shift Register CONTROL WORD 0 L D6 D5 D4 D3 ↑ Bit D 7 Set Low to Select Control Word 0 D2 D1 D0 On-Time Oscillator Cycles PWM Brightness Control L L L L L L L L H H H H H H H H Peak Current Brightness Control H L L H L L H H SLEEP MODE L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H Typical Peak Pixel Current (mA) 4.0 6.4 9.3 12.8 L H L H L H L H L H L H L H L H 0 1 2 3 4 5 7 9 11 14 18 22 28 36 48 60 Duty Factor (%) Relative Brightness (%) 0 0.2 0.4 0.6 0.8 1.0 1.4 1.8 2.1 2.7 3.5 4.3 5.5 7.0 9.4 11.7 0 1.7 3.3 5.0 6.7 8.3 11.7 15 18 23 30 37 47 60 80 100 Relative Full Scale Current (Relative Brightness, %) 31 50 73 (Default at Power Up) 100 L - DISABLES INTERNAL OSCILLATOR-DISPLAY BLANK H - NORMAL OPERATION CONTROL WORD 1 H ↑ Bit D 7 Set High to Select Control Word 1 9 L L L L Reserved for Future Use (Bits D 2 -D 6 must be set Low) L D1 D0 Serial/Simultaneous Data Out L - D out holds contents of Bit D 7 H - D out is functionally tied to D in External Display Oscillator Prescaler L - Oscillator Freq ÷ 1 H - Oscillator Freq ÷ 8 Serial/Simultaneous Data Output D0 Cascaded ICs Bit D0 of control word 1 is used to switch the mode of D OUT between serial and simultaneous data entry during Control Register writes. The default mode (logic low) is the serial DOUT mode. In serial mode, DOUT is connected to the last bit D 7 of the Control Shift Register. Figure 6 shows how two ICs are connected within an HCMS-29XX display. The first IC controls the four leftmost characters and the second IC controls the four right-most characters. The Dot Registers are connected in series to form a 320-bit dot shift register. The location of pixel 0 has not changed. However, Dot Shift Register bit 0 of IC2 becomes bit 160 of the 320-bit dot shift register. Storing logic high to bit D 0 changes D OUT to simultaneous mode, which affects the Control Register only. In simultaneous mode, DOUT is logically connected to DIN. This arrangement allows multiple ICs to have their Control Registers written to simultaneously. For example, for n ICs in the serial mode, n * 8 clock pulses to load the same data in all Control Registers. The propagation delay from the first IC to the last is n * tDOUTP. External Oscillator Prescaler Bit D1 Bit D1 of Control Word 1 is used to scale the frequency of an external Display Oscillator. When this bit is logic low, the external Display Oscillator directly sets the internal display clock rate. When this bit is a logic high, the external oscillator is divided by 8. This scaled frequency then sets the internal display clock rate. It takes 512 cycles of the display clock (or 8 x 512 = 4096 cycles of an external clock with the divide by 8 prescaler) to completely refresh the display once. Using the prescaler bit allows the designer to use a higher external oscillator frequency without extra circuitry. This bit has no affect on the internal Display Oscillator Frequency. Bits D2-D6 These bits must always be programmed to logic low. 10 The Control Registers of the two ICs are independent of each other. This means that to adjust the display brightness the same control word must be entered into both ICs, unless the Control Registers are set to simultaneous mode. Longer character string systems can be built by cascading multiple displays together. This is accomplished by creating a five line bus. This bus consists of CE, RS, BL, Reset, and CLK. The display pins are connected to the corresponding bus line. Thus, all CE pins are connected to the CE bus line. Similarly, bus lines for RS, BL, Reset, and CLK are created. Then DIN is connected to the right-most display. DOUT from this display is connected to the next display. The left-most display receives its DIN from the DOUT of the display to its right. DOUT from the left-most display is not used. Each display may be set to use its internal oscillator, or the displays may be synchronized by setting up one display as the master and the others as slaves. The slaves are set to receive their oscillator input from the master’s oscillator output. CE RS BL RESET CLK CE CE RS RS BL BL RESET CLK DOUT DOUT IC1 BITS 0-159 CHARACTERS 0-3 RESET CLK D IN DOUT SEL SEL OSC OSC OSC SEL DIN Figure 6. Cascaded ICs. 11 IC2 BITS 160-319 CHARACTERS 4-7 D IN Appendix A. Thermal Considerations A typical value for RθJA is 100°C/W. This value is typical for a display mounted in a socket and covered with a plastic filter. The socket is soldered to a .062 in. thick PCB with .020 inch wide, one ounce copper traces. PD can be calculated as Equation 2 below. Figure 7 shows how to derate the power of one IC versus ambient temperature. Operation at high ambient temperatures may require the power per IC to be reduced. The power consumption can be reduced by changing either the N, I PIXEL, Osc cyc or V LED. Changing VLOGIC has very little impact on the power consumption. Appendix B. Electrical Considerations Current Calculations The peak and average display current requirements have a significant impact on power supply selection. The maximum peak current is calculated with Equation 3 below. The average current required by the display can be calculated with Equation 4 below. The power supply has to be able to supply I PEAK transients and supply ILED (AVG) continuously. The range on VLED allows noise on this supply without significantly changing the display brightness. RΘ J-A = 100 C/W 1.1 P D MAX MAXIMUM POWER DISSIPATION PER IC - W The display IC has a maximum junction temperature of 150°C. The IC junction temperature can be calculated with Equation 1 below. 1.3 1.2 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 25 30 35 40 45 50 55 60 65 70 75 80 85 90 TA - AMBIENT TEMPERATURE - C Figure 7. Maximum power dissipation per IC versus ambient temperature. Equation 1: T J MAX = T A + P Where: T J MAX TA RθJA PD D * Rθ JA = maximum IC junction temperature = ambient temperature surrounding the display = thermal resistance from the IC junction to ambient = power dissipated by the IC Equation 2: P D = (N * I PIXEL * Duty Factor * V LED ) + I LOGIC * VLOGIC Where: P D = total power dissipation N = number of pixels on (maximum 4 char * 5 * 7 = 140) I PIXEL = peak pixel current. Duty Factor = 1/8 * Osccyc/64 Osc cyc = number of ON oscillator cycles per row I LOGIC = IC logic current VLOGIC = logic supply voltage Equation 3: I PEAK = M * 20 * I PIXEL Where: I PEAK M 20 I PIXEL = maximum instantaneous peak current for the display = number of ICs in the system = maximum number of LEDs on per IC = peak current for one LED Equation 4: I LED (AVG) = N * I PIXEL* 1/8 * (oscillator cycles)/64 (see Variable Definitions above) 12 VLOGIC and VLED Considerations The display uses two independent electrical systems. One system is used to power the display’s logic and the other to power the display’s LEDs. These two systems keep the logic supply clean. Separate electrical systems allow the voltage applied to VLED and VLOGIC to be varied independently. Thus, VLED can vary from 0 to 5.5V without affecting either the Dot or the Control Registers. VLED can be varied between 4.0 to 5.5 V without any noticeable variation in light output. However, operating VLED below 4.5 V may cause objectionable mismatch between the pixels and is not recommended. Dimming the display by pulse width modulating VLED is also not recommended. VLOGIC can vary from 3.0 to 5.5 V without affecting either the displayed message or the display intensity. However, operation below 4.5 V will change the timing and logic levels and operation below 3 V may cause the Dot and Control Registers to be altered The logic ground is internally connected to the LED ground by a substrate diode. This diode becomes forward biased and conducts when the logic ground is 0.4 V greater than the LED ground. The LED ground and the logic ground should be connected to a common ground, which can withstand the current introduced by the switching LED drivers. When separate ground connections are used, the LED ground can vary from -0.3 V to +0.3 V with respect to the logic ground. Voltages below -0.3 V can cause all the dots to be ON. Voltage above +0.3 V can cause dimming and dot mismatch. Using a decoupling capacitor between the power supply and ground will help prevent any supply noise in the frequency range greater than that of the functioning display from interfering with the display’s internal circuitry. The value of the capacitor depends on the series resistance from the ground back to the power supply and the range of frequencies that need to be suppressed. It is also advantageous to use the largest ground plane possible. Electrostatic Discharge The inputs to the ICs are protected against static discharge and input current latchup. However, for best results, standard CMOS handling precautions should be used. Before use, the HCMS-29XX should be stored 13 in antistatic tubes or in conductive material. During assembly, a grounded conductive work area should be used and assembly personnel should wear conductive wrist straps. Lab coats made of synthetic material should be avoided since they are prone to static buildup. Input current latchup is caused when the CMOS inputs are subjected to either a voltage below ground (VIN < ground) or to a voltage higher than VLOGIC (VIN > VLOGIC) and when a high current is forced into the input. To prevent input current latchup and ESD damage, unused inputs should be connected to either ground or VLOGIC. Voltages should not be applied to the inputs until VLOGIC has been applied to the display. Appendix C. Oscillator The oscillator provides the internal refresh circuitry with a signal that is used to synchronize the columns and rows. This ensures that the right data is in the dot drivers for that row. This signal can be supplied from either an external source or the internal source. A display refresh rate of 100 Hz or faster ensures flickerfree operation. Thus for an external oscillator the frequency should be greater than or equal to 512 x 100 Hz = 51.2 kHz. Operation above 1 MHz without the prescaler or 8 MHz with the prescaler may cause noticeable pixel to pixel mismatch. Appendix D. Refresh Circuitry This display driver consists of 20 one-of-eight column decoders and 20 constant current sources, 1 one-ofeight row decoder and eight row sinks, a pulse width modulation control block, a peak current control block, and the circuit to refresh the LEDs. The refresh counters and oscillator are used to synchronize the columns and rows. The 160 bits are organized as 20 columns by 8 rows. The IC illuminates the display by sequentially turning ON each of the 8 row-drivers. To refresh the display once takes 512 oscillator cycles. Because there are eight row drivers, each row driver is selected for 64 (512/8) oscillator cycles. Four cycles are used to briefly blank the display before the following row is switched on. Thus, each row is ON for 60 oscillator cycles out of a possible 64. This corresponds to the maximum LED on time. Appendix E. Display Brightness Relative Luminous Intensity (normalized to 1 at 25˚C) Two ways have been shown to control the brightness of this LED display: setting the peak current and setting the duty factor. Both values are set in Control Word 0. To compute the resulting display brightness when both PWM and peak current control are used, simply multiply the two relative brightness factors. For example, if Control Register 0 holds the word 1001101, the peak current is 73% of full scale (BIT D5 = L, BIT D4 = L) and the PWM is set to 60% duty factor (BIT D3 = H, BIT D2 = H, BIT D1 = L, BIT D0 = H). The resulting brightness is 44% (.73 x .60 = .44) of full scale. The temperature of the display will also affect the LED brightness as shown in Figure 8. The temperature of the display will also affect the LED brightness as shown in Figure 8. 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 -40 -20 0 Application Note 1027: Soldering LED Components Application Note 1015: Contrast Enhancement Techniques for LED Displays www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries. Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved. AV01-0115EN - May 16, 2006 14 40 Figure 8. Relative luminous intensity versus ambient temperature. Appendix F. Reference Material For product information and a complete list of distributors, please go to our web site: 20 Ambient Temperature ( o C) 60 80