HD74HC292/HD74HC294 Programmable Frequency Divider/Digital Timer REJ03D0608–0200 (Previous ADE-205-486) Rev.2.00 Jan 31, 2006 Description This device divides the incoming clock frequency by a number (a power of 2) that is preset by the Programming inputs. It has two Clock inputs, either of which may be used as a clock inhibit. The device also has an active-low Reset, which initializes the internal flip-flop states. Test Point outputs (TP1, TP2, TP3) are provided with HD74HC292 to facilitate incoming inspections. Test Point output is provided with HD74HC294 to facilitate incoming inspections. Features • • • • • • High Speed Operation: tpd (Clock to Q) = 16 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information Part Name HD74HC292P Package Code (Previous Code) Package Type PRDP0016AE-B (DP-16FV) DILP-16 pin Package Abbreviation P — PRSP0016DH-B FP (FP-16DAV) Note: Please consult the sales office for the above package availability. HD74HC294FPEL Taping Abbreviation (Quantity) SOP-16 pin (JEITA) EL (2,000 pcs/reel) Function Table H : L : CLR L H H H H high level low level Rev.2.00 Jan 31, 2006 page 1 of 9 CLK1 X L H X CLK2 X L X H Q Output Mode Cleared to L Count Count Inhibit Inhibit HD74HC292 / HD74HC294 HD74HC292 Programming Frequency Division Inputs Q Out TP1 TP2 TP3 E D C B A Binary Decimal Binary Decimal Binary Decimal Binary Decimal L L L L L Inhibit Inhibit Inhibit Inhibit Inhibit Inhibit Inhibit Inhibit L L L L H Inhibit Inhibit Inhibit Inhibit Inhibit Inhibit Inhibit Inhibit L L L H L 2 2 L L L H H 2 3 4 8 2 9 512 2 9 512 2 17 131,072 2 17 131,072 2 24 16,777,216 2 24 16,777,216 16,777,216 L L H L L 2 4 16 2 9 512 2 17 131,072 2 24 L L H L H 2 5 32 2 9 512 2 17 131,072 2 24 16,777,216 L L H H L 2 6 64 2 9 512 2 17 131,072 2 24 16,777,216 24 16,777,216 L L H H H 2 7 128 2 9 512 2 17 131,072 2 L H L L L 2 8 256 2 9 512 2 17 131,072 2 2 4 L H L L H 2 9 512 2 9 512 2 17 131,072 2 2 4 512 2 17 131,072 2 4 16 512 2 17 131,072 2 4 16 131,072 2 6 64 131,072 2 6 64 256 L H L H L 2 10 L H L H H 2 11 1,024 2 9 2,048 2 9 L H H L L 2 12 4,096 2 9 512 2 17 L H H L H 2 13 8,192 2 9 512 2 17 L H H H L 2 14 16,384 2 9 512 Disabled LOW 2 8 L H H H H 2 15 32,768 2 9 512 Disabled LOW 2 65,536 2 9 512 131,072 2 9 512 8 256 2 10 1,024 2 10 1,024 32 2 12 4,096 32 2 12 4,096 16,384 H L L L L 2 16 H L L L H 2 17 262,144 2 9 524,288 2 9 512 2 7 128 2 14 512 2 7 128 2 14 16,384 9 512 2 16 65,536 65,536 H L L H L 2 18 H L L H H 2 19 H L H L L 2 20 1,048,576 2 9 H L H L H 2 21 2,097,152 2 9 H L H H L 2 22 4,194,304 8,388,608 2 3 8 2 3 8 512 2 5 512 2 5 Disabled LOW 2 H L H H H 2 23 512 2 16 H H L L L 2 24 16,777,216 2 3 8 2 11 2,048 2 18 262,144 H H L L H 2 25 33,554,432 2 3 8 2 11 2,048 2 18 262,144 67,108,864 2 5 32 2 13 8,192 2 20 1,048,576 134,217,728 2 5 32 2 13 8,192 2 20 1,048,576 4,194,304 H H L H L 2 26 H H L H H 2 27 Disabled LOW 9 2 H H H L L 2 28 268,435,456 2 7 128 2 15 32,768 2 22 H H H L H 2 29 536,870,912 2 7 128 2 15 32,768 2 22 4,194,304 H H H H L 2 30 1,073,741,824 2 9 512 2 17 131,072 2 24 16,777,216 H H H H H 2 31 2,147,483,648 2 9 512 2 17 131,072 2 24 16,777,216 Rev.2.00 Jan 31, 2006 page 2 of 9 HD74HC292 / HD74HC294 HD74HC294 Programming Inputs D L L L L L L L L H H H H H H H H C L L L L H H H H L L L L H H H H B L L H H L L H H L L H H L L H H A L H L H L H L H L H L H L H L H Frequency Division Q Output TP Output Binary Decimal Binary Decimal Inhibit Inhibit Inhibit Inhibit Inhibit Inhibit Inhibit Inhibit 2 9 2 4 2 512 23 8 29 512 4 9 2 16 2 512 25 32 29 512 26 64 29 512 7 2 128 Disabled LOW 28 256 22 4 29 512 23 8 10 4 2 1,024 2 16 211 2,048 25 32 12 6 2 4,096 2 64 213 8,192 27 128 214 16,384 28 256 15 9 2 32,768 2 512 Pin Arrangement • HD74HC292 B 1 16 VCC E 2 15 C TP1 3 14 D CLK1 4 13 TP3 CLK2 5 12 NC TP2 6 11 CLR Q 7 10 A GND 8 9 NC (Top view) Rev.2.00 Jan 31, 2006 page 3 of 9 HD74HC292 / HD74HC294 • HD74HC294 B 1 16 VCC A 2 15 C TP 3 14 D CLK1 4 13 NC CLK2 5 12 NC NC 6 11 CLR Q 7 10 NC GND 8 9 NC (Top view) Logic Diagram • HD74HC292 CLR CLK1 R CLK2 R CK R R MC R R TP1 CK 0 1 14 13 D D D R R MC R CK D D D R TP2 D 12 11 10 9 A B 2 C D E 4 R R MC D 8 6 R TP3 D R R Q D 8 7 6 5 R R MC CK D 4 3 2 Rev.2.00 Jan 31, 2006 page 4 of 9 R CK D D HD74HC292 / HD74HC294 • HD74HC294 CLR CLK1 CLK2 0 1 14 13 12 11 10 TP 9 A B C D 1 8 2 4 8 7 6 5 Q 4 3 2 Absolute Maximum Ratings Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC VIN, VOUT IIK, IOK IO ICC or IGND PT Tstg Ratings –0.5 to 7.0 –0.5 to VCC +0.5 ±20 ±25 ±50 500 –65 to +150 Unit V V mA mA mA mW °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time*1 Symbol VCC VIN, VOUT Ta tr, tf Ratings 2 to 6 0 to VCC –40 to 85 0 to 1000 0 to 500 0 to 400 Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Rev.2.00 Jan 31, 2006 page 5 of 9 Unit V V °C ns Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V HD74HC292 / HD74HC294 Electrical Characteristics Item Symbol VCC (V) Input voltage VIH VIL 2.0 4.5 6.0 2.0 4.5 6.0 Min 1.5 3.15 4.2 — — — Output voltage VOH 2.0 4.5 6.0 4.5 6.0 2.0 4.5 6.0 4.5 6.0 6.0 6.0 1.9 4.4 5.9 4.18 5.68 — — — — — — — VOL Input current Iin Quiescent supply current ICC Ta = 25°C Typ Max — — — — — — — 0.5 — 1.35 — 1.8 2.0 4.5 6.0 — — 0.0 0.0 0.0 — — — — — — — — — 0.1 0.1 0.1 0.26 0.26 ±0.1 4.0 Ta = –40 to+85°C Unit Min Max 1.5 — V 3.15 — 4.2 — V — 0.5 — 1.35 — 1.8 1.9 4.4 5.9 4.13 5.63 — — — — — — — — — — — — 0.1 0.1 0.1 0.33 0.33 ±1.0 40 V V Test Conditions Vin = VIH or VIL IOH = –20 µA Vin = VIH or VIL IOH = –4 mA IOH = –5.2 mA IOL = 20 µA IOL = 4 mA IOL = 5.2 mA µA Vin = VCC or GND µA Vin = VCC or GND, Iout = 0 µA Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Symbol VCC (V) Maximum clock frequency fmax Propagation delay time tPLH Removal time trem Pulse width tw Min Ta = 25°C Typ Max Ta = –40 to +85°C Unit Min Max 2.0 4.5 6.0 2.0 4.5 — — — — — — — — — 16 5 27 31 600 120 — — — — — 4 21 24 750 150 6.0 2.0 4.5 6.0 2.0 4.5 6.0 — 100 20 17 80 16 14 — — –4 — — 14 – 100 — — — — — — — 125 25 21 100 20 17 125 — — — — — — MHz ns ns ns Output rise/fall time tTLH tTHL 2.0 4.5 6.0 — — — — 5 — 75 15 13 — — — 95 19 16 ns Input capacitance Cin — — 5 10 — 10 pF Rev.2.00 Jan 31, 2006 page 6 of 9 Test Conditions Clock to output HD74HC292 / HD74HC294 Test Circuit • HD74HC292 VCC VCC Output A Pulse Generator Zout = 50 Ω Input Pulse Generator Zout = 50 Ω See Function Table Input TP1 B C Output CL = 50 pF D TP3 E CK1 Output CL = 50 pF CK2 Q CLR CL = 50 pF Note : 1. CL includes probe and jig capacitance. • HD74HC294 VCC VCC Input Pulse Generator Zout = 50 Ω See Function Table Input Pulse Generator Zout = 50 Ω Output A B TP C CL = 50 pF D Output CK1 CK2 Q CLR Note : 1. CL includes probe and jig capacitance. Rev.2.00 Jan 31, 2006 page 7 of 9 CL = 50 pF HD74HC292 / HD74HC294 Waveforms 6ns 6ns 90% CLR VCC 90% 50% 50% 10% 10% trem 6ns 90% 90% CLK 50% 50% Q or TP VCC 90% 50% 50% 10% 10% 10% tPLH tPHL tPLH 90% 50% 50% 10% tTHL Note : 1. Input pulse : PRR≤1MHz, duty cycle 50%, tr ≤ 6ns, tf ≤ 6ns Rev.2.00 Jan 31, 2006 page 8 of 9 GND tPHL VOH 90% 90% 10% tTLH GND 6ns 6ns 50% 50% 10% 10% tTLH tTHL VOL HD74HC292 / HD74HC294 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B MASS[Typ.] 1.05g Previous Code DP-16FV D 9 E 16 1 8 b3 0.89 Z A1 A Reference Symbol L e Nom θ c e1 D 19.2 E 6.3 JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV 7.4 A1 0.51 b p 0.40 b 3 0.48 0.56 1.30 c 0.19 θ 0° e 2.29 0.25 0.31 2.54 2.79 15° 1.12 L 2.54 MASS[Typ.] 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 20.32 5.06 Z ( Ni/Pd/Au plating ) Max 7.62 1 A bp e Dimension in Millimeters Min 9 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 bp Nom D 10.06 E 5.50 Max 10.5 A2 8 e Dimension in Millimeters Min x A1 M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 A L1 2.20 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 e 1.27 x 0.12 y 0.15 0.80 Z L L Rev.2.00 Jan 31, 2006 page 9 of 9 8° 0.50 1 0.70 1.15 0.90 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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