HYNIX HM17CM256

HM17CM256
Preliminary Specification(0.3)
128XRGBX82 OUTPUT LCD DRIVER IC
with built-in RAM
■ INSTRUCTION
HM17CM256 is a dot-Matrix LCD drive IC with 82
commons (80 + 2 icons) and 384 segments (128 X
RGB) drive ports for 256 colors driving.
This IC stores the serial or parallel BIT data
transferred by the microcomputer on the built-in
RAM (81,920 bits for graphic + 2048 bits for icons)
and generates the signals to drive LCD panel.
Color graphic display is achieved by selecting 8
gray (256 color) levels out of 32 gray palettes
independently.
This IC is suitable for battery-operated system,
hand-carrying information equipment by ensuring
low power consumption, low power supply (1.7V ~ )
and a wide range of operating voltage.
And 164 x 128 display (maximum) is possible with
master and slave application.
EXTERNAL SHAPE
HM17CM256
■ FEATURES
256 color bitmap LCD driver
LCD drive outputs
128×RGB segments, 80 commons for graphic and 2 commons for icons
Display RAM capacity 81,920bits (for graphic usage)
2,048bits (for icon usage)
Gradation display
8 gradations can be selected from 32 gradations by PWM control
Black/White display
82 × (128 × 3) bits display is possible
8 bit BUS interface
directly connectable with 68 / 80 series CPU
RAM data length
8 BIT / 16 BIT selectable
Serial interface available
Programmable duty / bias ratio with command
Various instruction set
display data read/write, display ON/OFF, positive/negative display, page address set
display start line address set, partial display, bias select,
column address set, all display ON/OFF, boosting selection, n line inversion mode
read modified write, power save …
Built-in voltage booster (programmable) : 7 × boosting
Built-in voltage regulator
Controllable contrast with built-in electric volume (128 steps)
Low current consumption
Logic supply
1.7V ~ 3.3V
LCD drive supply
5.0V ~ 18.0V
C-MOS silicon process
Package
bumped chip / bare chip
01/02/09
-1-
HM17CM256
PAD LAYOUT
SEGA125
SEGB125
SEGC125
SEGA126
SEGB126
SEGC126
SEGA127
SEGB127
SEGC127
DMY5(L)
DMY5(R)
DMY6(L)
DMY6(R)
SEGSA2
SEGSC3
COM40
COM66
DMY7(L)
DMY7(R)
1
CLK
FR
FLM
CL
VSS(R)
VSS(C)
VSS(L)
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4/SPOL
D3/SMODE
D2/EXCS
D1/SDA
D0/SCL
VDD(R)
VDD(C)
VDD(L)
RD
WR
VSSA(R)
VSSA(C)
VSSA(L)
SEL68
P/S
VDDA
M/S
VSS(R)
VSS(C)
VSS(L)
RS
CSB
RES
VDD(R)
VDD(C)
VDD(L)
TEST
VSSA(R)
VSSA(C)
VSSA(L)
COMI1
COM79
COM67
DMY0(R)
DMY0(L)
note 1) The (L) (R) (C) mark after port name is internally shorted.
note 2) DMYport is opened electrically.
chip center
chip size
:
:
chip thickness
bump size
bump pitch
bump height
bump material
:
:
:
:
:
X= 0µ
µm, Y= 0µ
µm
with scribe lane : 19.84mm x 2.48mm ,
main chip : 19.74mm x 2.38mm
µm ± 25µ
µm
625µ
µm x 32µ
µm, 100µ
µm x 80µ
µm
100µ
µm(Min)
50µ
µm
18 ± 3µ
Au
align mark appearance and size
a
d
µm
a : 30µ
µm
b : 6µ
µm
c : 120µ
µm
d : 27µ
d
b
a
coordinates of align marks
µm, Y= -1052µ
µm)
(X= - 9732µ
µm, Y= -1052µ
µm)
(X= 9732µ
b
c
-2-
c
HM17CM256
DMY4(L)
DMY4(R)
SEGA0
SEGB0
SEGC0
SEGA1
SEGB1
SEGC1
SEGA2
SEGB2
SEGC2
DMY3(R)
DMY3(L)
SEGSC1
Y
SEGSA0
COMI0
COM0
X
COM25
DMY2(R)
DMY2(L)
µm
unit
DMY1(R)
DMY1(L)
COM26
COM39
VOUT(R)
VOUT(L)
VLCD(R)
VLCD(L)
C6-(R)
C6-(L)
C6+(R)
C6+(L)
C5-(R)
C5-(L)
C5+(R)
C5+(L)
C4-(R)
C4-(L)
C4+(R)
C4+(L)
C3-(R)
C3-(L)
C3+(R)
C3+(L)
C2-(R)
C2-(L)
C2+(R)
C2+(L)
C1-(R)
C1-(L)
C1+(R)
C1+(L)
VSSH(R)
VSSH(C)
VSSH(L)
VEE(R)
VEE(C)
VEE(L)
VREF
VBA(R)
VBA(L)
VREG(R)
VREG(L)
V4(R)
V4(L)
V3(R)
V3(L)
V2(R)
V2(L)
V1(R)
V1(L)
VLCD(R)
VLCD(L)
VSSH(R)
VSSH(C)
VSSH(L)
OSC2
OSC1
All sorts of PAD open
1. open size (e, f)=(66, 86)
17~118
2. open size (e, f)=(18, 86)
1~16, 119~596
Original point mark of left picture is presented
at the table of pad coordinates.
-3-
HM17CM256
■ PAD coordinates 1
PAD
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
-4-
Pin name
X(µm)
Y(µm)
DMY0(L)
DMY0(R)
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
VSSA(L)
VSSA(C)
VSSA(R)
TEST
VDD(L)
VDD(C)
VDD(R)
RES
CS
RS
VSS(L)
VSS(C)
VSS(R)
M/S
VDDA
P/S
SEL68
VSSA(L)
VSSA(C)
VSSA(R)
WR
RD
VDD(L)
VDD(C)
VDD(R)
D0/SCL
D1/SDA
D2/EXCS
D3/SMODE
D4/SPOL
D5
D6
D7
D8
D9
-9625
-9575
-9525
-9475
-9425
-9375
-9325
-9275
-9225
-9175
-9125
-9075
-9025
-8975
-8925
-8875
-8670
-8500
-8330
-8171
-7990
-7820
-7650
-7480
-7310
-7140
-6970
-6800
-6630
-6448
-6290
-6120
-5950
-5780
-5610
-5440
-5270
-5111
-4930
-4760
-4590
-4420
-4250
-3995
-3740
-3570
-3400
-3230
-3060
-2890
-2720
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
-1068
PAD
No.
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
chip size 19840µm x 2480µm ( chip center : 0µm x 0µm )
Pin name X (µm) Y (µm) PAD Pin name X (µm) Y (µm)
No.
D10
-2550 -1068 103
C4+(L)
6120 -1068
D11
-2380 -1068 104
C4+(R)
6290 -1068
D12
-2210 -1068 105
C4-(L)
6460 -1068
D13
-2040 -1068 106
C4-(R)
6630 -1068
D14
-1870 -1068 107
C5+(L)
6800 -1068
D15
-1700 -1068 108
C5+(R)
6970 -1068
VSS(L)
-1472 -1068 109
C5-(L)
7140 -1068
VSS(C)
-1340 -1068 110
C5-(R)
7310 -1068
VSS(R)
-1190 -1068 111
C6+(L)
7480 -1068
CL
-1020 -1068 112
C6+(R)
7650 -1068
FLM
-850 -1068 113
C6-(L)
7820 -1068
FR
-680 -1068 114
C6-(R)
7990 -1068
CLK
-510 -1068 115
VLCD(L)
8160 -1068
OSC1
-340 -1068 116
VLCD(R)
8330 -1068
OSC2
-107 -1068 117
VOUT(L)
8500 -1068
VSSH(L)
74 -1068 118
VOUT(R)
8670 -1068
VSSH(C)
196 -1068 119
COM39
8875 -1068
VSSH(R)
318 -1068 120
COM38
8925 -1068
VLCD(L)
510 -1068 121
COM37
8975 -1068
VLCD(R)
680 -1068 122
COM36
9025 -1068
V1(L)
850 -1068 123
COM35
9075 -1068
V1(R)
1020 -1068 124
COM34
9125 -1068
V2(L)
1190 -1068 125
COM33
9175 -1068
V2(R)
1360 -1068 126
COM32
9225 -1068
V3(L)
1530 -1068 127
COM31
9275 -1068
V3(R)
1700 -1068 128
COM30
9325 -1068
V4(L)
1870 -1068 129
COM29
9375 -1068
V4(R)
2040 -1068 130
COM28
9425 -1068
VREG(L)
2210 -1068 131
COM27
9475 -1068
VREG(R)
2380 -1068 132
COM26
9525 -1068
VBA(L)
2550 -1068 133
DMY1(L)
9575 -1068
VBA(R)
2693 -1068 134 DMY1(R)
9625 -1068
VREF
2879 -1068 135
DMY2(L)
9726
-900
VEE(L)
3060 -1068 136 DMY2(R)
9726
-850
VEE(C)
3230 -1068 137
COM25
9726
-800
VEE(R)
3400 -1068 138
COM24
9726
-750
VSSH(L)
3570 -1068 139
COM23
9726
-700
VSSH(C)
3740 -1068 140
COM22
9726
-650
VSSH(R)
3910 -1068 141
COM21
9726
-600
C1+(L)
4102 -1068 142
COM20
9726
-550
C1+(R)
4250 -1068 143
COM19
9726
-500
C1-(L)
4420 -1068 144
COM18
9726
-450
C1-(R)
4590 -1068 145
COM17
9726
-400
C2+(L)
4760 -1068 146
COM16
9726
-350
C2+(R)
4930 -1068 147
COM15
9726
-300
C2-(L)
5100 -1068 148
COM14
9726
-250
C2-(R)
5270 -1068 149
COM13
9726
-200
C3+(L)
5440 -1068 150
COM12
9726
-150
C3+(R)
5610 -1068 151
COM11
9726
-100
C3-(L)
5780 -1068 152
COM10
9726
-50
C3-(R)
5950 -1068 153
COM9
9726
0
HM17CM256
■ PAD coordiantes 2
PAD
No.
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
Pin name
X(µm)
Y(µm)
COM8
COM7
COM6
COM5
COM4
COM3
COM2
COM1
COM0
COMI0
SEGSA0
SEGSB0
SEGSC0
SEGSA1
SEGSB1
SEGSC1
DMY3(L)
DMY3(R)
DMY4(L)
DMY4(R)
SEGA0
SEGB0
SEGC0
SEGA1
SEGB1
SEGC1
SEGA2
SEGB2
SEGC2
SEGA3
SEGB3
SEGC3
SEGA4
SEGB4
SEGC4
SEGA5
SEGB5
SEGC5
SEGA6
SEGB6
SEGC6
SEGA7
SEGB7
SEGC7
SEGA8
SEGB8
SEGC8
SEGA9
SEGB9
SEGC9
SEGA10
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9726
9675
9625
9575
9525
9475
9425
9375
9325
9275
9225
9175
9125
9075
9025
8975
8925
8875
8825
8775
8725
8675
8625
8575
8525
8475
8425
8375
8325
8275
8225
8175
8125
8075
50
100
150
200
250
300
350
400
450
500
550
600
650
700
750
800
850
900
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
PAD
No.
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
chip size 19840µm x 2480µm ( chip center : 0µm x 0µm )
Pin name X (µm) Y (µm) PAD Pin name X (µm) Y (µm)
No.
SEGB10
8025
1068 256
SEGB27
5475
1068
SEGC10
7975
1068 257
SEGC27
5425
1068
SEGA11
7925
1068 258
SEGA28
5375
1068
SEGB11
7875
1068 259
SEGB28
5325
1068
SEGC11
7825
1068 260
SEGC28
5275
1068
SEGA12
7775
1068 261
SEGA29
5225
1068
SEGB12
7725
1068 262
SEGB29
5175
1068
SEGC12
7675
1068 263
SEGC29
5125
1068
SEGA13
7625
1068 264
SEGA30
5075
1068
SEGB13
7575
1068 265
SEGB30
5025
1068
SEGC13
7525
1068 266
SEGC30
4975
1068
SEGA14
7475
1068 267
SEGA31
4925
1068
SEGB14
7425
1068 268
SEGB31
4875
1068
SEGC14
7375
1068 269
SEGC31
4825
1068
SEGA15
7325
1068 270
SEGA32
4775
1068
SEGB15
7275
1068 271
SEGB32
4725
1068
SEGC15
7225
1068 272
SEGC32
4675
1068
SEGA16
7175
1068 273
SEGA33
4625
1068
SEGB16
7125
1068 274
SEGB33
4575
1068
SEGC16
7075
1068 275
SEGC33
4525
1068
SEGA17
7025
1068 276
SEGA34
4475
1068
SEGB17
6975
1068 277
SEGB34
4425
1068
SEGC17
6925
1068 278
SEGC34
4375
1068
SEGA18
6875
1068 279
SEGA35
4325
1068
SEGB18
6825
1068 280
SEGB35
4275
1068
SEGC18
6775
1068 281
SEGC35
4225
1068
SEGA19
6725
1068 282
SEGA36
4175
1068
SEGB19
6675
1068 283
SEGB36
4125
1068
SEGC19
6625
1068 284
SEGC36
4075
1068
SEGA20
6575
1068 285
SEGA37
4025
1068
SEGB20
6525
1068 286
SEGB37
3975
1068
SEGC20
6475
1068 287
SEGC37
3925
1068
SEGA21
6425
1068 288
SEGA38
3875
1068
SEGB21
6375
1068 289
SEGB38
3825
1068
SEGC21
6325
1068 290
SEGC38
3775
1068
SEGA22
6275
1068 291
SEGA39
3725
1068
SEGB22
6225
1068 292
SEGB39
3675
1068
SEGC22
6175
1068 293
SEGC39
3625
1068
SEGA23
6125
1068 294
SEGA40
3575
1068
SEGB23
6075
1068 295
SEGB40
3525
1068
SEGC23
6025
1068 296
SEGC40
3475
1068
SEGA24
5975
1068 297
SEGA41
3425
1068
SEGB24
5925
1068 298
SEGB41
3375
1068
SEGC24
5875
1068 299
SEGC41
3325
1068
SEGA25
5825
1068 300
SEGA42
3275
1068
SEGB25
5775
1068 301
SEGB42
3225
1068
SEGC25
5725
1068 302
SEGC42
3175
1068
SEGA26
5675
1068 303
SEGA43
3125
1068
SEGB26
5625
1068 304
SEGB43
3075
1068
SEGC26
5575
1068 305
SEGC43
3025
1068
SEGA27
5525
1068 306
SEGA44
2975
1068
-5-
HM17CM256
PAD coordinates 3
PAD
No.
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
-6-
Pin name
X(µm)
Y(µm)
SEGB44
SEGC44
SEGA45
SEGB45
SEGC45
SEGA46
SEGB46
SEGC46
SEGA47
SEGB47
SEGC47
SEGA48
SEGB48
SEGC 48
SEGA49
SEGB49
SEGC49
SEGA50
SEGB50
SEGC50
SEGA51
SEGB51
SEGC51
SEGA52
SEGB52
SEGC52
SEGA53
SEGB53
SEGC53
SEGA54
SEGB54
SEGC54
SEGA55
SEGB55
SEGC55
SEGA56
SEGB56
SEGC56
SEGA57
SEGB57
SEGC57
SEGA58
SEGB58
SEGC58
SEGA59
SEGB59
SEGC59
SEGA60
SEGB60
SEGC60
SEGA61
2925
2875
2825
2775
2725
2675
2625
2575
2525
2475
2425
2375
2325
2275
2225
2175
2125
2075
2025
1975
1925
1875
1825
1775
1725
1675
1625
1575
1525
1475
1425
1375
1325
1275
1225
1175
1125
1075
1025
975
925
875
825
775
725
675
625
575
525
475
425
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
PAD
No.
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
chip size 19840µm x 2480µm (chip center : 0µm x 0µm )
Pin name X (µm) Y (µm) PAD Pin name X (µm) Y (µm)
No.
SEGB61
375
1068 409
SEGB78
-2175
1068
SEGC61
325
1068 410
SEGC78
-2225
1068
SEGA62
275
1068 411
SEGA79
-2275
1068
SEGB62
225
1068 412
SEGB79
-2325
1068
SEGC62
175
1068 413
SEGC79
-2375
1068
SEGA63
125
1068 414
SEGA80
-2425
1068
SEGB63
75
1068 415
SEGB80
-2475
1068
SEGC63
25
1068 416
SEGC80
-2525
1068
SEGA64
-25
1068 417
SEGA81
-2575
1068
SEGB64
-75
1068 418
SEGB81
-2625
1068
SEGC64
-125
1068 419
SEGC81
-2675
1068
SEGA65
-175
1068 420
SEGA82
-2725
1068
SEGB65
-225
1068 421
SEGB82
-2775
1068
SEGC65
-275
1068 422
SEGC82
-2825
1068
SEGA66
-325
1068 423
SEGA83
-2875
1068
SEGB66
-375
1068 424
SEGB83
-2925
1068
SEGC66
-425
1068 425
SEGC83
-2975
1068
SEGA67
-475
1068 426
SEGA84
-3025
1068
SEGB67
-525
1068 427
SEGB84
-3075
1068
SEGC67
-575
1068 428
SEGC84
-3125
1068
SEGA68
-625
1068 429
SEGA85
-3175
1068
SEGB68
-675
1068 430
SEGB85
-3225
1068
SEGC68
-725
1068 431
SEGC85
-3275
1068
SEGA69
-775
1068 432
SEGA86
-3325
1068
SEGB69
-825
1068 433
SEGB86
-3375
1068
SEGC69
-875
1068 434
SEGC86
-3425
1068
SEGA70
-925
1068 435
SEGA87
-3475
1068
SEGB70
-975
1068 436
SEGB87
-3525
1068
SEGC70
-1025
1068 437
SEGC87
-3575
1068
SEGA71
-1075
1068 438
SEGA88
-3625
1068
SEGB71
-1125
1068 439
SEGB88
-3675
1068
SEGC71
-1175
1068 440
SEGC88
-3725
1068
SEGA72
-1225
1068 441
SEGA89
-3775
1068
SEGB72
-1275
1068 442
SEGB89
-3825
1068
SEGC72
-1325
1068 443
SEGC89
-3875
1068
SEGA73
-1375
1068 444
SEGA90
-3925
1068
SEGB73
-1425
1068 445
SEGB90
-3975
1068
SEGC73
-1475
1068 446
SEGC90
-4025
1068
SEGA74
-1525
1068 447
SEGA91
-4075
1068
SEGB74
-1575
1068 448
SEGB91
-4125
1068
SEGC74
-1625
1068 449
SEGC91
-4175
1068
SEGA75
-1675
1068 450
SEGA92
-4225
1068
SEGB75
-1725
1068 451
SEGB92
-4275
1068
SEGC75
-1775
1068 452
SEGC92
-4325
1068
SEGA76
-1825
1068 453
SEGA93
-4375
1068
SEGB76
-1875
1068 454
SEGB93
-4425
1068
SEGC76
-1925
1068 455
SEGC93
-4475
1068
SEGA77
-1975
1068 456
SEGA94
-4525
1068
SEGB77
-2025
1068 457
SEGB94
-4575
1068
SEGC77
-2075
1068 458
SEGC94
-4625
1068
SEGA78
-2125
1068 459
SEGA95
-4675
1068
HM17CM256
■ PAD coordinates 4
PAD
No.
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
Pin name
X(µm)
Y(µm)
SEGB95
SEGC95
SEGA96
SEGB96
SEGC96
SEGA97
SEGB97
SEGC97
SEGA98
SEGB98
SEGC98
SEGA99
SEGB99
SEGC99
SEGA100
SEGB100
SEGC100
SEGA101
SEGB101
SEGC101
SEGA102
SEGB102
SEGC102
SEGA103
SEGB103
SEGC103
SEGA104
SEGB104
SEGC104
SEGA105
SEGB105
SEGC105
SEGA106
SEGB106
SEGC106
SEGA107
SEGB107
SEGC107
SEGA108
SEGB108
SEGC108
SEGA109
SEGB109
SEGC109
SEGA110
SEGB110
SEGC110
SEGA111
SEGB111
SEGC111
SEGA112
-4725
-4775
-4825
-4875
-4925
-4975
-5025
-5075
-5125
-5175
-5225
-5275
-5325
-5375
-5425
-5475
-5525
-5575
-5625
-5675
-5725
-5775
-5825
-5875
-5925
-5975
-6025
-6075
-6125
-6175
-6225
-6275
-6325
-6375
-6425
-6475
-6525
-6575
-6625
-6675
-6725
-6775
-6825
-6875
-6925
-6975
-7025
-7075
-7125
-7175
-7225
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
1068
PAD
No.
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
Pin name
SEGB112
SEGC112
SEGA113
SEGB113
SEGC113
SEGA114
SEGB114
SEGC114
SEGA115
SEGB115
SEGC115
SEGA116
SEGB116
SEGC116
SEGA117
SEGB117
SEGC117
SEGA118
SEGB118
SEGC118
SEGA119
SEGB119
SEGC119
SEGA120
SEGB120
SEGC120
SEGA121
SEGB121
SEGC121
SEGA122
SEGB122
SEGC122
SEGA123
SEGB123
SEGC123
SEGA124
SEGB124
SEGC124
SEGA125
SEGB125
SEGC125
SEGA126
SEGB126
SEGC126
SEGA127
SEGB127
SEGC127
DMY5(L)
DMY5(R)
DMY6(L)
DMY6(R)
chip size 19840µm x 2480µm (chip center : 0µm x 0µm )
X (µm) Y (µm) PAD Pin name X (µm) Y (µm)
No.
-7275
1068 562
SEGSA2
-9726
800
-7325
1068 563
SEGSB2
-9726
750
-7375
1068 564
SEGSC2
-9726
700
-7425
1068 565
SEGSA3
-9726
650
-7475
1068 566
SEGSB3
-9726
600
-7525
1068 567
SEGSC3
-9726
550
-7575
1068 568
COM40
-9726
500
-7625
1068 569
COM41
-9726
450
-7675
1068 570
COM42
-9726
400
-7725
1068 571
COM43
-9726
350
-7775
1068 572
COM44
-9726
300
-7825
1068 573
COM45
-9726
250
-7875
1068 574
COM46
-9726
200
-7925
1068 575
COM47
-9726
150
-7975
1068 576
COM48
-9726
100
-8025
1068 577
COM49
-9726
50
-8075
1068 578
COM50
-9726
0
-8125
1068 579
COM51
-9726
-50
-8175
1068 580
COM52
-9726
-100
-8225
1068 581
COM53
-9726
-150
-8275
1068 582
COM54
-9726
-200
-8325
1068 583
COM55
-9726
-250
-8375
1068 584
COM56
-9726
-300
-8425
1068 585
COM57
-9726
-350
-8475
1068 586
COM58
-9726
-400
-8525
1068 587
COM59
-9726
-450
-8575
1068 588
COM60
-9726
-500
-8625
1068 589
COM61
-9726
-550
-8675
1068 590
COM62
-9726
-600
-8725
1068 591
COM63
-9726
-650
-8775
1068 592
COM64
-9726
-700
-8825
1068 593
COM65
-9726
-750
-8875
1068 594
COM66
-9726
-800
-8925
1068 595
DMY7(L)
-9726
-850
-8975
1068 596
DMY7(R)
-9726
-900
-9025
1068
-9075
1068
-9125
1068
-9175
1068
-9225
1068
-9275
1068
-9325
1068
-9375
1068
-9425
1068
-9475
1068
-9525
1068
-9575
1068
-9625
1068
-9675
1068
-9726
900
-9726
850
-7-
HM17CM256
COM79
COMI1
COMI0
COM0
SEGSA2
SEGSB2
SEGSC2
SEGSA3
SEGSB3
SEGSC3
VDDA
SEGA127
SEGB127
SEGC127
VSSA
SEGA0
SEGB0
SEGC0
SEGSA0
SEGSB0
SEGSC0
SEGSA1
SEGSB1
SEGSC1
BLOCK DIAGRAM
VSSH
VSS
VDD
VLCD, V1 ~V4
D
D
5
C1+
C1C2+
C2C3+
C3C4+
C4C5+
C5C6+
C6VOUT
VEE
VREF
VBA
VREG
R
)
*E
!"
,
-
.
/
0
1
2
,
1
3
1
4
1
5
+
+
+
(F
&
6
,
,
4
1
5
7
()
D
()
!"
()
()
*
)
)
)
)
"
"
6
8
9
:
;
:
<
=
>
=
>
7
;
?
-
3
9
&
"
(
"
'
'
'
'
#$%
'
*
*
*
*
!"
!&
*
*
"
"
)
*
-
@
A
B
,
1
3
1
4
1
5
*
"
"
)
'
#$
%
"
6
/
C
4
1
5
7
#$
G
'
&
!&
'
#$
"
)
"
"
*
"
6
8
9
:
;
9
=
>
=
>
7
;
?
-
3
9
)
G
&
"
*
'
'
'
'
'
D15
D14
D13
R
FR
D12
D11
FLM
CL
D10
$
D9
%
CLK
D8
S
"
OSC2
T
T
D7
'
OSC1
D6
D5
D4/SPOL
D3/SMODE
D2/EXCS
INTERNAL BUS
D1/SDA
D0/SCL
H
CS
-8-
RS
M/S
I
J
RD
K
L
M
N
WR
O
P
Q
H
N
P/S
SEL68
RES
TEST
HM17CM256
■ POWER CIRCUIT BLOCK DIAGRAM
W
R
VLCD
V
W
V
D
VBA
V1
W
VREG
V
VREF
U
V2
W
V
V
W
V
E.V.R.
V3
W
V
W
V
V4
W
V
D
C1+
C1C2+
C2C3+
C3C4+
C4C5+
C5C6+
C6VEE
D
D
VOUT
-9-
HM17CM256
■ PIN DESCRIPTION 1
No.
21,22,23,
39,40,41
27,28,29,
58,59,60
67,68,69,
88,89,90
31
NAME
VDD
I/O
supply
VSS
supply
VSSH
supply
VDDA
supply
17,18,19,
34,35,36
VSSA
supply
70,71,115,116
72,73
74,75
76,77
78,79
VLCD
V1
V2
V3
V4
supply/O
91,92
93,94
95,96
97,98
99,100
101,102
103,104
105,106
107,108
109,110
111,112
113,114
82,83
84
85,86,87
C1+
C1C2+
C2C3+
C3C4+
C4C5+
C5C6+
C6VBA
VREF
VEE
O
This pin is internally connected to VDD pin.
This pin is used when the voltage of each input pin is fixed to
VDD level.
caution) Do not use to main power pin.
This pin is internally connected to VSS pin.
This pin is used when the voltage of each input pin is fixed to
VSS level.
caution) Do not use to main power pin.
LCD driver supply voltage
• LCD driver power supply port when external power supply
is used. When external power is used, voltages should
have following relations.
VSS<V4<V3<V2<V1<VLCD
• VLCD, V1~V4 voltages are generated by voltage booster at
master mode operation under power circuit ON.
• When internal power supply is used, capacitors must be
connected between VLCD, V1~V4 and VSS.
Capacitor connection pin for voltage converter
O
Capacitor connection pin for voltage converter
O
Capacitor connection pin for voltage converter
O
Capacitor connection pin for voltage converter
O
Capacitor connection pin for voltage converter
O
Capacitor connection pin for voltage converter
117,118
80,81
24
VOUT
VREG
- 10 -
RES
O
I
supply
supply/O
O
I
FUNCTION
Power pin for logic
GND pin for logic
High voltage GND pin
Reference voltage output pin for voltage regulating.
Reference voltage input pin for voltage regulating.
Voltage supply pin for boosted voltage generation.
VDD level at normal status.
Internal DC/DC converter output pin.
Voltage regulator output pin.
Reset pin
Reset when RES= “L”
HM17CM256
■ PIN DESCRIPTION 2
No.
42
NAME
D0/SCL
I/O
I/O
43
D1/SDA
I/O
44
D2/EXCS
I/O
45
D3/SMODE
I/O
46
D4/SPOL
I/O
47,48,49
D5,D6,D7
I/O
50,51,52,53
54,55,56,57
D8,D9,D10,D11,
D12,D13,D14,D15
I/O
25
26
CS
RS
I
I
FUNCTION
When parallel interface is selected (P/S=”H”), data line is
connected to MPU data bus with 8bit bi-directional bus
• When serial interface is selected (P/S=”L”),
D0 and D1(SCL, SDA) are used as serial interface pins
and various sets are taken by serial interface use mode of
D2, D3, D4.
SDA : serial data input pin
SCL : data transfer clock
EXCS : extension chip selection I/O pin
SMODE : serial transfer mode setting input pin
SPOL : RS polarity selection pin when 3 line serial interface is
selected.
SDA data is shifted at the rising edge of SCL
Internal serial/parallel conversion into 8-bit data occurs at the
th
rising edge of 8 clock of SCL.
Set to “L” after data transfer or during non-access time
•
Connect to data bus to MPU with 8bit bi-directional bus.
Used as MSB 8bit data bus in the 16bit data RAM transfer
mode
Set to “L” or “H” when not used.
Chip selection pin.
Data in-out is possible when CS = “L”.
Input data selection pin.
Distinguish bus data from CPU whether instruction or display
data.
RS
class
38
37
RD (E)
WR (R/W)
I
I
H
instruction
L
display data
<80 series CPU interface (P/S=”H”,SEL68=”L”)>
RD signal connection port of 80 series CPU.
Data bus goes to output state at RD = “L”.
<68 series CPU interface (P/S=”H”,SEL68=”H”)>
Enable signal connection port of 68 series CPU.
Active status when this signal is at “H”.
<80 series CPU interface (P/S=”H”,SEL68=”L”)>
WR signal connection port of 80 series CPU.
Active at “L” and data bus signal is taken at the rising edge
of WR.
<68 series CPU interface (P/S=”H”,SEL68=”H”)>
Read write control signal , R/W connection port of 68series MPU.
R/W
status
H
read
L
write
- 11 -
HM17CM256
■ PIN DESCRIPTION 3
No.
33
NAME
SEL68
I/O
I
32
P/S
I
FUNCTION
CPU interface selection port
SEL68
H
L
status
68 series
80 series
Serial / parallel interface selection port
P/S
chip
select
data/
command
data
read/
write
serial clock
H
CS
RS
D0~D7
RD, WR
-
L
CS
RS
SDA(D1)
write only
SCL (D0)
X
P/S = “L” :serial interface selection ,D15~D5 goes to Hi-Z
- 12 -
state. Fix RD, WR to “H” or “L”.
Test port.
Fix to ”L”.
Latching signal pin of display data.
Display line counter is counted up at the rising edge and LCD
driving signal is generated at the falling edge
M/S
status
CL
H
master
output
L
slave
input
20
TEST
I
61
CL
I/O
62
FLM
I/O
LCD synchronous signal (first line marker) I/O pin.
Display start address is loaded in the display line counter at
FLM = “H”.
M/S
status
FLM
H
master
output
L
slave
input
63
FR
I/O
Alternated display signal of LCD driver output I/O pin.
M/S
status
FR
H
master
output
L
slave
input
30
M/S
I
Master / slave mode selection pin
M/S
mode
oscillator
Power supply
H
master
enable
enable
L
slave
disable
disable
Fix to “H” or “L” according to operating mode.
HM17CM256
PIN DESCRIPTION 4
No.
174~557
NAME
SEGA0~SEGA127,
SEGB0~SEGB127,
SEGC0~SEGC127
I/O
O
FUNCTION
Segment drive port
Segment output from display RAM data
mode
Non-lighted
lighted
Normal
0
1
Reverse
1
0
The output level is selected among VLCD, V2, V3, VSS by the
combination of FR signal and RAM data
(B/W mode)
FR signal
display RAM data
164~169,
562~567
162~137,
132~119,
568~594,
3~15
SEGSA0~SEGSA3,
SEGSB0~SEGSB3,
SEGSC0~SEGSC3
COM0~COM79
O
O
Normal mode
V2
VLCD
V3
VSS
Reverse mode
VLCD
V2
VSS
V3
Dummy segment driver output
Located at both side of segment drivers, used for edge
display.
Common driver output
The output level is selected among VLCD, V1, V4 and VSS by
the combination of FR and scan data.
data
H
L
H
L
163
16
65,
66
COMI0
COMI1
OSC1,
OSC2
O
O
I
O
64
CLK
I/O
FR
H
H
L
L
Output level
VSS
V1
VLCD
V4
Common drive output for icon display
Common drive output for icon display
External reference clock input pin
Open when using internal oscillator clock or used as slave
device.
In this case, OSC1 goes to VSS level.
Connect external oscillating source to OSC1 port or connect
resistor between OSC1 and OSC2 when using external
oscillator.
Input / output pin for display timing clock
Output clock from master device is applied to slave chip
through CLK pin when used as master / slave mode.
M/S
H
L
mode
master
slave
CLK
output
input*
*input from master chip’s CLK output
(port No. 1,2,133,134,135,136,170,171,172,173,558,559,560,561,595,596 is dummy port.)
- 13 -
HM17CM256
■ FUNCTION DESCRIPTION
(1) CPU interface
(1-1) Selection of interface type
HM17CM256 receives data through 8 bit parallel I/O(D0~D7) 16 bit parallel I/O(D0~D15) or
divided into serial data input (SDA, SCL). Parallel or serial selection is decided by P/S pin setting.
Parallel or serial selection is possible as following table.
Reading out from internal register or RAM is not possible at serial interface mode.
Y
TABLE
P/S
Type
CS
RS
RD
WR
SEL68
H
Parallel input
CS
RS
RD
WR
SEL68
L
Serial input
-
-
RS
CS
caution 1) “-” mark item : Fix to ”H” or ”L”
SDA
SCL
data
D0~D7 (D0~D15)
SDA
SCL
-
(1-2) Parallel input
In the parallel interface mode selected by P/S port, parallel data is transferred from the
8bit/16bit MPU through data bus. SEL68 port setting makes 80-series or 68-series interface
selection
TABLE
SEL68
CPU type
CS
RS
RD
WR
data
H
68 series CPU
CS
RS
E
R/W
D0~D7 (D0~D15)
L
80 series CPU
CS
RS
RD
WR
D0~D7 (D0~D15)
(1-3) Data identification
Combinations of RS, RD, and WR signals identify contents of 8bit data bus.
TABLE
68 series
RS
1
1
0
0
R/W
1
0
1
0
80 series
FUNCTION
RD
0
1
0
1
WR
1
0
1
0
Read out from internal register
Write in to internal register
Read display data
Write display data
(1-4) Serial interface
2 types of serial interface (3 line type mode, 4 line type mode) are available by selecting
SMODE pin.
TABEL
SMODE
H
L
- 14 -
Serial interface mode
3 line type
4 line type
HM17CM256
(1-5) 4 line type serial interface
4 line serial interface by SDA and SCL is possible at chip selection state (CS=”L”)
When chip is not selected, internal shift register and counter are reset to initial value.
Serial input data from SDA are latched at the rising edge of serial clock (SCL) in the sequence
of D7,
, D1, D0 and converted into 8-bit parallel data at the rising edge of 8th serial clock.
Serial data (SDA) are identified to display data or command by RS input.
Z
TABLE
RS
H
L
Data contents
command
Display data
Make serial clock (SCL) “L” at the non-access period and after 8bit data transfer.
SDA and SCL signals are sensitive to external noise. To prevent mal-function, chip selector
state should be released (CS = “H”) after 8bit data transfer as shown in the following figure.
CS
VALID
RS
SDA
D7
D6
D5
D4
D3
D2
D1
D0
1
2
3
4
5
6
7
8
SCL
4 line serial interface
(1-6) 3 line type serial interface
3-line serial interface by SDA and SCL is possible at chip selection state (CS=”L”)
When chip is not selected, internal shift register and counter are reset to initial value.
Input data from SDA are latched at the rising edge of serial clock (SCL) in the sequence of RS,
D7 , ,D1, D0, and converted to 8bit parallel data and handled at the rising edge of 9th serial
clock.
Serial data (SDA) are identified to display data or command by RS bit data at the rising of first
serial clock (SCL) and state of command data bit polarity shift pin (SPOL).
[
TABLE
RS
L
H
SPOL=L
Data identify
Display data
command
RS
L
H
SPOL=H
Data identify
command
Display data
- 15 -
HM17CM256
Serial clock (SCL) should go to “L” at the non-access period and after 9bit data transfer.
SDA and SCL signals are sensitive to external noise. To prevent miss operation chip
selector state should be released (CS = “H”) after 9bit data transfer as shown in the following
figure.
CS
SDA
RS
D7
D6
D5
D4
1
2
3
4
5
D3
D2
D1
D0
SCL
6
7
8
9
3line serial interface
(1-7) One systematization of CS when serial interface is selected
In the multi-chip operation (master/slave) mode with serial I/F connection, one CS signal
controls two chips to reduce control signal.
Connect extended chip selection port (EXCS) of master chip to EXCS port ( input at slave
device and output at master device mode ) of slave chip.
When EXCS is “L”, master chip cannot accept command except for EXCS control; at this
point, only slave chip can be controlled.
Slave device control is possible when CS = “L” period within EXCS = “L” state.
RS SCL SDA CS
CS
SDA
SCL
RS
M/S
P/S
SMODE
SPOL
EXCS
CS
SDA
SCL
RS
M/S
P/S
SMODE
SPOL
EXCS
- 16 -
EXCS: expand CS signal ( input port )
Master device : output port
Slave device : input port
(MASTER)
P/S: parallel . serial selection port
(input port)
P/S=0: serial I/F
P/S=1: parallel I/F
M/S: master . slave selection port
(input port)
M/S=0: slave operation
M/S=1: master operation
(SLAVE)
SMODE: serial I/Fmode selection port
(input port)
SMODE=0: 4 line serial I/F
SMODE=1: 3 line serial I/F
SPOL:command data bit polarity selection port
(input port)
At 3 line serial I/F mode
Access display RAM at SPOL=0:RS=0
Access display RAM at SPOL=1:RS=1
HM17CM256
(2) DDRAM and internal register access
DDRAM and internal register are accessed by data bus D0~D7(D0~D15), chip select pin (CS),
DDRAM / register select pin (RS), read / write control pin (RD) or WR pin.
When CS=“H”, it is in non-selective state and DDRAM and internal register access is impossible.
During access, Set CS=“L”.
Access selection to DDRAM or internal register is controlled by RS input.
TABLE
RS
L
H
Data contents
Display RAM data
Internal command register
Write process starts after address setting and then the data on the 8bit data bus D0~D7 or 16bit
data bus D0~D15 will be written in by CPU. The data is written at the rising edge of WR (80 series) or
falling edge of E (68 series).
Internally, bus holder data is processed to data bus and data are written to bus holder from CPU
until next cycle.
After address setting, data of assigned address are read at the 1st and 3rd clock, which means it
needs dummy read at the 2nd clock.
There are rules at reading data out of display RAM, after address setting, the data of assigned
address is shown directly after the end of the read command, so pay attention that assigned data is
available at 2nd timing step.
In other words, 1 cycle dummy read is needed after address setting and write cycle.
DATA WRITE IN OPERATION
D0~D15
n
n+1
n+2
n+3
n+4
WR
\]^
n
BUS HOLDER
_`
n+1
n+2
n+3
n+4
b
]a
WR
DATA READ OUT OPERATION
WR
D0~D7(D0~D15)
n
address set
n
dummy
read
n
n+1
data read
n address
data read
n+1 address
n+2
data read
n+2 address
RD
caution) When 16 bit mode, do write in and read out by 16 bit not only RAM access but also command
setting.
- 17 -
HM17CM256
(3) Read out of internal register
Read out is possible not only from DDRAM, but also from the internal register.
read (0~FH) are allocated in each register.
Read out is executed after writing read-out register address to internal register.
Addresses for
WR
D0~D7
M
m
N
n
Address set
for
register read
Internal
register read
Address set
for
register read
Internal
register read
RD
Internal register read out sequence
RE register set:100
Internal register read address set
set RE of register to be read out
Internal register read
When register is read out, upper 4 bit data are “1111”.
Non-used bits of active registers are “0”.
When non-used registers are read out, upper 4 bits are “1111” and lower 4 bits are “0000”.
(4) 16 bit data access to DDRAM
It is possible to write in DDRAM by 16-bits access with the data of 16 bits data bus D0~D15.
16 bits data access mode is possible by setting the value of WLS register to “1”.
TABEL
WLS
L
H
Acess mode
8 bit
16 bit
Each command should be set to 8-bits(D0~D7) as well as to 16-bit access mode.
16-bit access is available at display RAM access.
(5) Display start line register
When displaying the DDRAM data, it is the contents of Y address register that is corresponding to
display start line.
The data of Y address is displayed on the display start line depending on the value of the shift
command register and the display start line register.
The data of this register are preset to the display line counter per FLM signal transition.
Line counter is counted up in synchronization with CL input and generates line address that read
out 384bit data from DDRAM to LCD driver circuit.
- 18 -
HM17CM256
(6) DDRAM addressing
This IC includes display memory Bit mapped that is composed of 1024 bit of X direction
(8bit×128) and 82bit of Y direction.
In gray mode, neighboring 3-bit data or 2-bit data are displayed by segment driver with 8 grays or
4 grays, respectively.
3 outputs of segment driver compose 1 pixel of RGB and 128×82 pixels are displayed with 256
color (8gray×8gray×4gray).
Address area of X direction is varied according to accessed data length. The area of X direction
is 0H~7FH at 8bit access mode and 0H~3FH at 16bit access mode.
•
8BIT access
X-address
0H
0H
8bit
1H
8bit
7EH
8bit
7FH
8bit
51H
8bit
8bit
8bit
8bit
Y-address
•
16 BIT access
X-address
0H
0H
16bit
3FH
16bit
51H
16bit
16bit
Y-address
In the Black & white mode, the MSBs of 3 bit and 2 bit corresponding with RGB are used to
display data. And so, 128x82 dot gray display or 384 x 82 B/W mode display is possible.
Display RAM is accessed with X address and Y address from CPU by 8 bit or 16 bit unit.
X address and Y address can be increased automatically by setting status of control register.
The address is increased per every read and write of display RAM by CPU. ( Please see detail
description at command function.)
X direction is selected by X address and Y direction is selected by Y address. Please do not set
the address on non-effective area and it is forbidden to set address on outside area in each case.
384bit display data of Y direction are read out to display latch at rising edge of CL signal per 1 line
cycle and this data comes out from display latch at falling edge of CL signal.
Display start line address register is preset to line counter at “H” state of FLM signal which changes
per one frame cycle and the address is counted up with synchronized CL input.
Display line address counter is synchronized by timing signals of LCD driver, and it operates
independently with X, Y address counters.
- 19 -
HM17CM256
(7) Window address assign of display RAM
This IC can be accessed to display RAM by window area designation in addition to access to
display RAM designated by X and Y address.
Through address space of all display address, specific area of RAM can be accessed by
designated two points.
The start point of two point addresses is assigned by normal X address and Y address register and
the end point of them is done by X end address and Y end address register value.
Designated
inner addresses depend on WLS bit.
Read modified write action can be taken by AIM=“1”.
In case of using window area accessing mode, you must set start point X address, Y address in
sequence and end point X address, Y address in sequence after executing Win command (WIN=“1”,
auto increase mode AXI=“1”, AYI=“1”) and then access to Display RAM.
And set start point and end point not to be designated to access the outside of available address
area.
Address set value should be taken to set AX ≤ EX ( end point of X address ) and AY≤EY
( end point of Y address ).
X direction
Y direction
(X, Y)
address designation
Window display area
end address designation
(X, Y)
All display RAM area
(8) display RAM data and LCD
Display RAM data related with one dot of LCD is dependent on REV register.
reverse display by REV register are set up as follows.
TABLE
REV
(9)
Display
L
normal
H
reverse
Normal display and
RAM data
0
1
0
1
Segment display output order/reverse set up
The order of display outputs, SEGA0, SEGB0, SEGC0 to SEGA127, SEGB127, and can be reversed
by reversing access to display RAM from MPU by using REF register, lessen the limitation in placing
IC when assembling an LCD panel module.
- 20 -
palette
C
palette
B
palette
A
SEGB1
SEGC1
d
d
d
d
palette
A
d
SEGC127
e
D2
D1
D0
e
e
D3
X address / bit / segment assign
X=01H
X=7EH
X=7EH
X=01H
e
SEGB127
d
palette
B
d
SEGC127
SEGB127
palette
C
palette
B
palette
A
d
SEGA127
d
palette
C
D4
D5
D6
D7
d
SEGA127
e
D7
D0
D1
D2
D3
e
e
D7
D6
D5
D4
X address / bit / segment assign
X=01H
X=7EH
X=7EH
X=01H
e
palette
C
SEGC127
SEGB127
palette
C
SEGA127
palette
A
palette
B
palette
A
SEGC126
d
SEGC126
d
palette
A
d
SEGC126
d
SEGB126
d
D2
D1
D0
e
SEGB126
e
e
palette
B
e
palette
C
palette
A
SEGC126
SEGA127
SEGC127
palette
C
palette
B
palette
B
SEGB126
SEGB127
palette
A
SEGA126
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
d
palette
B
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D13
D14
D15
d
palette
C
palette
C
SEGC1
D12
d
SEGA126
palette
B
SEGB1
d
SEGB126
D0
D1
D2
D3
D4
D5
D6
SEGC1
D2
D1
D0
D3
palette
A
SEGA1
d
palette
A
palette
A
SEGB1
palette
C
SEGC0
d
SEGA126
palette
B
SEGA1
palette
B
SEGB0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
c
D4
D3
palette
C
SEGC1
D5
D6
D7
D4
palette
C
SEGC0
D10
D9
D8
D7
D6
D5
D4
palette
A
SEGA0
c
c
palette
B
D7
D6
D5
palette
B
SEGB1
palette
A
SEGB0
D12
D11
X=00H
X=3FH
c
palette
C
palette
A
SEGA1
palette
B
D15
D14
D13
X=00H
X=3FH
SEGA126
X=00H
X=7FH
D2
D1
D0
palette
C
SEGC0
X=00H
X=7FH
D3
1
0
SEGA1
SWAP
0
1
SEGC0
REF
palette
A
0
1
SEGB0
0
1
palette
B
SWAP
SEGB0
REF
palette
C
1
0
SEGA0
SWAP
0
1
palette
B
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
REF
palette
A
0
1
SEGA0
0
1
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
SWAP
palette
C
REF
SEGA0
HM17CM256
(10) Relation between Display RAM and address
• RAM address and bitmap
COLOR / 16 BIT MODE
X address / bit / segment assign
X=3FH
X=00H
X address / bit / segment assign
X=3FH
X=00H
d
COLOR / 8 BIT MODE
X=7FH
X=00H
d
X=7FH
X=00H
d
- 21 -
- 22 f
f
f
g
g
g
g
X address / bit / segment assign
X=01H
X=7EH
X=7EH
X=01H
f
f
f
f
g
g
g
g
SEGC127
f
SEGC127
X address / bit / segment assign
X=01H
X=7EH
X=7EH
X=01H
SEGB127
g
SEGB127
g
SEGA127
g
SEGA127
g
SEGC127
SEGB127
SEGA127
SEGC126
D0
f
SEGC126
f
f
SEGC126
f
SEGC127
SEGB127
SEGA127
SEGC126
SEGB126
D15
D13
D14
D11
D12
D6
D7
D8
D9
D10
D3
D4
D5
D2
D1
g
SEGB126
D0
g
SEGA126
g
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
g
SEGA126
D15
SEGC1
f
SEGB126
D15
D0
SEGB1
D9
D10
D11
D12
D13
D14
SEGA1
f
f
SEGA126
SEGC1
D2
D1
D3
SEGC0
D8
D5
D6
D7
f
SEGB126
SEGC1
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D5
D6
D7
SEGB1
X=00H
X=3FH
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
X=00H
X=7FH
D4
D7
D6
D5
D4
D4
D3
D1
D2
D0
SEGB0
SEGA0
X=00H
X=3FH
SEGA126
1
0
SEGC1
SWAP
0
1
D2
D1
D0
REF
X=00H
X=7FH
SEGB1
0
1
D3
0
1
SEGB1
SWAP
SEGA1
REF
SEGA1
1
0
SEGC0
SWAP
0
1
SEGC0
D15
D14
D13
D12
D11
D10
D9
D8
REF
SEGB0
SEGA0
0
1
SEGA1
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
0
1
SEGB0
SEGA0
SWAP
SEGC0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
REF
SEGB0
SEGA0
HM17CM256
BLACK & WHITE / 16 BIT MODE
X address / bit / segment assign
X=3FH
X=00H
X address / bit / segment assign
X=3FH
X=00H
BLACK & WHITE / 8 BIT MODE
X=7FH
X=00H
X=7FH
X=00H
HM17CM256
•
WRITE IN / READ IN BITMAP ( 16 BIT MODE )
REF=0, SWAP=0
WRITE IN DATA
SEGMENT DATA
READ IN DATA
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
REF=0, SWAP=1
WRITE IN DATA
SEGMENT DATA
READ IN DATA
D0
D1
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
REF=1, SWAP=0
WRITE IN DATA
SEGMENT DATA
READ IN DATA
D0
D1
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
REF=1, SWAP=1
WRITE IN DATA
SEGMENT DATA
READ IN DATA
D0
D1
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
- 23 -
HM17CM256
•
READ OUT AFTER WROTE IN DATA ( 16 BIT MODE )
REF=0, SWAP=0
WRITE IN DATA
D15
1
1
1
0
0
1
0
0
1
1
1
1
0
0
1
D0
0
(E4F2H)
READ IN DATA
D15
1
1
1
0
0
1
0
0
1
1
1
1
0
0
1
D0
0
(E4F2H)
REF=0, SWAP=1
WRITE IN DATA
D15
1
1
1
0
0
1
0
0
1
1
1
1
0
0
1
D0
0
(E4F2H)
READ IN DATA
D15
0
1
0
0
1
1
1
1
0
0
1
0
0
1
1
D0
1
(4F27H)
REF=1, SWAP=0
WRITE IN DATA
D15
1
1
1
0
0
1
0
0
1
1
1
1
0
0
1
D0
0
(E4F2H)
READ IN DATA
D15
1
1
1
0
0
1
0
0
1
1
1
1
0
0
1
D0
0
(E4F2H)
REF=1, SWAP=1
WRITE IN DATA
D15
1
1
1
0
0
1
0
0
1
1
1
1
0
0
1
D0
0
(E4F2H)
READ IN DATA
D15
0
1
0
0
1
1
1
1
0
0
1
0
0
1
1
D0
1
(4F27H)
- 24 -
HM17CM256
•
WRITE IN / READ IN BITMAP ( 8 BIT MODE )
REF=0, SWAP=0
WRITE IN DATA
SEGMENT DATA
READ IN DATA
D0
D1
D2
D3
D4
D5
D6
D7
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
D0
D1
D2
D3
D4
D5
D6
D7
D2
D3
D4
D5
D6
D7
REF=0, SWAP=1
WRITE IN DATA
SEGMENT DATA
READ IN DATA
D0
D1
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
D0
D1
D2
D3
D4
D5
D6
D7
D2
D3
D4
D5
D6
D7
REF=1, SWAP=0
WRITE IN DATA
SEGMENT DATA
READ IN DATA
D0
D1
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
D0
D1
D2
D3
D4
D5
D6
D7
D2
D3
D4
D5
D6
D7
REF=1, SWAP=1
WRITE IN DATA
SEGMENT DATA
READ IN DATA
D0
D1
SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7
D0
D1
D2
D3
D4
D5
D6
D7
- 25 -
HM17CM256
•
READ OUT AFTER WROTE IN DATA ( 8 BIT MODE )
REF=0, SWAP=0
WRITE IN DATA
D15
1
1
1
0
0
1
0
D0
0
(E4H)
READ IN DATA
D15
1
1
1
0
0
1
0
D0
0
(E4H)
REF=0, SWAP=1
WRITE IN DATA
D15
1
1
1
0
0
1
0
D0
0
(E4H)
READ IN DATA
D15
0
0
1
0
0
1
1
D0
1
(27H)
REF=1, SWAP=0
WRITE IN DATA
D15
1
1
1
0
0
1
0
D0
0
(E4H)
READ IN DATA
D15
1
1
1
0
0
1
0
D0
0
(E4H)
REF=1, SWAP=1
WRITE IN DATA
D15
1
1
1
0
0
1
0
D0
0
(E4H)
READ IN DATA
D15
0
0
1
0
0
1
1
D0
1
(27H)
- 26 -
Palette
C
Palette
B
Palette
A
Palette
C
Palette
B
Palette
A
Palette
C
Palette
B
Palette
A
SEGSA1
SEGSB1
SEGSC1
SEGSA2
SEGSB2
SEGSC2
SEGSA3
SEGSB3
SEGSC3
X=00H
X=03H
X address / bit segment assign
X=01H
X=02H
X=02H
X=01H
Palette
C
Palette
A
SEGSC2
SEGSA3
Palette
C
Palette
B
SEGSB2
X address / bit segment assign
X=01H
X=02H
X=02H
X=01H
SEGSC3
Palette
A
SEGSA2
Palette
B
Palette
A
Palette
C
SEGSB2
SEGSC2
SEGSA3
SEGSC3
SEGSB3
Palette
C
SEGSA2
Palette
A
Palette
B
Palette
A
SEGSC1
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X=00H
X=01H
Palette
B
Palette
C
SEGSC1
SEGSA1
SEGSB1
Palette
C
SEGSC0
Palette
B
Palette
A
SEGSB0
Palette
C
Palette
B
SEGSA0
Palette
B
Palette
C
Palette
A
SEGSB2
SEGSC2
SEGSA3
SEGSC3
Palette
C
Palette
B
Palette
A
SEGSA2
SEGSB3
Palette
C
Palette
A
SEGSA1
SEGSC1
Palette
C
SEGSC0
Palette
B
Palette
B
SEGSB0
SEGSB1
Palette
A
SEGSA0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
X=00H
X=01H
SEGSB3
Palette
B
Palette
A
SEGSA1
X=00H
X=03H
SEGSB1
Palette
C
SEGSC0
SWAP
1
0
Palette
A
REF
0
1
SEGSC0
SWAP
0
1
SEGSB0
REF
0
1
Palette
B
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
SWAP
1
0
SEGSB0
Palette
A
REF
0
1
Palette
B
SEGSA0
SWAP
0
1
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
REF
0
1
Palette
C
•
SEGSA0
HM17CM256
DUMMY SEGMENT REGISTER ADDRESS AND BITMAP
COLOR / 16 BIT MODE
X address / bit segment assign
X=01H
X=00H
X address / bit segment assign
X=01H
X=00H
COLOR / 8 BIT MODE
X=03H
X=00H
X=03H
X=00H
- 27 -
- 28 SEGSC3
X address / bit segment assign
X=01H
X=02H
X=02H
X=01H
SEGSC3
SEGSB3
X address / bit segment assign
X=01H
X=02H
X=02H
X=01H
SEGSB3
SEGSA3
SEGSC2
SEGSB2
SEGSA2
SEGSC1
SEGSC3
SEGSB3
SEGSA3
SEGSC2
SEGSB2
SEGSA2
SEGSC1
SEGSB1
X=00H
X=01H
SEGSA3
X=00H
X=03H
SEGSB1
SEGSA1
SEGSA1
SEGSC0
SEGSA0
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
SEGSC3
SEGSB3
SEGSA3
SEGSC2
SEGSB2
SEGSA2
SEGSC1
SEGSB1
SEGSA1
SEGSC0
SEGSB0
X=00H
X=01H
SEGSC2
SWAP
1
0
SEGSB2
REF
0
1
X=00H
X=03H
SEGSA2
SWAP
0
1
SEGSC1
REF
0
1
SEGSC0
•
SEGSB0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SWAP
1
0
SEGSB0
SEGSA0
REF
0
1
SEGSB1
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
SWAP
0
1
SEGSA1
SEGSA0
REF
0
1
SEGSC0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
D7
D6
D5
D4
D3
D2
D1
D0
•
SEGSB0
SEGSA0
HM17CM256
BLACK 7 WHITE / 16 BIT MODE
X address / bit segment assign
X=01H
X=00H
X address / bit segment assign
X=01H
X=00H
BLACK & WHITE / 8 BIT MODE
X=03H
X=00H
X=03H
X=00H
HM17CM256
(11)
display data structure and gradation control
For the purpose of gradation control, information per pixel requires multiple bits. This IC has 3 bit
or 2 bit data per output to achieve the gradation display.
This IC is connected to an STN color LCD panel by three segment port units and one pixel consists
of three outputs of segment driver, and so 256 color ( 3 bits x 3 bits x 2 bits ) display on 128 x 82
pixels is realized.
Since one pixel data can be processed by one time access to memory, the data can be rewritten
fast and naturally.
The weight of each data bit is dependent on the status of SWAP register bit and REF register
when data is written to the display RAM.
•
ACCESS when (REF, SWAP)=(0, 0) or (1, 1)
SEGBi
SEGAi
h
Palette AjAj
i
j
SEGCi
Palette Bj
k
i=0~127
Gradation palette
j=0~7
Palette Cj
Gradation
control circuit.
0
GLSB circuit
0
0
1
0
MSB
LSB
0
0
1
D0
D1
D2
0
1
1
MSB
LSB
0
0
1
1
1
D3
D4
D5
D6
D7
Display RAM data
1
MSB
CPU access data
X address :nH
notice) internal access X address :nH~7FH (access when REF=”0”)
:7FH~nH (access when REF=”1”)
•
ACCESS when (REF, SWAP)=(0, 1) or (1, 0)
SEGAi
Gradation palette
j=0~7
Palette Cj
SEGBi
SEGCi
Palette Bj
Palette Aj
i=0~127
Gradation
control circuit
0
Display RAM data
1
1
MSB
CPU access data
X address :nH
1
0
0
LSB MSB
1
0
0
LSB MSB
GLSB circuit
0
0
1
0
0
1
1
1
D0
D1
D2
D3
D4
D5
D6
D7
notice) internal access X address :nH~7FH (access when REF=”0”)
:7FH~nH (access when REF=”1”)
- 29 -
HM17CM256
When display RAM is accessed by 16 bit data width, the weight of each data bit is dependent on
the status of SWAP register and REF register, the same method as 8 bit access
•
ACCESS when (REF, SWAP)=(0, 0) or (1, 1)
SEGAi
SEGBi
SEGCi
SEGAi+1
Palette Aj
Palette Bj
Palette Cj
Palette Aj
SEGBi+1
SEGCi+1
Palette Bj
i=0~126
Gradation palette
j=0~7
Palette Cj
Gradation
control ciruit
0
GLSB circuit
0
0
1
0
0
MSB LSB
0
0
1
1
1
MSB LSB
1
0
0
0
MSB
1
1
0
1
0
0
MSB LSB
1
0
0
1
1
1
MSB LSB
0
0
Display RAM data
1
MSB
1
1
CPU access data
X address :nH
1
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15
notice) internal access X address :nH~3FH (access when REF=”0”)
:3FH~nH (access when REF=”1”)
•
ACCESS when (REF, SWAP)=(0, 1) or (1, 0)
SEGAi
Gradation palette
Palette Cj
SEGBi
SEGCi
Palette Bj
Palette Aj
SEGAi+1
SEGBi+1
SEGCi+1
i=0~126
Palette Bj
Palette Aj
j=0~7
Palette Cj
Graydation
control ciruit
0
Display RAM data
1
1
MSB
CPU access data
X address :nH
1
0
0
LSB MSB
0
0
1
D0
D1
D2
0
1
0
0
LSB MSB
1
1
MSB
0
1
1
1
0
D3 D4
D5
D6
D7
D8
0
0
LSB MSB
0
1
0
1
0
0
LSB MSB
0
1
1
1
D9 D10 D11 D12 D13 D14 D15
notice) internal access X address :nH~3FH (access when REF=”0”)
:3FH~nH (access when REF=”1”)
- 30 -
1
GLSB circuit
HM17CM256
DISPLAY RAM BITMAP AT BLACK & WHITE MODE (MON=”1”)
The MSBs of display RAM data ( 3 bit, 2 bit ) is used as display data at black and white mode.
l
example)
•
8 bit width access ( the same method as 16 bit width access)
ACCESS when (REF, SWAP)=(0, 0) or (1, 1)
SEGAi
m
n
o
SEGBi
SEGCi
i=0~127
Palette Bj
Palette Cj
Gradation palette
j=0~7
p
Palette AjAj
Gradation control circuit.
0
GLSB circuit
0
0
1
MSB
LSB
0
0
1
D0
D1
D2
0
0
1
1
1
MSB
LSB
0
0
1
1
1
D3
D4
D5
D6
D7
Display RAM data
MSB
CPU access data
X address :nH
notice) internal access X address :nH
(access when REF=”0”)
:7FnH~nH (access when REF=”1”)
•
ACCESS when (REF, SWAP)=(0, 1) or (1, 0)
Gradation palette
j=0~7
SEGAi
SEGBi
SEGCi
Palette Aj
Palette Bj
Palette Cj
i=0~127
Gradation control circuit
0
Display RAM data
1
1
MSB
CPU access data
X address :nH
1
0
0
LSB MSB
1
0
0
GLSB circuit
LSB MSB
0
0
1
0
0
1
1
1
D0
D1
D2
D3
D4
D5
D6
D7
notice) internal access X address :nH
(access when REF=”0”)
:7FnH~nH (access when REF=”1”)
- 31 -
HM17CM256
gradation level table (MON=”1”, Black & white mode)
(MSB)RAM data (LSB)
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Gradation level
0
0
0
0
1
1
1
1
RAM data
GLSB
0
0
*
0
1
*
1
0
*
1
1
*
* : Don’t Care
Gradation level
0
0
1
1
(12)
GRADATION LSB CONTROL
At 256 colors input mode, this IC provides segment driver output for 8-gradation display using
successive 3 bits of data and that for 4-gradation display using successive 2 bits of data.
The segment driver output for the 4-gradation display uses 2 bits written to the corresponding RAM
area and 1 bit supplemented by the gradation LSB circuit, and then selects 4 gradations from 8gradations.
At fixed gradation mode, the segment driver output for the 4-gradation display result in a gradation
level of 0 regardless of gradation LSB register, when 2 bits of data on the display RAM are “00”.
When 2 bits of data on the display RAM is “11”, a gradation level of 7/7 is selected regardless of
gradation LSB register.
The other gradation levels are selected depending on 2 bits of data on the
display RAM and the gradation LSB register.
One bit of data is supplemented by setting the gradation LSB register (GLSB).
For this register, the bit information specified for only one time setting is used as the LSB of the
RAM for all the 4-gradation segment drivers.
Gradation LSB = “0”: Set 0 as the LSB of the RAM for 4-gradation segment drivers.
Gradation LSB = “1”: Set 1 as the LSB of the RAM for 4-gradation segment drivers.
(13)
GRADATION PALETTE
This IC has two gradation display modes, the fixed gradation display mode and the variable
gradation display mode.
Select mode by setting the gradation display mode register (PWM command) to the purpose.
PWM=”0” : variable gradation mode among 32-level gradations.
PWM=”1” : fixed 8 gradation mode
To select the best gradation level suited to LCD panel at variable gradation display mode, use the
gradation palette register among 32-level gradation palettes. Segment driver outputs are set by
selected 8-level gradation palette.
The gradation palette register provides three registers ( palette Aj, Bj, and Cj : j=0∼7 ) for the
segment driver outputs, SEGAi(0∼127), SEGBi(0∼127), and SEGCi(0∼127) .
Each register
consists of a 5-bit register, selecting 8 gradations from the 32 gradation pattern.
Segment driver selects 4 gradations among 8 gradation by 2 bits wrote-in RAM and 1bit calibrated
by GLSB.
- 32 -
HM17CM256
GRADATION PALETTE INITIAL VALUE
( palette Aj, palette Bj, palette Cj (j=0~7) )
(MSB)RAM data (LSB)
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Register name
Gradation palette 0
Gradation palette 1
Gradation palette 2
Gradation palette 3
Gradation palette 4
Gradation palette 5
Gradation palette 6
Gradation palette 7
Initial value
00000
00101
01010
01110
10001
10101
11010
11111
GRADATION PALETTE TABLE (PWM=”0”, variable mode)
( palette Aj, palette Bj, palette Cj (j=0~7) )
Palette
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
Gradation
0
1/31
2/31
3/31
4/31
5/31
6/31
7/31
8/31
9/31
10/31
11/31
12/31
13/31
14/31
15/31
remark
Palette 0 initial value
Palette 1 initial value
Palette 2 initial value
Palette 3 initial value
Palette
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
gradation
16/31
17/31
18/31
19/31
20/31
21/31
22/31
23/31
24/31
25/31
26/31
27/31
28/31
29/31
30/31
31/31
remark
Palette 4 initial value
Palette 5 initial value
Palette 6 initial value
Palette 7 initial value
GRADATION PALETTE TABLE (PWM=”1”, fixed mode)
(MSB)RAM data(LSB)
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
gradation
0
1/7
2/7
3/7
4/7
5/7
6/7
7/7
RAM data
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
GLSB
0
1
0
1
0
1
0
1
gradation
0
2/7
3/7
4/7
5/7
7/7
- 33 -
HM17CM256
(14)
DISPLAY TIMMING GENERATOR
The display-timing generator makes a timing clock and timing pulses (CL, FLM, FR and CLK) for
internal operation by inputting the original oscillating clock CK or by the oscillating circuit.
By setting up Master / Slave mode (M/S), the state of timing pulse pins and the timing generator
changes.
Display timing pulse pins and generator status
M/S port
mode
CL port
FR port FLM port CLK port
L
Slave
Input
Input
Input
Input
H
Master
Output
Output
Output
Output
Timing generator status
CL, FLM, FR signal generator stop
Operating status
(15)
SIGNAL GENERATION OF DISPLAY LINE COUNTER, DISPLAY DATA LATCH CIRCUIT.
The latch signal from line counter clock to display data latch circuit is generated from display clock
(CL). Synchronized with the display clock, the line addresses of Display RAM are generated and
384-bit display data are latched to display-data latching circuit and then output to the LCD drive
circuit (SEG output port).
Read-out of the display data to the LCD drive circuit is completely independent of MPU side and so
MPU can access it with no relationship with the read-out operation of the display data.
(16)
GENERATION OF THE ALTERNATED SIGNAL(FR), SYNCHRONOUS SIGNAL(FLM).
The alternated signal (FR) and synchronous signal (FLM) are generated from the display clock
(CL). The FLM generates alternated drive waveform to the LCD drive circuit per frame at normal
state ( inverse FR signal level per 1 frame ). But by setting up data (n-1) on n-line inversion
register and “1” on n-line alternated command (NLIN), n-line inverse waveform can be generated.
When this HM17CM256 is used in multi-chip application, the signals of CL, FLM, FR and CLK
must be sent from master side to slave side.
(17)
DISPLAY DATA LATCH CIRCUIT
This circuit latches the display data from display RAM to LCD driver circuit temporarily per every
common period. Normal / reverse display, display ON/OFF, and display all on command are done
by controlling data in this latch. And no data within display RAM changes.
- 34 -
HM17CM256
(18) EXAMPLE OF LCD DRIVING (NORMAL MODE, 1/82 DUTY, BLACK & WHITE DISPLAY MODE)
COM0
82 1
2 3 4
5
82 1
2 3 4 5
82 1
COM1
SEG2
SEG1
SEG0
CL
FLM
FR
COM0
VLCD
V1
V2
V3
V4
VSS
COM1
VLCD
V1
V2
V3
V4
VSS
SEG0
SEG1
VLCD
V1
V2
V3
V4
VSS
VLCD
V1
V2
V3
V4
VSS
- 35 -
HM17CM256
(19)
LCD DRIVER CIRCUIT
This drive circuit generates four levels of LCD drive voltage. The circuit has 384 segment outputs
and 82 common outputs and outputs combined display data and FR signal.
Two of common outputs(COMI0,COMI1) are for pictograph marker display only. The common
drive circuit that has shift register and outputs common scan signals sequentially.
(20)
DUMMY SEGMENT DRIVER CIRCUIT
Segment driver circuit has 6 dummy output ( SEGSA0 ~ SEGSA3, SEGSB0 ~ SEGSB3, SEGSC0 ~
SEGSC3 ) at each edge side. Normally, the segment driver output is generated by memorized
RAM data but there are no RAMs but registers for dummy segment driver. There are 8 bit registers
correspond to SEGSA0, SEGSB0, SEGSC0 and drive LCD with same level to Y direction. ( SEGSA1
~ SEGSA3, SEGSB1 ~ SEGSB3, SEGSC1 ~ SEGSC3 are the same function. )
SEGSA0 ~ SEGSA3 port is used same gradation palette with SEGA0 ~ SEGA127, SEGSB0 ~
SEGSB3 with SEGB0 ~ SEGB127 , and SEGSC0 ~ SEGSC3 with SEGC0 ~ SEGC127
This circuit is effective at display of boundary or background display.
The dummy segment
drivers do not depend on LREV polarity but ALLON and REV command for display
There are 4-byte registers for dummy segment driver, SEGSA0 ~ SEGSA3, SEGSB0 ~ SEGSB3,
SEGSC0 ~ SEGSC3, If you want to access this register, please use DMY =”1” command.
68 series
RS
DMY
0
0
0
0
0
0
1
1
R/W
1
0
1
0
80 series
RD
0
1
0
1
WR
1
0
1
0
Function
Read out display data
Write in display data
Read out dummy segment register
Write in dummy segment register
There are the same rules at read out of dummy segment register as display RAM data read out
sequence.
After address setting, the data of assigned address is shown directly after the end of
the read command, so pay attention that assigned data is available at 2nd timing step. In other
words, there needs 1 cycle dummy read after address set and write cycle.
1 cycle dummy read is necessary for after address setting and write cycle.
When access with DMY=”1”, X address is an effective value at address setting. There are 4-byte
and so 00H, 01H, 02H, 03H are effective at 8-bit mode and 00H, 01H are effective at 16-bit mode.
The access bears no relation to Y address setting.
When access with DMY=”1”, it is possible that the data is written into register by increment
operation.
notice) more detail information at DUMMY SEGMENT REGISTER ADDRESS AND BITMAP in (10) Relation
between Display RAM and address
q
t
- 36 -
r
s
HM17CM256
ACCESS WITH 8 BIT BUS EXAMPLE : GRAY MODE , ACCESS UNDER (REF, SWAP)=(0, 0)
SEGSA0
Palette Aj
SEGSB0
SEGSC0
Palette Bj
Palette Cj
Gradation
j=0~7
palette
Gradation control circuit
0
GLSB circuit
0
0
1
0
MSB
LSB
0
0
1
D0
D1
D2
0
1
1
1
MSB
LSB
0
0
1
1
1
D3
D4
D5
D6
D7
Latched data
MSB
CPU access data
X address :00H
SEGSA3
Palette Aj
SEGSB3
SEGSC3
Palette Bj
Palette Cj
Gradation palette
j=0~7
Gradation control circuit
0
GLSB circuit
0
0
1
MSB
LSB
0
0
1
D0
D1
D2
0
0
1
1
1
MSB
LSB
0
0
1
1
1
D3
D4
D5
D6
D7
Latched data
MSB
CPU access data
X address :03H
(21) OSCILLATOR CIRCUIT
HM17CM256 has the CR oscillator. The output of oscillator is used as the timing signal source of
display and boosting clock to the booster. This is valid only in the master operation mode.
When in the master operation mode and if external clock is used, feed the clock to OSC1 pin or
connect resistor between OSC1 and OSC2.
And feedback resistance with command can set the inner oscillator circuit of HM17CM256.
The frame frequency can be altered by changed oscillator frequency according to feedback
resistance length set value. To get optimum frame frequency, please check LCD and then set the
frequency of oscillator.
(22) POWER SUPPLY CIRCUIT
- 37 -
HM17CM256
This block generates the voltages necessary for driving LCD panel. The power supply circuit
consists of voltage boosting circuit and voltage converting circuit and generates the voltages (VLCD,
V1, V2, V3, V4. ) for LCD driving.
For large panel driving, it’s preferable to use external voltage source rather than to use built-in
power supply circuit for good image quality.
When using external voltage source, disable the built-in power supply circuit(AMPON, DCON=‘00’),
supply the VLCD, V1, V2, V3, V4 and VOUT externally and open the C1+, C1-, C2+, C2-, C3+, C3-, C4+, C4-,
C5+, C5-, C6+, C6-, VREF, VREG, VEE terminals.
According to power supply circuit control command input, the power supply circuit can be enabled
partially.
External power supply and partial inner power circuit can be used together. Refer to the
next table.
DCON
AMPON
0
0
1
0
1
1
Boosting circuit
Disable
Disable
Enable
Converting circuit
disable
enable
enable
External voltage input
VOUT, VLCD, V1, V2, V3, V4 common
VOUT common
−
remark
1,3
2,3
−
u
u
v
v
v
1. All the built-in boosting circuit, converting circuit is not used. Open the ,C1+, C1-, C2+, C2-, C3+, C3-, C4+,
C4-, C5+, C5-, C6+, C6-, VREF, VREG, VEE terminals, LCD driving voltage should be applied externally.
2.Only the Boosting circuit is not used. Open the C1+,C1-,C2+,C2-,C3+,C3-,C4+,C4-,C5+,C5-,C6+,C6-, VOUT
terminals, The power for converting circuit must be supplied through VOUT terminal and the reference
voltage must be supplied by VREF terminal.
3.The conditions between VOUT, VLCD, V1, V2, V3, and V4 are VOUT ≥ VLCD ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS.
(23) VOLTAGE BOOSTING CIRCUIT
By connecting capacitor CA1 between C1+ and C1-, C2+ and C2-, C3+ and C3-, C4+ and C4-, C5+
and C5- , C6+ and C6-, VOUT and VSS , n-time boosted voltage of VEE - VSS can be generated through
VOUT port. The boosting coefficient can be set by command and 2-times/ 3-times / 4-times/ 5times/ 6-times/ 7-times boosted voltage is output through VOUT port.
At application, specific boosting coefficient is used, refer to the following description.
At 2-times boosting is designed, connect boosting capacitor CA1 between C1+ and C1- , and
open C2+, C2-, C3+, C3-, C4+, C4-, C5+, C5-, C6+, C6- terminals.
At 3-times boosting is designed, connect boosting capacitor CA1 between C1+ and C1- , C2+
and C2- , and open C3+,C3-, C4+, C4-, C5+, C5-, C6+, C6- terminals.
At 4-times boosting is designed, connect boosting capacitor CA1 between C1+ and C1- , C2+
and C2- , C3+ and C3- , and open C4+, C4-, C5+, C5-, C6+, C6- terminals
At 5-times/ 6-times/ 7-times boosting are same structures with upper case.
w
x
y
z
Special care should be taken so that the voltage of VOUT would not exceed 18V MAX.
VOUT voltage exceeding 18V can cause malfunction and reliability problem.
VOUT=17.5V
VOUT=9V
VEE=3V
VEE=2.5V
VSS=0V
VSS=0V
3-times boosting
- 38 -
7-times boosting
HM17CM256
(24) ELECTRIC VOLUME
The electric volume is within voltage converting circuit and the brightness of LCD can be controlled
by adjusting VLCD level with command.
The LCD driving voltage VLCD is generated by selecting 1 level within 128 step electric volume
controlled levels by setting 7 bit electric volume register.
(25)
VOLTAGE REGULATOR CIRCUIT
The voltage regulator circuit is within voltage converting circuit and generates regulated voltage
using VREF input with magnification by adjusting internal resistor. The generated voltage by voltage
regulator is output at VREG terminal.
Even though boosted voltage variation, generated regulator
voltage is stable because boosting voltage level is higher than the amplified regulator voltage VREG .
And so, stable voltage level can be generated even if there is load variation.
VREG is used as input voltage of electric volume circuit to generate LCD driving voltage.
(26) REFERENCE VOLTAGE GENERATION CIRCUIT
The reference voltage generation circuit is within voltage converting circuit.
This circuit generates reference voltage VBA terminal for using at regulator circuit through.
output voltage level from VBA terminal is as following description.
The
VBA = VEE x 0.9
The LCD driving voltages can be made by applying reference voltage to reference voltage input
terminal VREF .
(27)
LCD DRIVING VOLTAGE GENERATION CIRCUIT
The generation circuit of LCD driving voltage is within voltage converting circuit and generates
voltages VLCD, V1, V2, V3, V4 by resistively dividing VLCD into 4 levels.
The bias ratio of LCD driving voltages can be one of 1/5, 1/6, 1/7, 1/8, 1/9, 1/10.
When using built-in power supply circuit, you should connect voltage stabilization capacitor CA2 at
each of LCD power terminals.
There is need for selecting the coefficient of capacitor CA2 after
display the LCD.
When using external voltage supply, disable the built-in power supply circuit(AMPON, DCON=‘00’),
supply the VOUT, VLCD, V1, V2, V3, V4 voltages externally and open the C1+ , C1- , C2+ , C2- , C3+ , C3- ,
C4+ , C4- , C5+ , C5- , C6+ , C6- , VEE , VREF , VREG terminals.
When using external voltage source and parts of built-in voltage converting circuit, the terminals of
C1+ , C1- , C2+ , C2- , C3+ , C3- , C4+ , C4- , C5+ , C5- , C6+ , C6- should be open because boosting
circuit is not activated, you should supply reference voltage through VREF terminal and the voltage for
voltage converting circuit at VOUT .
Connecting stabilization capacitor CA3 at VREG terminal is recommended.
- 39 -
HM17CM256
internal power circuit / internal reference voltage
generating circuit are activated case.(7 times boosting)
VDD
VDD
VEE
CA3
VSS
CA1
CA1
CA1
CA1
CA1
VSS
CA2
CA2
CA2
CA2
CA2
VSS
value
CA1
CA2
CA3
caution
- 40 -
{
VDD
VEE
VBA
VREF
VREF
VREG
VREG
C1-
C1-
C1+
C1+
C2-
C2-
C2+
C2+
C3-
C3-
C3+
C3+
C4+
CA1
VDD
VBA
C4-
CA1
internal power circuit is not used case
C4-
HM17CM256
C4+
C5-
C5-
C5+
C5+
C6-
C6-
C6+
C6+
VOUT
VOUT
VLCD
V1
VLCD
VLCD
V1
V3
V1
Extnal
power V2
circuit
V3
V4
V4
V4
V2
1.0 ~ 4.7µF
1.0 ~ 2.2µF
0.1µF
Please use B grade capacitor.
V2
V3
HM17CM256
HM17CM256
Internal power circuit is used case. Reference
voltage input from outside . (7 times boosting)
VDD
VREF
thermistor
VREF
C3-
C4+
HM17CM256
C6-
VOUT
CA2
CA2
CA2
CA2
CA2
C3+
C4C4+
C5+
C6C6+
VOUT
CA1
VSS
VLCD
CA2
V1
CA2
V2
CA2
V3
CA2
V4
VSS
HM17CM256
C5-
CA1
C6+
CA1
VSS
C3-
CA1
C5+
CA1
C2+
CA1
C5-
CA1
C2-
CA1
C3+
C4-
C1+
CA1
C2+
CA1
C1-
CA1
C2-
CA1
VREG
CA3
VSS
C1+
CA1
|
VBA
C1-
used case.
by
external
VDD
VEE
VBA
VREG
CA1
value
CA1
CA2
CA3
caution
VDD
VDD
VEE
CA3
VSS
VSS
Internal power circuit is
Temperature
compensation
thermistor . (7 times boosting )
CA2
VLCD
V1
V2
V3
V4
1.0 ~ 4.7µF
1.0 ~ 2.2µF
0.1µF
Please use B grade capacitor.
- 41 -
HM17CM256
Internal power circuit is used case. (boosting circuit is
not used, VOUT is supplied from outside)
VDD
VDD
VEE
VBA
VREF
VREG
CA3
VSS
C1C1+
C2C2+
C3C3+
C4-
HM17CM256
C4+
C5C5+
C6C6+
External
power
circuit
VOUT
CA2
CA2
CA2
CA2
CA2
VSS
value
CA1
CA2
CA3
caution
- 42 -
}
VLCD
V1
V2
V3
V4
1.0 ~ 4.7µF
1.0 ~ 2.2µF
0.1µF
Please use B grade capacitor.
HM17CM256
(28) PARTIAL DISPLAY FUNCTION
HM17CM256 can realize the partial display at graphic display area on LCD panel.
Partial display is used with lower duty than normal state at driving.
And so, HM17CM256 can drive the LCD panel with lower bias ratio, lower boosting times and
lower LCD driving voltages, and that can drive the LCD panel with lower power consumption.
This function is suitable for calendar or clock display at mobile information apparatus.
PARTIAL DISPLAY IMAGE
HYUNDAI
LCD DRIVER
Low Power and
Low Voltage
LCD DRIVER
Normal display
partial display
The next sequence should be followed carefully to realize partial display function.
Any display states
DISPLAY OFF(ON/OFF=”0”)
built-in power source OFF(DCON=”0”, AMPON=”0”)
WAIT
~
Setting the power supply circuit
boosting coefficient
electric volume
bias ratio
~
~
Built-in power source ON(DCON=”1”, AMPON=”1”)
WAIT
~
Setting the display-related function
~
~
duty ratio
display start line setting
display start command
and so on.
Display ON(ON/OFF=”1”)
Partial display state
- 43 -
HM17CM256
When using partial display function, the display duty can be selected among 1/17, 1/26, 1/32, 1/38,
1/47, 1/66, 1/77 by setting the LCD duty set command.
The display states such as LCD driving bias ratio, LCD Driving voltage, electric volume setting
value, boosting coefficient should be optimized to the selected LCD and display duty.
(29) DISCHARGE CIRCUIT
The discharge circuit of voltage(VLCD, V1~V4) stabilization capacitor is built in the HM17CM256.
To discharge the capacitors, set the DIS register to “1” or set the RES terminal to “0”. When builtin power supply circuit is used, built-in power supply circuit should be disabled before discharging of
the capacitor is executed. When external power supply(VLCD, V1~V4, VOUT) is used, external power
supply should be turned off before discharging of the capacitor is executed. Do not turn on the
internal power supply and external power supply (VLCD, V1~V4, VOUT) during discharging is executed.
(30) RESET CIRCUIT
HM17CM256 is initialized as following description when RES terminal is set to “L”.
INITIAL SETTING CONDITION (default setting)
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
display RAM
:unknown
X address
:00H set
Y address
:00H set
display start line
:1 line value 0H
display ON/OFF
:display OFF
positive/negative
:positive
display duty ratio
:1/82
n line inversion
:n inversion disable
COM shift direction
:COM0 → COM79, COMI0, COMI1
increment mode
:increment OFF
REF mode
:positive
data SWAP mode
:OFF
electric volume
:(0, 0, 0, 0, 0, 0, 0)
power circuit
:OFF
display mode :gradation display mode
bias ratio
:1/10 bias
gradation palette 0
:(0, 0, 0, 0, 0)
gradation palette 1
:(0, 0, 1, 0, 1)
gradation palette 2
:(0, 1, 0, 1, 0)
gradation palette 3
:(0, 1, 1, 1, 0)
gradation palette 4
:(1, 0, 0, 0, 1)
gradation palette 5
:(1, 0, 1, 0, 1)
gradation palette 6
:(1, 1, 0, 1, 0)
gradation palette 7
:(1, 1, 1, 1, 1)
gradation mode
:variable mode
GLSB
:"0"
RAM data length
:8 bit mode
discharge register
:"0"
Usually RES terminal is connected reset terminal of CPU, so that the chip can be initialized
simultaneously with CPU. HM17CM256 should be initialized when the power is on.
- 44 -
HM17CM256
(31) SUPPLYING POWER AND ON/OFF SEQUENCE
Special care should be taken to the next notice. Supplying the power at LCD driving voltage
terminal when the logic VDD is floating can cause over-current and damage the IC
(31-1) WHEN USING EXTERNAL POWER SUPPLY

power ON sequence
Reset the IC after supplying the logic power at VDD terminal, and then turn on the LCD driving
voltage at the terminals (VLCD, V1, V2, V3, V4).
And when internal voltage converter is used, reset the IC after supplying the logic power at
VDD terminal, and then supply power to VLCD terminal.
€
power OFF sequence
Execute HALT command or reset the IC to turn off the outputs of LCD driving output port, and
then turn off the LCD driving voltage after logic power OFF.
Inserting series resistor of 50 ~100Ω or fuse at VLCD or VOUT terminal (when only internal
voltage converting circuit is used) is recommended to prevent over-current.
This series resistor should be selected carefully because image quality can be dependent on.
(31-2) WHEN USING BUILT-IN POWER SUPPLY CIRCUIT
power ON sequence
€
Reset the IC after supplying the logic power at VDD terminal or after supplying power through
voltage common port (VEE) of boosting voltage generation and then operate internal power
circuit by command.
And when internal voltage converter is used, reset the IC after supplying the logic power at
VDD terminal, and then supply power to VLCD terminal.
You should turn on the display after the output level of internal power module is set.
If you do not keep this sequence, LCD can display wrong data.
€
power OFF sequence
To make off state of LCD driving output, cut the source to voltage common port (VEE) of
boosting voltage generation, the logic power at VDD terminal after reset the IC by HALT
command.
If VEE, and VDD are supplied from different power source, VEE terminal should be turned on/off
during VDD terminal voltage maintain voltage level specified in specification sheet.
Specially, when turn off the power, after cut the source to voltage common port (VEE), and then
turn off the logic power at VDD terminal after the voltage levels of VEE, VOUT, VLCD, V1~V4 become
under LCD on voltage(LCD threshold voltage)level.
- 45 -
HM17CM256
(32) COMMAND SETTING EXAMPLE
(32-1) initial setting
VDD, VEE-VSS power ON
Power stable
RESET input
WAIT

Function setting by command (user setting
electric volume code set
bias ratio set
‚


Function setting by command (user setting
power control set
(DCON=”1”, AMPON=”1”)
ƒ
End of initial setting
(notice) If the voltage level of VEE and VDD are different, VDD should be inputted first.
(32-2) DATA DISPLAY
End of initialization
Function setting by command (user setting)

display start line set
increment mode set
X address set
Y address set




Function setting by command (user setting
Function setting by command (user setting)
Data display
- 46 -
display data write
„

display ON/OFF command set(ON/OFF=”1”)
HM17CM256
(32-3) POWER OFF
Any operation states
…
Function setting by command (user setting
†
…
HALT command set or reset operation
(all LCD driver output is VSS level)
Discharge command set
(discharge of VLCD, V1~V4 capacitor)
WAIT
VEE, VDD-VSS power OFF
Before turning off the power, be sure to execute HALT or RESET command to make LCD
driver output OFF state.
And if VDD and VEE have different potential (VDD and VEE are not common), be sure to turn off
VEE first during VDD is supplied.
- 47 -
HM17CM256
(33) INSTRUCTION
INSTRUCTION TABLE (1)
CODE (80 series I/F)
INSTRUCTION
CODE
CS RS RD WR RE2 RE1 RE0 D7
D6
D5
D4
FUNCTION
D3
D2
D1
D0
0
0
1
0 0/1 0/1 0/1
Write Data
Write in to display RAM
display data read out. 0
0
0
1 0/1 0/1 0/1
Read Data
Read out from display RAM
X address
(lower)
[0H]
0
1
1
0
0
0
0
0
0
0
0 AX3 AX2 AX1 AX0 Display RAM X direction set
X address
(upper)
[1H]
0
1
1
0
0
0
0
0
0
0
1
Y address
(lower)
[2H]
0
1
1
0
0
0
0
0
0
1
0
Y address
(upper)
[3H]
0
1
1
0
0
0
0
0
0
1
1
0
1
1
0
0
0
0
0
1
0
0
display data write in
display start line set
(lower)
[4H]
display start line set
*
AX6 AX5 AX4 Display RAM X direction set
AY3 AY2 AY1 AY0 Display RAM Y direction set
*
AY6 AY5 AY4 Display RAM Y direction set
RAM
Y
address
1
1
0
0
0
0
0
1
0
1
0
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
1
1
display control (1)
0
[8H]
1
1
0
0
0
0
1
0
0
0
display control (2)
0
[9H]
1
1
0
0
0
0
1
0
0
1
increment control
0
[AH]
1
1
0
0
0
0
1
0
1
0 WIN AIM AYI AXI
0
1
1
0
0
0
0
1
0
1
1
0
1
1
0
0
0
0
1
1
0
0
*
DS2 DS1 DS0 LCD driver duty ratio set
boosting coefficient
0
set
[DH]
1
1
0
0
0
0
1
1
0
1
*
VU2 VU1 VU0 Boosting times set
0
1
1
0
0
0
0
1
1
1
0
*
B2 B1 B0 LCD drive bias set
0
1
1
0 0/1 0/1 0/1 1
1
1
1
[5H]
N line inversion set
(lower)
[6H]
N line inversion set
(upper)
[7H]
power control
[BH]
LCD duty set
[CH]
bias ratio set
[EH]
RE register set
[FH]
*
common driver.
RAM
Y
address
setting
LA4 corresponds to scan start line of
common driver.
0
(upper)
setting
LA3 LA2 LA1 LA0 corresponds to scan start line of
LA6 LA5
N3 N2 N1 N0 quantity setting of line inversion
*
N6 N5 N4 quantity setting of line inversion
SHIFT: common shift direction set,
SHI MO ALL ON/ MON: BW/gradation display,
FT N ON OFF ALLON: all on ,
RE
V
NL SW RE
IN AP F
ON/OFF: display ON/OFF control
REV: display positive / negative,
NLIN: n line inversion ON/OFF,
SWAP: display data swap,
REF: segment positive / negative
WIN: window selection,
AIM: increment timing selection,
AYI:Y increment,
AXI:X increment
internal OP Amp. ON,
AMP HA DC AC AMPON:
HALT: power save
ON LT ON L DCON: boosting circuit ON, ACL: reset
TST0 RE2 RE1 RE0
RE flag set
Notice 1) * mark is Don’t Care
Notice 2) [ ] The inner side number is an address for internal register read.
Notice 3) The commands that upper/lower register settings are demanded are effective at the point of commands input.
But electric volume is effective after upper and lower register setting.
- 48 -
HM17CM256
INSTRUCTION TABLE (2)
CODE (80 series I/F)
INSTRUCTION
CODE
CS RS RD WR RE2 RE1 RE0 D7
Gradation palette A0 set
(lower)
0
0
0
Set value to gradation palette
0 PA03 PA02 PA01 PA00 A
0
1
1
0
0
0
1
0
0
0
1
1
1
0
0
0
1
0
0
1
Set value to gradation palette
0 PA13 PA12 PA11 PA10 A
1
1
1
0
0
0
1
0
0
1
1
1
1
0
0
0
1
0
1
0
Set value to gradation palette
0 PA23 PA22 PA21 PA20 A
2
1
1
0
0
0
1
0
1
0
1
1
1
0
0
0
1
0
1
1
Set value to gradation palette
0 PA33 PA32 PA31 PA30 A
3
1
1
0
0
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
Set value to gradation palette
0 PA43 PA42 PA41 PA40 A
4
1
1
0
0
0
1
1
0
0
1
1
1
0
0
0
1
1
0
1
Set value to gradation palette
0 PA53 PA52 PA51 PA50 A
5
1
1
0
0
0
1
1
0
1
1
1
1
0
0
0
1
1
1
0
Set value to gradation palette
0 PA63 PA62 PA61 PA60 A
6
[DH] 0
1
1
0
0
0
1
1
1
0
1
0
1
1
0 0/1 0/1 0/1 1
1
1
1
[1H] 0
[2H] 0
[3H] 0
[4H] 0
[5H] 0
[6H] 0
Gradation palette A3 set
(upper)
[7H] 0
Gradation palette A4 set
(lower)
[8H] 0
Gradation palette A4 set
(upper)
[9H] 0
Gradation palette A5 set
(lower)
[AH] 0
Gradation palette A5 set
(upper)
[BH] 0
Gradation palette A6 set
(lower)
[CH] 0
Gradation palette A6 set
(upper)
D0
1
Gradation palette A3 set
(lower)
D1
0
Gradation palette A2 set
(upper)
FUNCTION
D2
0
Gradation palette A2 set
(lower)
D3
0
Gradation palette A1 set
(upper)
D4
1
Gradation palette A1 set
(lower)
D5
1
[0H] 0
Gradation palette A0 set
(upper)
D6
RE register set
[FH]
*
*
*
*
*
*
*
*
*
*
*
*
*
*
Set value to gradation palette
* PA04 A
0
Set value to gradation palette
* PA14 A
1
Set value to gradation palette
* PA24 A
2
Set value to gradation palette
* PA34 A
3
Set value to gradation palette
* PA44 A
4
Set value to gradation palette
* PA54 A
5
Set value to gradation palette
* PA64 A
6
TST0 RE2 RE1 RE0
RE flag set
Notice 1) * mark is Don’t Care
Notice 2) [ ] The inner side number is an address for internal register read.
Notice 3) The commands that upper/lower register settings are demanded are effective at the point of commands input.
But electric volume is effective after upper and lower register setting.
- 49 -
HM17CM256
INSTRUCTION TABLE (3)
CODE (80 series I/F)
INSTRUCTION
CODE
CS RS RD WR RE2 RE1 RE0 D7
Gradation palette A7 set
(lower)
0
0
0
Set value to gradation palette
0 PA73 PA72 PA71 PA70 A
7
1
1
0
0
1
0
0
0
0
1
1
1
0
0
1
0
0
0
1
Set value to gradation palette
0 PB03 PB02 PB01 PB00 B
0
1
1
0
0
1
0
0
0
1
1
1
1
0
0
1
0
0
1
0
Set value to gradation palette
0 PB13 PB12 PB11 PB10 B
1
1
1
0
0
1
0
0
1
0
1
1
1
0
0
1
0
0
1
1
Set value to gradation palette
0 PB23 PB22 PB21 PB20 B
2
1
1
0
0
1
0
0
1
1
1
1
1
0
0
1
0
1
0
0
Set value to gradation palette
0 PB33 PB32 PB31 PB30 B
3
1
1
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
0
1
Set value to gradation palette
0 PB43 PB42 PB41 PB40 B
4
1
1
0
0
1
0
1
0
1
1
1
1
0
0
1
0
1
1
0
Set value to gradation palette
0 PB53 PB52 PB51 PB50 B
5
[DH] 0
1
1
0
0
1
0
1
1
0
1
0
1
1
0 0/1 0/1 0/1 1
1
1
1
[1H] 0
[2H] 0
[3H] 0
[4H] 0
[5H] 0
[6H] 0
Gradation palette B2 set
(upper)
[7H] 0
Gradation palette B3 set
(lower)
[8H] 0
Gradation palette B3 set
(upper)
[9H] 0
Gradation palette B4 set
(lower)
[AH] 0
Gradation palette B4 set
(upper)
[BH] 0
Gradation palette B5 set
(lower)
[CH] 0
Gradation palette B5 set
(upper)
D0
0
Gradation palette B2 set
(lower)
D1
1
Gradation palette B1 set
(upper)
FUNCTION
D2
0
Gradation palette B1 set
(lower)
D3
0
Gradation palette B0 set
(upper)
D4
1
Gradation palette B0 set
(lower)
D5
1
[0H] 0
Gradation palette A7 set
(upper)
D6
RE register set
[FH]
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
PA74
PB04
PB14
PB24
PB34
PB44
PB54
TST0 RE2 RE1 RE0
Set value to gradation palette
A7
Set value to gradation palette
B0
Set value to gradation palette
B1
Set value to gradation palette
B2
Set value to gradation palette
B3
Set value to gradation palette
B4
Set value to gradation palette
B5
RE flag set
Notice 1) * mark is Don’t Care
Notice 2) [ ] The inner side number is an address for internal register read.
Notice 3) The commands that upper/lower register settings are demanded are effective at the point of commands input.
But electric volume is effective after upper and lower register setting.
- 50 -
HM17CM256
INSTRUCTION TABLE (4)
CODE (80 series I/F)
INSTRUCTION
CODE
CS RS RD WR RE2 RE1 RE0 D7
Gradation palette B6 set
(lower)
1
0
0
0
Set value to gradation palette
0 PB63 PB62 PB61 PB60 B
6
1
1
0
0
1
1
0
0
0
1
1
1
0
0
1
1
0
0
1
Set value to gradation palette
0 PB73 PB72 PB71 PB70 B
7
1
1
0
0
1
1
0
0
1
1
1
1
0
0
1
1
0
1
0
Set value to gradation palette
0 PC03 PC02 PC01 PC00 C
0
1
1
0
0
1
1
0
1
0
1
1
1
0
0
1
1
0
1
1
Set value to gradation palette
0 PC13 PC12 PC11 PC10 C
1
1
1
0
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
0
Set value to gradation palette
0 PC23 PC22 PC21 PC20 C
2
1
1
0
0
1
1
1
0
0
1
1
1
0
0
1
1
1
0
1
Set value to gradation palette
0 PC33 PC32 PC31 PC30 C
3
1
1
0
0
1
1
1
0
1
1
1
1
0
0
1
1
1
1
0
Set value to gradation palette
0 PC43 PC42 PC41 PC40 C
4
[DH] 0
1
1
0
0
1
1
1
1
0
1
0
1
1
0 0/1 0/1 0/1 1
1
1
1
[1H] 0
[2H] 0
[3H] 0
[4H] 0
[5H] 0
Gradation palette C1 set
(lower)
[6H] 0
Gradation palette C1 set
(upper)
[7H] 0
Gradation palette C2 set
(lower)
[8H] 0
Gradation palette C2 set
(upper)
[9H] 0
Gradation palette C3 set
(lower)
[AH] 0
Gradation palette C3 set
(upper)
[BH] 0
Gradation palette C4 set
(lower)
[CH] 0
Gradation palette C4 set
(upper)
D0
1
Gradation palette C0 set
(upper)
D1
0
Gradation palette C0 set
(lower)
FUNCTION
D2
0
Gradation palette B7 set
(upper)
D3
1
Gradation palette B7 set
(lower)
D5 D4
1
[0H] 0
Gradation palette B6 set
(upper)
D6
RE register set
[FH]
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
PB64
PB74
PC04
PC14
PC24
PC34
PC44
TST0 RE2 RE1 RE0
Set value to gradation palette
B6
Set value to gradation palette
B7
Set value to gradation palette
C0
Set value to gradation palette
C1
Set value to gradation palette
C2
Set value to gradation palette
C3
Set value to gradation palette
C4
RE flag set
Notice 1) * mark is Don’t Care
Notice 2) [ ] The inner side number is an address for internal register read.
Notice 3) The commands that upper/lower register settings are demanded are effective at the point of commands input.
But electric volume is effective after upper and lower register setting.
- 51 -
HM17CM256
INSTRUCTION TABLE (5)
CODE (80 series I/F)
INSTRUCTION
CODE
CS RS RD WR RE2 RE1 RE0 D7
Gradation palette C5 set
D6
D5
D4
D3
FUNCTION
D2
‡
D1
D0
1
1
0
1
0
0
0
0
0
Set value to gradation palette
0 PC53 PC52 PC51 PC50 C
1
1
0
1
0
0
0
0
0
1
1
1
0
1
0
0
0
0
1
Set value to gradation palette
0 PC63 PC62 PC61 PC60 C
1
1
0
1
0
0
0
0
1
1
1
1
0
1
0
0
0
1
0
Set value to gradation palette
0 PC73 PC72 PC71 PC70 C
1
1
0
1
0
0
0
1
0
1
*
0
1
1
0
1
0
0
0
1
1
0
*
Serial extension CS
0
control
[7H]
1
1
0
1
0
0
0
1
1
1
*
*
*
Display selection
0
control
[8H]
1
1
0
1
0
0
1
0
0
0
PW
M
GL
SB
*
0
1
1
0
1
0
0
1
0
0
1
*
0
1
1
0
1
0
0
1
0
1
Electric volume level set
0 DV3 DV2 DV1 DV0 (lower bit)
0
1
1
0
1
0
0
1
0
1
1
Oscillator Rf control
0
[DH]
1
1
0
1
0
0
1
1
0
RF: oscillator feed back resistor set
1 FFL RF2 RF1 RF0 FFL: oscillator frequency control
0
1
1
0
1
0
0
1
1
1
0
0
1
1
0 0/1 0/1 0/1 1
1
1
1
TST0 RE2 RE1 RE0
Internal register read
address set
[CH]
0
1
1
0
1
1
0
0
Register read
address
Internal register read
0
1
0
1 0/1 0/1 0/1
*
*
*
*
Read Data
(lower)
[0H] 0
Gradation palette C5 set
(upper)
[1H] 0
Gradation palette C6 set
(lower)
[2H] 0
Gradation palette C6 set
(upper)
[3H] 0
Gradation palette C7 set
(lower)
[4H] 0
Gradation palette C7 set
(upper)
[5H] 0
Display start command
set
[6H]
RAM data length set
[9H]
Electric volume
control (lower)
[AH]
Electric volume
control (upper)
[BH]
discharge
[EH]
RE register set
[FH]
1
0
0
5
*
*
Set value to gradation palette
* PC54 C
5
6
*
*
Set value to gradation palette
* PC64 C
6
7
*
*
*
Set value to gradation palette
* PC74 C
7
SC2 SC1 SC0
Common drive scan start line
set
EX Serial I/F, extension CS port
CS (EXCS) control
* Gradation display set
WL RAM access data length set
* CKS S 8 bit/16 bit selection
DV6 DV5 DV4
*
*
DIS
Electric volume level set
(upper bit)
VLCD,
V1~V4
discharge
capacitor
RE flag set
Internal register
address set
read
Internal register read out
Notice 1) * mark is Don’t Care
Notice 2) [ ] The inner side number is an address for internal register read.
Notice 3) The commands that upper/lower register settings are demanded are effective at the point of commands input.
But electric volume is effective after upper and lower register setting.
Notice 4) CKS=0: internal oscillation mode
CKS=1: external oscillation mode
Default CSK=0
- 52 -
out
HM17CM256
INSTRUCTION TABLE (6)
CODE (80 series I/F)
INSTRUCTION
CODE
CS RS RD WR RE2 RE1 RE0 D7
Window end
X address(lower)
[0H]
Window end
X address(upper)
[1H]
Window end
Y address(lower)
[2H]
Window end
Y address(upper)
[3H]
FUNCTION
D6
D5
D4
D3
D2
D1
D0
EX3 EX2 EX1 EX0
Window mode X direction end
address set
0
1
1
0
1
0
1
0
0
0
0
0
1
1
0
1
0
1
0
0
0
1
0
1
1
0
1
0
1
0
0
1
0
0
1
1
0
1
0
1
0
0
1
1
Line inversion start
0
Address (lower) [4H]
1
1
0
1
0
1
0
1
0
0
Line inversion start
0
address (upper) [5H]
1
1
0
1
0
1
0
1
0
1
Line inversion end
0
Address (lower) [6H]
1
1
0
1
0
1
0
1
1
0
Line inversion end
0
Address (upper) [7H]
1
1
0
1
0
1
0
1
1
1
*
Line inversion
control
0
1
1
0
1
0
1
1
0
0
0
*
*
BT
Dummy segment
driver address set [9 0
1
1
0
1
0
1
1
0
0
1
*
*
*
1
1
0
1
0
1
1
0
1
0
PW PW PW PW
PWM mode selection
MS MA MB MC
1
1
0 0/1 0/1 0/1 1
1
1
1
TST0 RE2 RE1 RE0
[8H]
H]
PWM mode control
0
[AH]
RE register set
[FH]
0
EX6 EX5 EX4
Window mode X direction end
address set
EY3 EY2 EY1 EY0
Window mode Y direction end
address set
*
*
EY6 EY5 EY4
Window mode Y direction end
address set
LS3 LS2 LS1 LS0 Line inversion start address set
*
LS6 LS5 LS4 Line inversion start address set
LE3 LE2 LE1 LE0 Line inversion end address set
LE6 LE5 LE4 Line inversion end address set
LR
LREV,BT: line inversion display set
EV
segment
DM Dummy
Y address selection
driver
RE flag set
Notice 1) * mark is Don’t Care
Notice 2) [ ] The inner side number is an address for internal register read.
Notice 3) The commands that upper/lower register settings are demanded are effective at the point of commands input.
But electric volume is effective after upper and lower register setting.
- 53 -
HM17CM256
(34)
INSTRUCTION DESCRIPTION
As shown in instruction table, HM17CM256 has abundant command set.
All the data code and command code are valid only when the chip select signal CS is at “0” state.
The left side of the following command code and data table are the setting of 80 series CPU`
interface.
Do not use undefined command code.
(34-1) Write display data on RAM
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
0
0
1
0
0/1
0/1
0/1
Writing the 8-bit display RAM data at specified X, Y address.
D5
D4
D3
D2
D1
D0
D1
D0
Display RAM write data
(34-2) Read display data from RAM
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
0
0
0
1
0/1
0/1
0/1
Display RAM read data
Reading out the 8-bit display RAM data from specified X, Y address.
One Dummy read cycle is needed after X, Y address is set.
(34-3) X address register set
CS
RS
RD
WR
RE2
RE1
RE0
0
1
1
0
0
0
0
( reset :AX3~AX4=0H, read address :0H )
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
AX3
AX2
AX1
AX0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
*
AX6
AX5
AX4
0
1
1
0
0
0
0
0
( reset :AX6~AX4=0H, read address :1H ) * : “Don’t care”
Setting the X direction address address set. The lower 4-bits are set first, and then upper 3-bits are set later.
Please set from lower bit.
(34-4) Y address register set
CS
RS
RD
WR
RE2
RE1
0
1
1
0
0
0
( reset :AY3~AY0=0H, read address :2H )
CS
RS
RD
WR
RE2
RE1
0
1
1
0
0
0
( reset :AY6~AY4=0H, read address :3H )
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
0
AY3
AY2
AY1
AY0
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
* : “Don’t care”
0
1
1
*
AY6
AY5
AY4
Setting the Y address of display RAM. The lower 4-bits are set first, and then upper 3-bits are set later.
Please set from lower bit.
00H~51H is valid range at Y address(AY6~AY0). Do not use 52H~FFH range. The Y address(AY6~AY0) of
50H,51H is used for ICON display data address.
- 54 -
HM17CM256
(34-5) Display start line register set
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
0
LA3
LA2
LA1
LA0
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
* : “Don’t care”
1
0
1
*
LA6
LA5
LA4
0
1
1
0
0
0
(reset:LA3~LA0=0H, read address:4H)
CS
RS
RD
WR
RE2
RE1
0
1
1
0
0
0
(reset:LA6~LA4=0H, read address:5H)
Setting the line address of COM0. The address stored at the start line register becomes display line at
COM0 line of LCD panel.
The display of LCD panel is done from line address value to the direction of increase.
LA6
LA5
LA4
LA3
LA2
LA1
LA0
Line address
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
:
:
1
0
0
:
:
1
1
1
1
79
(34-6) n line inversion register set
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
0
N3
N2
N1
N0
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
* : “Don’t care”
1
1
1
*
N6
N5
N4
0
1
1
0
0
0
( reset :N3~N0=0H, read address :6H)
CS
RS
RD
WR
RE2
RE1
0
1
1
0
0
0
( reset :N6~N4=0H, read address :7H)
Setting line number to be inversed to register.
Setting range is from 2 to 80.
can be effective only when N line inversion command NLIN=‘1”.
If NLIN=“0”, the polarity of LCD driving voltage is inverted by every other frame.
N line inversion register
N6
N5
N4
N3
N2
N1
N0
Inversion line number
0
0
0
0
0
0
0
Forbidden *
0
0
0
0
0
0
1
2
:
:
1
0
0
1
n=N-1
* : N0~N6 =”0” is forbidden.
:
:
1
1
1
80
- 55 -
HM17CM256
•
Inversion timing
a) when n-line inversion function is OFF(1/82 duty display)
1 line
81 line 82 line 1 line
2 line 3 line
LP
FLM
FR
b) when n-line inversion function is ON
N line control
N line
1 line
2 line
D5
D4
D3
D2
0
1
1
0
0
0
0
1
0
0
( reset :{SHIFT, MON, ALLON, ON/OFF}=0H, read address : 8H)
0
SHIFT
MON
1 line
2 line
3 line
LP
FR
(34-7) display control (1) register set
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D1
D0
ALLON ON/OFF
various control setting of display
a) ON/OFF command
Display ON/OFF control
ON/OFF=”0”: display OFF (all ports are VSS level)
ON/OFF=”1”: display ON
b) ALLON command
Setting display data to “1” with independence of RAM data.
This command has higher priority than
positive display/negative display command. RAM data is not changed.
ALLON=”0”: normal display state
ALLON=”1”: turn on all the pixel
c) MON command
BW display / gradation display selection
MON=”0”: gradation display mode
MON=”1”: BW display mode
d) SHIFT command
Selection of the shift direction of scan data of common driver output
SHIFT=”0”:COM0 COM79 shift
SHIFT=”1”:COM79 COM0 shift
ˆ
ˆ
- 56 -
HM17CM256
(34-8) Display control (2) register set
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
0
0
0
1
( reset :{REV, NLIN, SWAP, REF}=0H, read address :9H )
0
0
1
REV
NLIN
SWAP
REF
various control setting of display
a) REF command
When CPU tries to access display RAM, the relation between X address and write data is changed by
command, normal or headfirst.
The output sequence of display data to segment driver can be controlled by register setting. The IC can
be placed in panel with less constraint at application.
b) SWAP command
When CPU tries to access display RAM, the display data can be swapped.
SWAP=”0”: Normal state, D7~D0 or D15~D0 are written to the RAM.
SWAP=”1”: SWAP mode on : The swapped data of D7~D0 or D15~D0 are written to the RAM.
SWAP=”0”
SWAP=”1”
Write data
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Internal data
d7 d6 d5 d4 d3 d2 d1 d0
d0 d1 d2 d3 d4 d5 d6 d7
Read data
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
c) NLIN command
n line inversion ON/OFF control.
NLIN=”0”: n line inversion OFF. Polarity signal, FR is inverted every other frame.
NLIN=”1”: n line inversion ON. The n lines are inverted according to the contents of n line inversion
register
d) REV command
The relation between RAM data and display data is defined by this command.
REV=”0”: The display data are reflected the RAM data until that time.
REV=”1”: The display data are reflected the opposite data from RAM data.
- 57 -
HM17CM256
(34-9) Increment control register set
CS
RS
RD
WR
RE2
RE1
RE0
D7
0
1
1
0
0
0
0
(reset :{WIN, AIM, AYI, AXI}=0H, read address :AH)
D6
D5
D4
D3
D2
D1
D0
1
0
1
* : ”Don’t care”
0
WIN
AIM
AYI
AXI
Sets the display RAM address to increment mode when RAM data is accessed.
Per RAM write or read access, the increment or non-increment settings of X and Y address counter are
possible by AIM, AYI, AXI register setting.
When accessing consecutive RAM areas by read or write,
the address increment operation is possible without setting the read or write address by this register setting.
After setting the auto increment register, the X, Y address should be set lower bits first.
Please revise X, Y address register after increment register setting.
When WIN register is set to “1”, the CPU accesses specified area of display RAM. In this case X, Y
address should be used with auto increment mode set (AXI=”1”, AYI=”1”). Do not revise X, Y address
register when it is not auto increment mode.
WIN=”0”: normal display RAM access
WIN=”1”: window area access at display RAM
The window to be accessed is defined by setting the start X, Y address and end X, Y address.
When accessing display with window area mode, please set X, Y start address and then X, Y window
end address.
When accessing consecutive RAM area, it is possible to access next location without setting the address
by using this command. X, Y address is unknown after auto increment setting. When WIN register is set
to “1”, the RAM should be accessed after setting start point address and end point address.
And address setting should be done in sequence of start point of X address and Y address, and then
end point of X address and Y address after WIN command setting ( WIN=”1”).
The relationship between AIM, AYI, AXI register and X, Y address increment mode is as follow.
AIM
0
1
notice
notice
Increment timing selection
Both case of writing in and read out display RAM
Only when writing in display RAM( read modify)
Remark
‰
Š
Œ

Ž
This mode is valid when read or write is performed on consecutive RAM location.
This mode is valid when read out consecutive data and modifying the data and then write them in again or
read
write per access.
‹

AYI
0
0
1
1
notice
notice
AXI
0
1
0
1
Increment timing selection
No increment
X address auto increment
Y address auto increment
X, Y address auto increment
Remark

‘
’
“
•
Regardless of AIM setting, no auto increment for X and Y address
According to AIM setting, auto increment only for X address.
”
•
–
And X address is increased as followed loop according to REF register( SEG output direction setting
register ) value.
MaxH
00H
∗) Please refer to
notice
š
›
—
RAM address bitmap
˜
in
™
(10) relation between display RAM and address
According to AIM setting, auto increment only for Y address
Y address is increased as followed loop regardless of REF register.
- 58 -
˜
HM17CM256
51H
00H
notice
œ

According to AIM setting, auto increment for X and Y address
X address is increased to MaxH first and then Y address is increased later.
You should set X address, Y address in sequence, anything else is forbidden.
MaxH
00H
X
∗) Please refer to
ž
51H
00H
address
Y address
RAM address bitmap
Ÿ
in
ž
(10) relation between display RAM and address
And when X, Y auto increment mode operating, window access is possible.
selected ( WIN =”1” ), address is increased as following loop.
START
Address
X
END
Address
address
START
Address
Y
Ÿ
When window mode is
END
Address
address
a) 8 bit access mode
The increment operating is as above description.
b) 16 bit access mode
Two-byte access is done by single RAM access.
Address is increased after access.
X address is increased as (00H, 01H,
3EH, 3FH) sequence.
- 59 -
HM17CM256
(34-10) Power control register set
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
0
0
0
1
0
( reset :{AMPON, HALT, DCON, ACL}=0H
read address :BH )
1
1
AMPON
HALT
DCON
ACL
¡
a) ACL command
This command initializes internal circuit and it is valid only at master operating.
ACL=”0”: normal state
ACL=”1”: initialization ON
Just after the execution of ACL command (ACL=”1”), D0 bit is set to 1.
But as the initialization process
goes on internally, D0 is reset to “0”.
When ACL command is executed, internal reset signal is produced by using local display clock ( clock
from internal oscillator or from external resistor oscillation mode ).
So, after ACL command is executed, it needs to WAIT at least 2 period of the clock for next process
beginning.
ACL command is effective only at master mode operation because it uses original oscillator clock.
It is prohibited for slave mode operation to use the internal oscillator or external oscillator.
So, ACL command is impossible at slave mode. Please reset the slave device at RES terminal, when
needed.
b) DCON command
ON/OFF the internal voltage boosting circuit.
DCON=”0”: boosting circuit OFF
DCON=”1”: boosting circuit ON
c) HALT command
Power save mode ON/OFF control
HALT=”0”: normal state
HALT=”1”: power save state
The power consumption is decreased near static current at power save mode.
States of each sub-block in power save mode are as follow.
•
•
•
•
•
•
Oscillator, built-in power supply block stop.
Stop driving LCD panel, segment drive, the outputs of common driver are all set to VSS level.
Clock input from OSC1 port is disabled.
Display RAM data are conserved.
Operational modes are preserved as those before power save command was executed.
VLCD, V1 ~ V4 become high impedance state.
Make display OFF state before power save mode by HALT command.
And when returning from power save mode, you should display ON after oscillator, power circuit is
activated stably.
After display OFF and HALT command, if the display is turned ON before oscillator and power circuit is
not activated stably, wrong display can be appeared.
d) AMPON command
ON/OFF the internal OP. amplifier circuit of power block (voltage regulator block, electric volume,
voltage converting circuit ).
AMPON=”0”:
AMPON=”1”:
- 60 -
internal power circuit OP. Amplifier OFF
internal power circuit OP. Amplifier ON
HM17CM256
(34-11) LCD duty set
CS
RS
RD
WR
0
1
1
0
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
1
0
0
*
DS2
DS1
DS0
( reset :{DS2, DS1, DS0}=0H read address :CH) *:”Don’t care”
¢
LCD display duty setting
DS2
0
0
0
0
1
1
1
1
DS1
0
0
1
1
0
0
1
1
DS0
0
1
0
1
0
1
0
1
duty
Y direction 80 dot width display, 1/82 duty
Y direction 75 dot width display, 1/77 duty
Y direction 64 dot width display, 1/66 duty
Y direction 45 dot width display, 1/47 duty
Y direction 30 dot width display, 1/32 duty
Y direction 15 dot width display, 1/17 duty
Y direction 36 dot width display, 1/38 duty
Y direction 24 dot width display, 1/26 duty
Partial display is possible by setting duty operation.
- 61 -
HM17CM256
(34-12) Boosting coefficient setting
CS
RS
RD
WR
0
1
1
0
( reset :{VU2~VU0}=0H
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
1
0
1
*
VU2
VU1
VU0
read address :DH) * : ”Don’t care”
£
coefficient setting of boosting circuit
VU2
0
0
0
0
1
1
1
1
VU1
0
0
1
1
0
0
1
1
VU0
Boosting multiple
0
No boosting *
1
2 times boosting operation
0
3 times boosting operation
1
4 times boosting operation
0
5 times boosting operation
1
6 times boosting operation
0
7 times boosting operation
1
forbidden
*VREG amplifier gain is 1.
(34-13) Bias setting register
CS
RS
RD
0
1
1
( reset :{B2~B0}=0H
£
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
1
1
0
*
B2
B1
B0
read address : EH) * : ”Don’t care”
The bias ratio is selected by this register.
and B0 register.
B2
0
0
0
0
1
1
1
1
B1
0
0
1
1
0
0
1
1
B0
0
1
0
1
0
1
0
1
1/10, 1/9, 1/8, 1/7, 1/6, 1/5 biases can be selected by B2, B1
bias
Operating under 1/9 bias
Operating under 1/8 bias
Operating under 1/7 bias
Operating under 1/6 bias
Operating under 1/5 bias
Operating under 1/10 bias
forbidden
forbidden
(34-14) RE flag state register setting.
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
0/1
0/1
0/1
1
( reset :{TST0, RE2, RE1, RE0}=0H read address :FH)
1
1
1
TST0
RE2
RE1
RE0
¤
Setting the register of command extension register(RE2, RE1, RE0).
When accessing command
register, the extension register corresponding flag should be set first, and then access it. The TST0
register is that for test, and so please set to “0”.
- 62 -
HM17CM256
(34-15) Gradation palette register setting
CS
RS
RD
0
1
1
(read address :0H)
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
0
0
0
0
PA03
PA02
PA01
PA00
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
1
*
*
*
PA04
0
1
1
0
0
0
( read address :1H) *:”Don’t care”
(reset :PA04~PA00=”00000”)
CS
RS
RD
0
1
1
( read address :2H)
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
0
0
1
0
PA13
PA12
PA11
PA10
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
1
*
*
*
PA14
0
1
1
0
0
0
( read address :3H) * : ”Don’t care”
( reset :PA14~PA10=”00101”)
CS
RS
RD
0
1
1
( read address :4H)
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
0
1
0
0
PA23
PA22
PA21
PA20
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
*
*
*
PA24
0
1
1
0
0
0
( read address:5H) * : “Don’t care”
( reset :PA24~PA20=”01010”)
CS
RS
RD
0
1
1
( read address : 6H)
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
0
1
1
0
PA33
PA32
PA31
PA30
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
1
*
*
*
PA34
0
1
1
0
0
0
( read address : 7H) * : “Don’t care”
( reset : PA34~PA30=”01110”)
CS
RS
RD
0
1
1
( read address :8H)
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
1
0
0
0
PA43
PA42
PA41
PA40
- 63 -
HM17CM256
CS
RS
RD
WR
RE2
RE1
0
1
1
0
0
0
( read address :9H) * : “Don’t care”
( reset :PA44~PA40=”10001”)
CS
RS
RD
0
1
1
( read address :AH)
CS
RS
RD
RS
RD
0
1
1
( read address :CH)
CS
RS
RD
RS
RD
0
1
1
( read address :0H)
CS
RS
RD
RS
RD
0
1
1
( read address :2H)
CS
RS
RD
D4
D3
D2
D1
D0
1
1
0
0
1
*
*
*
PA44
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
1
0
1
0
PA53
PA52
PA51
PA50
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
1
1
*
*
*
PA54
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
1
1
0
0
PA63
PA62
PA61
PA60
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
1
*
*
*
PA64
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
0
0
0
0
PA73
PA72
PA71
PA70
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
*
*
*
PA74
D3
D2
D1
D0
WR
RE2
RE1
RE0
D7
D6
D5
D4
0
0
1
0
0
0
1
0
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
1
*
*
*
PB04
0
1
1
0
0
1
( read address :3H) * : “Don’t care”
( reset :PB04~PB00=”00000”)
- 64 -
D5
RE1
0
1
1
0
0
1
( read address :1H) * : “Don’t care”
( reset :PA74~PA70=”11111”)
CS
D6
RE2
0
1
1
0
0
0
( read address :DH) * : “Don’t care”
( reset :PA64~PA60=”11010”)
CS
D7
WR
0
1
1
0
0
0
( read address :BH) * : “Don’t care”
( reset :PA54~PA50=”10101”)
CS
RE0
PB03 PB02 PB01 PB00
HM17CM256
CS
RS
RD
0
1
1
( read address :4H)
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D5
D4
0
0
1
0
0
1
0
0
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
0
0
1
0
1
0
1
1
0
0
1
( read address :5H) * : “Don’t care”
( reset :PB14~PB10=”00101”)
CS
RS
RD
0
1
1
( read address :6H)
CS
RS
RD
RS
RD
0
1
1
( read address :8H)
CS
RS
RD
RS
RD
0
1
1
( read address :AH)
CS
RS
RD
RS
RD
0
1
1
( read address :CH)
D0
PB11
PB10
D2
D1
D0
*
*
*
PB14
D3
D2
D1
D0
PB13 PB12
RE1
RE0
D7
D6
D5
D4
0
0
1
0
0
1
1
0
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
1
*
*
*
PB24
D3
D2
D1
D0
PB23 PB22 PB21 PB20
WR
RE2
RE1
RE0
D7
D6
D5
D4
0
0
1
0
1
0
0
0
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
*
*
*
PB34
D3
D2
D1
D0
PB33 PB32 PB31 PB30
WR
RE2
RE1
RE0
D7
D6
D5
D4
0
0
1
0
1
0
1
0
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
*
*
*
PB44
D3
D2
D1
D0
0
1
1
0
0
1
( read address :BH) * : “Don’t care”
( reset :PB44~PB40=”10001”)
CS
D1
RE2
0
1
1
0
0
1
( read address :9H) * : “Don’t care”
( reset :PB34~PB30=”01110”)
CS
D2
WR
0
1
1
0
0
1
( read address :7H) * : “Don’t care”
( reset :PB24~PB20=”01010”)
CS
D3
WR
RE2
RE1
RE0
D7
D6
D5
D4
0
0
1
0
1
1
0
0
PB43 PB42 PB41 PB40
PB53 PB52 PB51 PB50
- 65 -
HM17CM256
CS
RS
RD
WR
RE2
RE1
0
1
1
0
0
1
( read address :DH) * : “Don’t care”
( reset :PB54~PB50=”10101”)
CS
RS
RD
0
1
1
( read address :0H)
CS
RS
RD
RS
RD
0
1
1
( read address :2H)
CS
RS
RD
RS
RD
0
1
1
( read address :4H)
CS
RS
RD
RS
RD
0
1
1
( read address :6H)
CS
RS
RD
D4
D3
D2
D1
D0
0
1
1
0
1
*
*
*
PB54
D3
D2
D1
D0
RE0
D7
D6
D5
D4
0
0
1
1
0
0
0
0
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
1
*
*
*
PB64
D3
D2
D1
D0
PB63 PB62 PB61 PB60
WR
RE2
RE1
RE0
D7
D6
D5
D4
0
0
1
1
0
0
1
0
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
1
*
*
*
PB74
D3
D2
D1
D0
PB73 PB72 PB71 PB70
WR
RE2
RE1
RE0
D7
D6
D5
D4
0
0
1
1
0
1
0
0
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
1
*
*
*
PC04
D3
D2
D1
D0
PC03 PC02 PC01 PC00
WR
RE2
RE1
RE0
D7
D6
D5
D4
0
0
1
1
0
1
1
0
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
1
*
*
*
PC14
0
1
1
0
0
1
( read address :7H) * : “Don’t care”
( reset :PC14~PC10=”00101”)
- 66 -
D5
RE1
0
1
1
0
0
1
( read address :5H) * : “Don’t care”
( reset :PC04~PC00=”00000”)
CS
D6
RE2
0
1
1
0
0
1
( read address :3H) * : “Don’t care”
( reset :PB74~PB70=”11111”)
CS
D7
WR
0
1
1
0
0
1
( read address :1H) * : “Don’t care”
( reset :PB64~PB60=”11010”)
CS
RE0
PC13 PC12 PC11 PC10
HM17CM256
CS
RS
RD
0
1
1
( read address :8H)
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D5
D4
0
0
1
1
1
0
0
0
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
0
1
*
*
*
PC24
D3
D2
D1
D0
0
1
1
0
0
1
( read address :9H) * : “Don’t care”
( reset :PC24~PC20=”01010”)
CS
RS
RD
0
1
1
( read address :AH)
CS
RS
RD
RS
RD
0
1
1
( read address :CH)
CS
RS
RD
RS
RD
0
1
1
( read address :0H)
CS
RS
RD
RS
RD
0
1
1
( read address :2H)
D0
PC23 PC22 PC21 PC20
RE1
RE0
D7
D6
D5
D4
0
0
1
1
1
0
1
0
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
1
1
*
*
*
PC34
D3
D2
D1
D0
PC33 PC32 PC31 PC30
WR
RE2
RE1
RE0
D7
D6
D5
D4
0
0
1
1
1
1
0
0
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
0
1
*
*
*
PC44
D3
D2
D1
D0
PC43 PC42 PC41 PC40
WR
RE2
RE1
RE0
D7
D6
D5
D4
0
1
0
0
0
0
0
0
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
1
*
*
*
PC54
D3
D2
D1
D0
0
1
1
0
1
0
( read address :1H) * : “Don’t care”
( reset :PC54~PC50=”10101”)
CS
D1
RE2
0
1
1
0
0
1
( read address :DH) * : “Don’t care”
( reset :PC44~PC40=”10001”)
CS
D2
WR
0
1
1
0
0
1
( read address :BH) * : ”Don’t care”
( reset :PC34~PC30=”01110”)
CS
D3
WR
RE2
RE1
RE0
D7
D6
D5
D4
0
1
0
0
0
0
1
0
PC53 PC52 PC51 PC50
PC63 PC62 PC61 PC60
- 67 -
HM17CM256
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
1
1
*
*
*
PC64
D3
D2
D1
D0
0
1
1
0
1
0
( read address :3H) * : “Don’t care”
( reset :PC64~PC60=”11010”)
CS
RS
RD
0
1
1
( read address :4H)
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D5
D4
0
1
0
0
0
1
0
0
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
0
1
*
*
*
PC74
0
1
1
0
1
0
( read address :5H) * : “Don’t care”
( reset :PC74~PC70=”11111”)
Setting each gradation palette.
PC73 PC72 PC71 PC70
The gradation level is selected among 32 level.
GRADATION LEVEL TABLE
Palette value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
- 68 -
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Gradation
level
0
1/31
2/31
3/31
4/31
5/31
6/31
7/31
8/31
9/31
10/31
11/31
12/31
13/31
14/31
15/31
Remarks
Initial value of palette 0
Initial value of palette 1
Initial value of palette 2
Initial value of palette 3
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
( palette Aj, palette Bj, palette Cj (j=0~7) 3 kinds )
Gradation
Palette value
remarks
level
0 0 0 0
16/31
0 0 0 1
17/31
Initial value of palette 4
0 0 1 0
18/31
0 0 1 1
19/31
0 1 0 0
20/31
0 1 0 1
21/31
Initial value of palette 5
0 1 1 0
22/31
0 1 1 1
23/31
1 0 0 0
24/31
1 0 0 1
25/31
1 0 1 0
26/31
Initial value of palette 6
1 0 1 1
27/31
1 1 0 0
28/31
1 1 0 1
29/31
1 1 1 0
30/31
1 1 1 1
31/31
Initial value of palette 7
HM17CM256
(34-16) Display start command set
CS
RS
RD
WR
RE2
RE1
RE0
0
1
1
0
1
0
0
( reset :{SC2, SC1, SC0}=0H, read address :6H)
D7
D6
D5
D4
D3
D2
D1
D0
0
1
* : “Don’t care”
1
0
*
SC2
SC1
SC0
Setting the scan start output of common driver.
SC2
SC1 SC0
SHIFT=0 starting point of COM.
0
0
0
COM0~
0
0
1
COM15~
0
1
0
COM30~
0
1
1
COM45~
1
0
0
COM60~
1
0
1
COM75~
1
1
0
forbidden
1
1
1
forbidden
SHIFT=0:COM increasing direction scanning
SHIFT=1:COM decreasing direction scanning
SHIFT=1 starting point of COM.
COM79~
COM64~
COM49~
COM34~
COM19~
COM4~
forbidden
forbidden
(34-17) Serial extension CS control
CS
RS
RD
WR
RE2
RE1
0
1
1
0
1
0
( reset :{EXCS}=1H, read address :7H)
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
* : “Don’t care”
1
1
1
*
*
*
EXCS
D1
D0
*
*
Controlling the output of extension CS at serial interface application.
EXCS pin is I/O pin and used as output at master mode device thus can be controlled.
EXCS=”0”:EXCS pin output is set to “L”.
EXCS=”1”:EXCS pin output is set to “H”.
(34-18) display selection control
CS
RS
RD
WR
0
1
1
0
( reset :{PWM, GLSB}=0H,
RE2
RE1
RE0
1
0
0
read address :8H)
D7
D6
D5
D4
1
0
* : “Don’t care”
0
0
D3
D2
PWM GLSB
a) GLSB command
The segment driver outputs corresponding to 4 gradation display actually uses 3 bit data to select 4
gradation levels out of 8 gradation levels, 2 bit data out of RAM area and 1 bit out of Gradation LBS.
This command sets the supplement 1 bit Gradation LSB ( GLSB ) register.
GLSB=”0”: Set the LSB of segment driver corresponding to 4-gradataion display to “0”.
GLSB=”1”: Set the LSB of segment driver corresponding to 4 gradataion display to “1”.
b) PWM command
Selection gradation display mode.
PWM=”0”: Gradation mode is selected variable 8 gradation among 32 levels.
PWM=”1”: Fixed 8 gradation display mode.
- 69 -
HM17CM256
(34-19) RAM data length setting
CS
RS
RD
WR
RE2
RE1
0
1
1
0
1
0
( reset :{WLS}=0H, read address :9H)
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
* : “Don’t care”
0
0
1
*
*
CKS
WLS
WLS: Selection 8 bit access or 16 bit access at RAM access. Access with 16 bits data length is effective
only at RAM access. The other accesses are 8 bits access ( command access ).
WLS=”0”: RAM access is done by 8 bits data length.
WLS=”1”: RAM access is done by 16 bits data length
CKS: Selection the oscillator.
CKS=”0”: internal oscillation mode ( default ).
Internal oscillation mode should be used under condition of OSC1 and OSC2 open.
CKS=”1”: external oscillation mode.
External oscillation mode should be used under the condition of clock input by OSC1 port or resistor
connection between OSC1 and OSC2 port.
(34-20) Electric volume registers setting.
CS
RS
RD
0
1
1
( read address :AH)
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
0
1
0
1
0
DV3
DV2
DV1
DV0
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
0
1
1
*
DV6
DV5
DV4
0
1
1
0
1
0
( read address :BH) * : “Don’t care”
( reset :DV6~DV0=00H)
Setting the electric volume code.
The voltage range is divided into 127 levels by this register
DV6 DV5 DV4 DV3 DV2 DV1 DV0
Output voltage
0
0
0
0
0
0
0
low
0
0
0
0
0
0
1
:
:
:
:
:
1
1
1
1
1
1
0
:
1
1
1
1
1
1
1
high
The output voltage of VREG is determined by Eq.
¥
.
VREG = VREF x N
(N: booster coefficient)
N=1 under the condition of boosting operation is not valid (booster coefficient register, VU=0H ).
¦
¦
¦
¦
§
The LCD driving voltage VLCD is decided by VREG level or electric volume value (Eq.
VLCD = 0.5 x VREG + M x (VREG - 0.5VREG) / 127
( M : DV6~DV0 register value )
©
©
©
©
¨
).
¨
To prevent over voltage from being generated by electric volume setting, when the register value is set
to upper side of electric volume, voltage level is not changed immediately.
When the register value is set to lower side of electric volume, the voltage level is changed instantly.
- 70 -
HM17CM256
(34-21) Oscillator circuit Rf control
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
0
1
FFL
Rf2
Rf1
Rf0
0
1
1
0
0
0
0
( reset {FFL, Rf2, Rf1, Rf0}=0H, read address : DH)
ª
The feedback resistance of oscillator circuit can be changed by setting this register.
The frame frequency is changed according to the frequency of oscillator, and the oscillation frequency is
determined by the resistor value.
When you set the frame rate, please check the state of LCD display.
Rf 2
0
0
0
0
1
1
1
1
Rf 1
0
0
1
1
0
0
1
1
Rf 0
0
1
0
1
0
1
0
1
Feedback resistance size
Reference value
0.8 x reference value
0.9 x reference value
1.1 x reference value
1.2 x reference value
forbidden
forbidden
forbidden
FFL command Setting oscillator frequency ( frame frequency fFLM). ( refer to DC characteristic )
FFL=0
normal oscillator frequency ( set frame frequency, fFLM to 73Hz(Typ))
FFL=1
high speed oscillator frequency ( set frame frequency, fFLM to 150Hz(Typ))
* The value of typical frame frequency fFLMTyp is under following condition.
• Display mode : variable gradation display
• 1/82 Duty
• {Rf2, Rf1, Rf0}=0H
«
«
«
(34-22) Discharge control
CS
RS
0
( reset
¬
RD
WR
RE2
1
1
0
1
{DIS}=0H, read address
¬
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
1
0
*
*
*
DIS
EH) * : “Don’t care”
The capacitors connected between VLCD~V4 and VSS can be discharged by this control.
to capacitor setting example.
DIS=”0”
discharge stop
DIS=”1” start discharge
Please refer
­
­
- 71 -
HM17CM256
(34-23) Set read address of internal register
CS
RS
RD
WR
RE2
0
1
1
0
1
( reset :{RA3, RA2, RA1, RA0}=BH)
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
1
0
0
RA3
RA2
RA1
RA0
Before executing the internal register data read command the address of register should be specified
first. For example, when display control (1) is being read out, { RA3, RA2, RA1, RA0 } = 8H should be
specified first.
Because selected register is corresponded with RE flag, please set RE flag first and then read out the
register.
Refer to the command function description and the lists of commands for the address of each register.
(34-24) Internal register data read
CS
RS
RD
0
1
1
* : “Don’t care”
WR
RE2
RE1
RE0
D7
D6
D5
D4
0
0/1
0/1
0/1
*
*
*
*
This command is used to read out internal register data.
the address for internal register to read should be set first.
D3
D2
D1
D0
Internal register data read
Before executing this command, RE flag and
(34-25) Window end X address set
CS
RS
RD
WR
RE2
RE1
0
1
1
0
1
0
( reset :{EX3~EX0}=0H, read address :0H)
CS
RS
RD
WR
RE2
RE1
0
1
1
0
1
0
( reset :{EX6~EX4}=0H, read address :1H)
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
0
0
EX3
EX2
EX1
EX0
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
1
*
EX6
EX5
EX4
1
0
* : “Don’t care”
When the window area of RAM is specified(WIN=“1”) to access, the end X address of the window is set
by this command. The lower 4 bits of address should be set first and then upper 3 bits are set later
(34-26) Window end Y address set
CS
RS
RD
WR
RE2
RE1
0
1
1
0
1
0
( reset :{EY3~EY0}=0H, read address :2H)
CS
RS
RD
WR
RE2
RE1
0
1
1
0
1
0
( reset :{EY6~EY4}=0H, read address :3H)
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
0
1
0
EY3
EY2
EY1
EY0
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
*
EY6
EY5
EY4
1
0
* : “Don’t care”
When window area of RAM is specified(WIN=“1”) to access , the end Y address of the window is set by
this command.
The lower 4 bits of address should be set first and then upper 3 bits are set later.
- 72 -
HM17CM256
(34-27) Line inversion start address set
CS
RS
RD
WR
RE2
RE1
0
1
1
0
1
0
( reset :{LS3~LS0}=0H, read address :4H)
CS
RS
RD
WR
RE2
RE1
0
1
1
0
1
0
( reset :{LS6~LS4}=0H, read address :5H)
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
0
0
LS3
LS2
LS1
LS0
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
*
LS6
LS5
LS4
1
0
* : “Don’t care”
When the start address of negative display is set on, it is set by this command.
The lower 4 bits of
address should be set first and then upper 3 bits are set later. The possible range is LS=00H~4FH .
The other values are forbidden. Please set the value under the condition, LS≤LE.
(34-28) Line inversion end address set
CS
RS
RD
WR
RE2
RE1
0
1
1
0
1
0
( reset :{LE3~LE0}=0H, read address :6H)
CS
RS
RD
WR
RE2
RE1
0
1
1
0
1
0
( reset :{LE6~LE4}=0H, read address :7H)
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
0
1
1
0
LE3
LE2
LE1
LE0
RE0
D7
D6
D5
D4
D3
D2
D1
D0
1
1
1
*
LE6
LE5
LE4
1
0
* : “Don’t care”
When the end address of negative display is set on, it is set by this command.
The lower 4 bits of
address should be set first and then upper 3 bits are set later.
The possible range is LS=00H~4FH . The other values are forbidden. Please set the value under the
condition, LS≤LE.
(34-29) Line inversion control
CS
RS
RD
WR
RE2
RE1
RE0
0
1
1
0
1
0
1
( reset :{PSC, BT, LREV}=0H, read address :8H)
D7
D6
1
0
* : “Don’t care”
D5
D4
D3
D2
D1
D0
0
0
*
*
BT
LREV
Setting the status of line inversion display tone.
LREV command : line inversion display ON/OFF setting.
LREV=”0”: normal display
LREV=”1”: line inversion display ON. The area specified by line inversion start/stop address is
blinked.
The blink type display is controlled by BT command.
When line inversion display is ON(LREV=”1”), line inversion start address(LSi) and line inversion stop
address(LEi) should be set as following condition.
LSi ≤ LEi - (1)
And following condition is forbidden.
LEi < LSi - (2)
- 73 -
HM17CM256
BT command : inversion timing selection at line inversion display
BT=”0”: Negative tone display in specified area
BT=”1”: The image of specified area is blinked by every 32 frame.
®
¯
¯
¯
°
¯
°
°
°
¯
°
¯
¯
¯
°
¯
°
°
°
¯
°
¯
¯
¯
°
¯
°
°
°
¯
°
°
°
°
°
¯
¯
¯
¯
¯
°
¯
¯
¯
°
¯
°
°
°
¯
°
¯
¯
¯
°
¯
°
°
°
¯
°
¯
¯
¯
°
¯
°
°
°
¯
¯
¯
¯
¯
¯
°
°
°
°
°
Changes per
every 32 frame.
Display example (BT=”1”)
And be cautious that LREV and BT commands have no influence on dummy segment driver circuit.
And the image selected by COMI0, COMI1 is excluded.
HYUNDAI
LCD DRIVER
Low Power and
Low Voltage
Changes per
every 32 frame.
HYUNDAI
LCD DRIVER
Low Power and
Low Voltage
line inversioin start address
line inversioin end address
²
²
Line inversion display example (LREV=”1”,BT=”1”)
(34-30) Dummy segment driver address selection ( Refer to dummy segment drive related description. )
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
D5
D4
D3
D2
D1
D0
0
1
1
0
1
0
1
1
0
0
1
*
*
*
DMY
( reset :{DMY}=0H, read address :8H) * : “Don’t care”
When data is to be written to dummy segment driver, this register is active (DMY=”1”).
DMY=”0”: normal display RAM access
DMY=”1”: display data access to dummy segment driver
Normal segment drivers acquire display data from display RAM, but dummy segment drivers acquire
display data from corresponding register not from display RAM.
The capacity of register is 4 bytes.
That is correspond to SEGSA0~SEGSA3 SEGSB0~SEGSB3 SEGSC0~SEGSC3 output.
±
±
When accessing with DMY = “1”, address setting is valid by only X address. There is 4 byte capacity,
and so 00H, 01H, 02H, 03H is valid at 8 bits mode and 00H, 01H is valid at 16 bits mode. There is no
- 74 -
HM17CM256
relation with Y address setting value.
To access with DMY = “1”, register data write-in is possible with increment mode.
(34-31) PWM mode control
CS
RS
RD
WR
RE2
RE1
RE0
D7
D6
0
1
1
0
1
0
1
1
0
( reset :{PWMS, PWMA, PWMB, PWMC}=0H, read address :8H)
D5
D4
D3
D2
D1
D0
1
0 PWMS PWMA PWMB PWMC
* : “Don’t care”
PWM mode selection. ( Refer to following wave diagram. )
PWMS=”0”: Selection PWM type1.
PWMA, PWMB, PWMC=”0” : PWM type1-O is selectable for each A, B, C data.
PWMA, PWMB, PWMC=”1” : PWM type1-E is selectable for each A, B, C data.
PWMS=”1”: Selection PWM type2.
a) PWM type1 (PWMS=”0”)
“H”
CL
odd line
even line
“L”
VLCD
³
Type-O
´
V2
SEG
VLCD
µ
Type-E
´
V2
b) PWM type2 (PWMS=”1”)
CL
“H”
“L”
SEG
VLCD
µ
µ
V2
- 75 -
HM17CM256
(35) Relation between each setting and COM / display RAM
The COM port number corresponds to Y address of display RAM by SHIFT command, LCD duty
command, common display start position command and display start line setting command.
•
When display start address was set to “0”.
According to LCD duty and display start common line address, the port of COM line and
display RAM address ( MY ) is changed by 15 line unit.
When SHIFT register is set to “0” common line shift to upward direction, and when the value is
“1”, common line shift to downward direction.
When display start address (LA6~LA0) is set to
“0”, the “MY” corresponds to starting position is “0”.
The MY shift upward direction as display
goes on.
In any case, COMI0=MY80, COMI1=MY81 .
•
When display start line was set except for “0”
According to LCD duty and display start common line address, the port of COM line and
display RAM address, MY is changed by 15 line unit.
When SHIFT register is set to “0” common line shift to upward direction, and when the value is
“1”, common line shift to downward direction.
When display start address (LA6~LA0) is set to
except for “0”, the “MY” corresponds to starting position is shift by the amount of set value.
The MY shift upward direction as display goes on but MY is set to “0” after MY=79.
In any case, COMI0=MY80, COMI1=MY81 .
- 76 -
HM17CM256
¶
display start line set to “0” , 1/82 duty by DS2~DS0 register
SHIFT set value
DS2
DS1
DS0
SC2
SC1
SC0
LA6
LA0
·
COMI0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
·
·
·
·
·
·
“000”
·
80
0
SHIFT=”0” (common forward scan)
“000” (1/82 duty)
“001”
“010”
“011”
“100”
“0000000” (display start point 0)
80
65
80
50
80
35
80
20
“101”
“000”
80
5
80
79
SHIFT=”1” (common backward scan)
“000” (1/82 duty)
“001”
“010”
“011”
“100”
“0000000” (display start point 0)
80
64
80
49
80
34
80
19
“101”
80
4
0
79
79
0
0
79
79
0
0
79
79
0
0
79
79
0
0
79
79
0
79
81
64
81
49
81
34
81
19
81
4
81
0
81
65
81
50
81
35
81
20
81
5
81
The number on the table means MY ( Y direction shift address ).
The COM electrodes without MY number are driving with non-selection level signal.
The
Marked line is display start line.
- 77 -
HM17CM256
¸
display start line set to “0” , 1/77 duty by DS2~DS0 register
SHIFT set value
DS2
DS1
DS0
SC2
SC1
SC0
LA6
LA0
¹
COMI0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
¹
¹
¹
¹
¹
¹
“000”
¹
80
0
SHIFT=”0” (common forward scan)
“001” (1/77 duty)
“001”
“010”
“011”
“100”
“0000000” (display start point 0)
80
65
80
50
80
35
80
20
“101”
“000”
80
5
80
SHIFT=”1” (common backward scan)
“001” (1/77 duty)
“001”
“010”
“011”
“100”
“0000000” (display start point 0)
80
64
80
49
80
19
80
4
0
74
74
74
0
0
74
74
0
0
74
74
0
0
74
74
0
0
74
74
74
0
81
64
81
49
81
34
81
19
81
4
81
0
81
65
81
50
81
The number on the table means MY ( Y direction shift address ).
The COM electrodes without MY number are driving with non-selection level signal.
The
Marked line is display start line.
- 78 -
80
34
“101”
35
81
20
81
5
81
HM17CM256
º
display start line set to “0” , 1/66 duty by DS2~DS0 register
SHIFT set value
DS2
DS1
DS0
SC2
SC1
SC0
LA6
LA0
»
COMI0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
»
»
»
»
»
»
“000”
»
80
0
SHIFT=”0” (common forward scan)
“010” (1/66 duty)
“001”
“010”
“011”
“100”
“0000000” (display start point 0)
80
80
50
80
35
80
20
“101”
“000”
80
5
80
SHIFT=”1” (common backward scan)
“010” (1/66 duty)
“001”
“010”
“011”
“100”
“0000000” (display start point 0)
80
80
49
80
34
80
19
“101”
80
4
63
0
63
0
63
0
63
63
0
0
63
63
0
0
63
63
0
63
0
63
0
63
81
81
49
81
34
81
19
81
4
81
0
81
81
50
81
35
81
20
81
5
81
The number on the table means MY ( Y direction shift address ).
The COM electrodes without MY number are driving with non-selection level signal.
The
Marked line is display start line.
- 79 -
HM17CM256
¼
display start line set to “0” , 1/47 duty by DS2~DS0 register
SHIFT set value
DS2
DS1
DS0
SC2
SC1
SC0
LA6
LA0
½
COMI0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
½
½
½
½
½
½
“000”
½
80
0
SHIFT=”0” (common forward scan)
“011” (1/47 duty)
“001”
“010”
“011”
“100”
“0000000” (display start point 0)
80
80
80
35
80
20
“101”
“000”
80
5
80
SHIFT=”1” (common backward scan)
“011” (1/47 duty)
“001”
“010”
“011”
“100”
“0000000” (display start point 0)
80
80
80
19
80
4
0
44
44
0
0
44
44
0
0
44
44
44
44
0
0
44
44
0
0
44
44
0
81
81
81
34
81
19
81
4
81
0
81
81
81
The number on the table means MY ( Y direction shift address ).
The COM electrodes without MY number are driving with non-selection level signal.
The
Marked line is display start line.
- 80 -
80
34
“101”
35
81
20
81
5
81
HM17CM256
¾
display start line set to “0” , 1/32 duty by DS2~DS0 register
SHIFT set value
DS2
DS1
DS0
SC2
SC1
SC0
LA6
LA0
¿
COMI0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
¿
¿
¿
¿
¿
¿
“000”
¿
80
0
SHIFT=”0” (common forward scan)
“100” (1/32 duty)
“001”
“010”
“011”
“100”
“0000000” (display start point 0)
80
80
80
80
20
“101”
“000”
80
5
80
SHIFT=”1” (common back scan)
“100” (1/32 duty)
“001”
“010”
“011”
“100”
“0000000” (display start point 0)
80
80
80
80
19
“101”
80
4
0
29
29
0
0
29
29
29
0
0
29
29
0
0
29
29
29
0
0
29
29
0
81
81
81
81
19
81
4
81
0
81
81
81
81
20
81
5
81
The number on the table means MY ( Y direction shift address ).
The COM electrodes without MY number are driving with non-selection level signal.
The
Marked line is display start line.
- 81 -
HM17CM256
À
display start line set to “0” , 1/17 duty by DS2~DS0 register
SHIFT set value
DS2
DS1
DS0
SC2
SC1
SC0
LA6
LA0
Á
COMI0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
Á
Á
Á
Á
Á
Á
“000”
Á
80
0
SHIFT=”0” (common forward scan)
“101” (1/17 duty)
“001”
“010”
“011”
“100”
“0000000” (display start point 0)
80
80
80
80
“101”
“000”
80
5
80
SHIFT=”1” (common backward scan)
“101” (1/17 duty)
“001”
“010”
“011”
“100”
“0000000” (display start point 0)
80
80
80
80
4
0
14
14
14
0
0
14
14
0
0
14
14
0
0
14
14
0
0
14
14
14
0
81
81
81
81
81
4
81
0
81
81
81
The number on the table means MY ( Y direction shift address ).
The COM electrodes without MY number are driving with non-selection level signal.
The
Marked line is display start line.
- 82 -
80
“101”
81
81
5
81
HM17CM256
Â
display start line set to “0” , 1/38 duty by DS2~DS0 register
SHIFT set value
DS2
DS1
DS0
SC2
SC1
SC0
LA6
LA0
Ã
COMI0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
Ã
Ã
Ã
Ã
Ã
Ã
“000”
Ã
80
0
SHIFT=”0” (common forward scan)
“110” (1/38 duty)
“001”
“010”
“011”
“100”
“0000000” (display start point 0)
80
80
80
35
80
20
“101”
“000”
80
5
80
SHIFT=”1” (common backward scan)
“110” (1/38 duty)
“001”
“010”
“011”
“100”
“0000000” (display start point 0)
80
80
80
34
80
19
“101”
80
4
0
35
0
35
0
35
0
35
0
35
35
0
0
35
35
0
0
35
35
0
81
81
81
34
81
19
81
4
81
0
81
81
81
35
81
20
81
5
81
The number on the table means MY ( Y direction shift address ).
The COM electrodes without MY number are driving with non-selection level signal.
The
Marked line is display start line.
- 83 -
HM17CM256
Ä
display start line set to “0” , 1/26 duty by DS2~DS0 register
SHIFT set value
DS2
DS1
DS0
SC2
SC1
SC0
LA6
LA0
Å
COMI0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
Å
Å
Å
Å
Å
Å
“000”
Å
80
0
SHIFT=”0” (common forward scan)
“111” (1/26 duty)
“001”
“010”
“011”
“100”
“0000000” (display start point 0)
80
80
80
80
20
“101”
“000”
80
5
80
SHIFT=”1” (common backward scan)
“111” (1/26 duty)
“001”
“010”
“011”
“100”
“0000000” (display start point 0)
80
80
80
19
80
4
23
0
23
0
23
0
23
23
0
0
23
23
0
0
23
23
0
23
0
23
0
23
81
81
81
81
19
81
4
81
0
81
81
81
The number on the table means MY ( Y direction shift address ).
The COM electrodes without MY number are driving with non-selection level signal.
The
Marked line is display start line.
- 84 -
80
“101”
81
20
81
5
81
HM17CM256
Æ
display start line set to “5” , 1/82 duty by DS2~DS0 register
SHIFT set value
DS2
DS1
DS0
SC2
SC1
SC0
LA6
LA0
Ç
COMI0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
Ç
Ç
Ç
Ç
Ç
Ç
“000”
Ç
80
5
SHIFT=”0” (common forward scan)
“000” (1/82 duty)
“001”
“010”
“011”
“100”
“0000101” (display start point 5)
80
70
80
55
80
40
80
25
“101”
“000”
80
10
80
4
SHIFT=”1” (common backward scan)
“000” (1/82 duty)
“001”
“010”
“011”
“100”
“0000101” (display start point 5)
80
69
80
54
80
39
80
24
0
79
“101”
80
9
5
79
0
0
79
5
5
79
0
0
79
5
5
79
0
0
79
5
5
79
0
0
79
5
5
79
0
79
0
4
81
0
79
5
69
81
54
81
39
81
24
81
9
81
5
81
70
81
55
81
40
81
25
81
10
81
The number on the table means MY ( Y direction shift address ).
The COM electrodes without MY number are driving with non-selection level signal.
The
Marked line is display start line.
- 85 -
HM17CM256
È
display start line set to “5” , 1/77 duty by DS2~DS0 register
SHIFT set value
DS2
DS1
DS0
SC2
SC1
SC0
LA6
LA0
É
COMI0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
É
É
É
É
É
É
“000”
É
80
5
SHIFT=”0” (common forward scan)
“001” (1/77 duty)
“001”
“010”
“011”
“100”
“0000101” (display start point 5)
80
70
80
55
80
40
80
25
“101”
“000”
80
10
80
SHIFT=”1” (common backward scan)
“001” (1/77 duty)
“001”
“010”
“011”
“100”
“0000101” (display start point 5)
80
69
80
54
80
24
80
9
5
79
79
79
5
5
79
79
5
5
79
79
5
5
79
79
5
5
79
79
79
5
81
69
81
54
81
39
81
24
81
9
81
5
81
70
81
55
81
The number on the table means MY ( Y direction shift address ).
The COM electrodes without MY number are driving with non-selection level signal.
The
Marked line is display start line.
- 86 -
80
39
“101”
40
81
25
81
10
81
HM17CM256
Ê
display start line set to “5” , 1/66 duty by DS2~DS0 register
SHIFT set value
DS2
DS1
DS0
SC2
SC1
SC0
LA6
LA0
Ë
COMI0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
Ë
Ë
Ë
Ë
Ë
Ë
“000”
Ë
80
5
SHIFT=”0” (common forward scan)
“010” (1/66 duty)
“001”
“010”
“011”
“100”
“0000101” (display start point 5)
80
80
55
80
40
80
25
“101”
“000”
80
10
80
SHIFT=”1” (common backward scan)
“010” (1/66 duty)
“001”
“010”
“011”
“100”
“0000101” (display start point 5)
80
80
54
80
39
80
24
“101”
80
9
68
5
68
5
68
5
68
68
5
5
68
68
5
5
68
68
5
68
5
68
5
68
81
81
54
81
39
81
24
81
9
81
5
81
81
55
81
40
81
25
81
10
81
The number on the table means MY ( Y direction shift address ).
The COM electrodes without MY number are driving with non-selection level signal.
The
Marked line is display start line.
- 87 -
HM17CM256
Ì
display start line set to “5” , 1/47 duty by DS2~DS0 register
SHIFT set value
DS2
DS1
DS0
SC2
SC1
SC0
LA6
LA0
Í
COMI0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
Í
Í
Í
Í
Í
Í
“000”
Í
80
5
SHIFT=”0” (common forward scan)
“011” (1/47 duty)
“001”
“010”
“011”
“100”
“0000101” (display start point 5)
80
80
80
40
80
25
“101”
“000”
80
10
80
SHIFT=”1” (common backward scan)
“011” (1/47 duty)
“001”
“010”
“011”
“100”
“0000101” (display start point 5)
80
80
80
24
80
9
5
49
49
5
5
49
49
5
5
49
49
49
49
5
5
49
49
5
5
49
49
5
81
81
81
39
81
24
81
9
81
5
81
81
81
The number on the table means MY ( Y direction shift address ).
The COM electrodes without MY number are driving with non-selection level signal.
The
Marked line is display start line.
- 88 -
80
39
“101”
40
81
25
81
10
81
HM17CM256
Î
display start line set to “5” , 1/32 duty by DS2~DS0 register
SHIFT set value
DS2
DS1
DS0
SC2
SC1
SC0
LA6
LA0
Ï
COMI0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
Ï
Ï
Ï
Ï
Ï
Ï
“000”
Ï
80
5
SHIFT=”0” (common forward scan)
“100” (1/32 duty)
“001”
“010”
“011”
“100”
“0000101” (display start point 5)
80
80
80
80
25
“101”
“000”
80
10
80
SHIFT=”1” (common backward scan)
“100” (1/32 duty)
“001”
“010”
“011”
“100”
“0000101” (display start point 5)
80
80
80
80
24
“101”
80
9
5
34
34
5
5
34
34
34
5
5
34
34
5
5
34
34
34
5
5
34
34
5
81
81
81
81
24
81
9
81
5
81
81
81
81
25
81
10
81
The number on the table means MY ( Y direction shift address ).
The COM electrodes without MY number are driving with non-selection level signal.
The
Marked line is display start line.
- 89 -
HM17CM256
Ð
display start line set to “5” , 1/17 duty by DS2~DS0 register
SHIFT set value
DS2
DS1
DS0
SC2
SC1
SC0
LA6
LA0
Ñ
COMI0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
Ñ
Ñ
Ñ
Ñ
Ñ
Ñ
“000”
Ñ
80
5
SHIFT=”0” (common forward scan)
“101” (1/17 duty)
“001”
“010”
“011”
“100”
“0000101” (display start point 5)
80
80
80
80
“101”
“000”
80
10
80
SHIFT=”1” (common backward scan)
“101” (1/17 duty)
“001”
“010”
“011”
“100”
“0000101” (display start point 5)
80
80
80
80
9
5
19
19
19
5
5
19
19
5
5
19
19
5
5
19
19
5
5
19
19
19
5
81
81
81
81
81
9
81
5
81
81
81
The number on the table means MY ( Y direction shift address ).
The COM electrodes without MY number are driving with non-selection level signal.
The
Marked line is display start line.
- 90 -
80
“101”
81
81
10
81
HM17CM256
Ò
display start line set to “5” , 1/38 duty by DS2~DS0 register
SHIFT set value
DS2
DS1
DS0
SC2
SC1
SC0
LA6
LA0
Ó
COMI0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
Ó
Ó
Ó
Ó
Ó
Ó
“000”
Ó
80
5
SHIFT=”0” (common forward scan)
“110” (1/38 duty)
“001”
“010”
“011”
“100”
“0000101” (display start point 5)
80
80
80
40
80
25
“101”
“000”
80
10
80
SHIFT=”1” (common backward scan)
“110” (1/38 duty)
“001”
“010”
“011”
“100”
“0000101” (display start point 5)
80
80
80
39
80
24
“101”
80
9
5
40
5
40
5
40
5
40
5
40
40
5
5
40
40
5
5
40
40
5
81
81
81
39
81
24
81
9
81
5
81
81
81
40
81
25
81
10
81
The number on the table means MY ( Y direction shift address ).
The COM electrodes without MY number are driving with non-selection level signal.
The
Marked line is display start line.
- 91 -
HM17CM256
Ô
display start line set to “5” , 1/26 duty by DS2~DS0 register
SHIFT set value
DS2
DS1
DS0
SC2
SC1
SC0
LA6
LA0
Õ
COMI0
COM0
COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8
COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52
COM53
COM54
COM55
COM56
COM57
COM58
COM59
COM60
COM61
COM62
COM63
COM64
COM65
COM66
COM67
COM68
COM69
COM70
COM71
COM72
COM73
COM74
COM75
COM76
COM77
COM78
COM79
COMI1
Õ
Õ
Õ
Õ
Õ
Õ
“000”
Õ
80
5
SHIFT=”0” (common forward scan)
“111” (1/26 duty)
“001”
“010”
“011”
“100”
“0000101” (display start point 5)
80
80
80
80
25
“101”
“000”
80
10
80
SHIFT=”1” (common backward scan)
“111” (1/26 duty)
“001”
“010”
“011”
“100”
“0000101” (display start point 5)
80
80
80
24
80
9
28
5
28
5
28
5
28
28
5
5
28
28
5
5
28
28
5
28
5
28
5
28
81
81
81
81
24
81
9
81
5
81
81
81
The number on the table means MY ( Y direction shift address ).
The COM electrodes without MY number are driving with non-selection level signal.
The
Marked line is display start line.
- 92 -
80
“101”
81
25
81
10
81
HM17CM256
■ ABSOLUTE MAXIMUM RATING
ITEM
supply voltage (1)
supply voltage (2)
supply voltage (3)
supply voltage (4)
supply voltage (5)
supply voltage (6)
input voltage
Storage temperature
*1
SYMBOL
VDD
VEE
VOUT
VREG
VLCD
V1, V2, V3, V4
VI
Tstg
CONDITION
VSS(0V)
reference
Ta = +25°C
PORT
VDD
VEE
VOUT
VREG
VLCD
V1, V2, V3, V4
*1
RATINGS
-0.3 ~ +4.0
-0.3 ~ +4.0
-0.3 ~ +20.0
-0.3 ~ +20.0
-0.3 ~ +20.0
-0.3 ~ VLCD + 0.3
-0.3 ~ VDD + 0.3
-45 ~ +125
UNIT
V
V
V
V
V
V
V
°C
D0~D15, CS, RS, M/S, RD, WR, OSC1, LP, FLM, FR, CLK, RES, TEST port
■ RECOMMENDED OPERATING CONDITIONS
ITEM
supply voltage
Recommended
operating voltage
Operation
temperature
*1
*2
*3
*4
*5
SYMBOL
VDD1
VDD2
VEE
VLCD
VOUT
VREG
VREF
Topr
PORT
VDD
VEE
VLCD
VOUT
VREG
VREF
MIN
1.7
2.4
2.4
5
2.1
-30
TYP
MAX
3.3
3.3
3.3
18.0
18.0
VOUT x 0.9
3.3
85
UNIT REMARK
V
*1
V
*2
V
*3
V
*4
V
V
V
*5
°C
The case when internal reference voltage generation circuit (VBA output) is not used.
The voltage compare to VSS port.
The case when internal reference voltage generation circuit (VBA output) is used.
The voltage compare to VSS port.
When the boosting circuit is used, supply voltage VEE should be used within the limit.
When driving LCD panel by use of internal boosting circuit, it is possible to short VDD and VEE.
Please keep the relation, VSS < V4 < V3 < V2 < V1 < VLCD≤VOUT.
When the internal voltage regulator circuit is used, reference voltage VREF should be used within the limit.
Please keep the relation VREF≤VEE .
- 93 -
HM17CM256
■ ELECTRICAL CHARACTERISTICS
•
DC Characteristics 1
ITEM
SYMBOL
High level input voltage
VIH
VIL
VOH1
VOL1
VOH2
VOL2
ILI
ILO
Low level input voltage
High level output voltage
Low level output voltage
High level output voltage
Low level output voltage
Input leakage current
Output leakage current
LCD driver output
ON resistance
Static current
Oscillator frequency
oscillator frequency
by External resistor
Boosting output
voltage
RON1
ISTB
fOSC1
fOSC2
fOSC3
fOSC4
fOSC5
fOSC6
fr1
fr2
fr3
fr4
fr5
fr6
VOUT
VBA output voltage
IDD1
IDD2
IDD3
IDD4
IDD5
IDD6
IDD7
IDD8
IDD9
IDD10
IDD11
IDD12
IDD13
IDD14
IDD15
IDD16
VBA
VREG output voltage
VREG
Current consumption (1)
Current consumption (2)
Current consumption (3)
Current consumption (4)
Current consumption (5)
Current consumption (6)
Current consumption (7)
Current consumption (8)
Current consumption (9)
Current consumption (10)
Current consumption (11)
Current consumption (12)
Current consumption (13)
Current consumption (14)
Current consumption (15)
Current consumption (16)
- 94 -
Unless otherwise noted VSS = 0V, VDD = +1.7~+3.3V, Ta = -30~+85°C
UNIT PORT
CONDITION
MIN
TYP
MAX
0.8 VDD
VDD
V
*1
0
0.22 VDD
V
*1
IOH = -0.4mA
VDD - 0.4
V
*2
IOL = 0.4mA
0.4
V
*2
IOH = -0.1mA
VDD - 0.4
V
*3
IOL = 0.1mA
0.4
V
*3
VI = VSS or VDD
-10
10
*4
µA
VI = VSS or VDD
-10
10
*5
µA
VLCD = 10V
1
2
| VON| = 0.5V
*6
kΩ
VLCD = 6V
2
4
Ö
CS=VDD, Ta=25°C
VDD = 3V
Ta = 25°C
VDD = 3V
FFL = “0”
(normal
mode)
15
TBD
FFL = “1”
(high speed
mode)
TBD
Rf=6.2kΩ
Rf=20kΩ
Rf=51kΩ
TBD
Rf=110kΩ
Rf=390kΩ
Rf=820kΩ
N x boosting (N=2~7)
RL = 30kΩ (between VOUT ,VSS)
VDD = 2.5V
7 x boosting (all ON)
VDD = 2.5V 7x
boosting(cross check)
VDD = 3.0V
6 x boosting (all ON)
VDD = 3.0V 6x
boosting(cross check)
VDD = 3.0V
5 x boosting (all ON)
VDD = 3.0V 5x
boosting(cross check)
VDD = 3.0V
4 x boosting (all ON)
VDD = 3.0V 4x
boosting(cross check)
VEE = 2.4~3.3V
VEE = 2.4~3.3V
VREF = 0.9 x VEE
N x boosting (N=2~7)
372
84
12
762.6
172.2
24.6
775.2
373.9
167.8
84.3
25.8
12.6
TBD
kHz
TBD
TBD
N * VEE
* 0.95
FFL = “0”
FFL = “1”
FFL = “0”
FFL = “1”
FFL = “0”
FFL = “1”
FFL = “0”
FFL = “1”
FFL = “0”
FFL = “1”
FFL = “0”
FFL = “1”
FFL = “0”
FFL = “1”
FFL = “0”
FFL = “1”
µA
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
0.9 VEE
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
(VREF x N)
TBD
*7
*8
*9
*10
*8
*9
*10
kHz
V
*11
µA
*12
V
*13
V
*14
HM17CM256
■ ELECTRICAL CHARACTERISTICS
•
•
DC Characteristics 1
ITEM
SYMBOL
Output voltage
VLCD
V1
V2
V3
V4
Unless otherwise noted VSS = 0V, VDD = +1.7~+3.3V, Ta = -30~+85°C
UNIT PORT
CONDITION
MIN
TYP
MAX
TBD
TBD
TBD
TBD
V
TBD
TBD
TBD
TBD
V
TBD
TBD
TBD
TBD
V
TBD
TBD
TBD
TBD
V
TBD
TBD
TBD
TBD
V
Oscillator frequency,fOSC at each mode, relation external clock frequency,fCK to LCD frame frequency,fFLM
Used
Display duty (1/D)
ITEM
Display mode
PORT
clock
1/82, 1/77, 1/66 1/47, 1/38, 1/32, 1/26
1/17
Variable
fOSC / (62*D)
fOSC / (62*D*2)
fOSC / (62*D*4)
gradation display
Using internal
oscillator
fOSC
Fixed gradation
fOSC / (14*D)
fOSC / (14*D*2)
fOSC / (14*D*4)
circuit
display
BW display
fOSC / (2*D)
fOSC / (2*D*2)
fOSC / (2*D*4)
FLM
Variable
fCK / (62*D)
fCK / (62*D*2)
fCK / (62*D*4)
gradation display
Input external
fCK
Fixed gradation
clock
fCK / (14*D)
fCK / (14*D*2)
fCK / (14*D*4)
display
BW display
fCK / (2*D)
fCK / (2*D*2)
fCK / (2*D*4)
- 95 -
HM17CM256
Applied port (* Remark Solves)
*1
D0~D15, CS, RS, M/S, RD, WR, P/S, SEL68, CLK, CL, FLM, FR, RES
ports
*2
D0~D15
*3
CL, FLM, FR, CLK
*4
CS, RS, M/S, SEL68, RD, WR, P/S, RES, OSC1 ports
*5
applicable at D0~D15, CL, FLM, FR, CLK = high impedance state
*6
SEGA0~SEGA127, SEGB0~SEGB127, SEGC0~SEGC127, COM0~COM79, COMI0, COMI1 ports
resistance when being supplied 0.5V between each output ports and power port (VLCD, V1, V2, V3, V4)
applicable under bias ratio = 1/9
*7
VDD ports
VDD current when source clock is stopped, chip selection (CS=VDD) is non-selection state and no load.
*8
oscillator frequency when internal oscillator circuit is used ( gradation display mode).
applicable under Rf register of oscillator circuit, {Rf2, Rf1, Rf0} = “000”
*9
oscillator frequency when internal oscillator circuit is used ( fixed gradation display mode).
applicable under Rf register of oscillator circuit, {Rf2, Rf1, Rf0} = “000”
ports
ports
*10 oscillator frequency when internal oscillator circuit is used ( BW display mode).
applicable under Rf register of oscillator circuit, {Rf2, Rf1, Rf0} = “000”
*11 VOUT port
N x boosting (N=2~7). applicable under internal oscillator circuit and internal power circuit are ON state
VEE = 2.4~3.3V, electric volume is MAX(“1111111”).
bias = 1/5~1/10, 1/82 duty, no load at LCD driver port.
RL = 30kΩ(between VOUT ,VSS), CA1= CA2=1.0µF, CA3=0.1µF, DCON=“1”, AMPON=“1”
*12 applicable under internal oscillator circuit and internal power circuit are ON state and no access from
CPU.
electric volume is “1111111”.
Display is all ON and cross check pattern display ( variable gradation display mode), and no load at LCD
driver port.
Test condition :
VDD=VEE=VREF, CA1=CA2=1.0µF, CA3=0.1µF, DCON=“1”, AMPON=“1”, NLIN=”0”,
1/82 duty.
*13 VREG output voltage when VBA output is connected to VREF input, VREG gain is N=1.
*14 VREG port
VEE= 2.4~3.3V, VREF= 0.9 VEE, bias= 1/5~1/10, 1/82 duty, electric volume is “1111111”
Cross hatch state and no load at LCD driver port.
Boosting coefficient N is 2~7 times
Test condition : CA1=CA2=1.0µF, CA3=0.1µF, DCON=“1”, AMPON=“1”, NLIN=”0”
×
- 96 -
×
HM17CM256
■ AC CHARACTERISTICS
•
SYSTEM BUS READ / WRITE TIMING (80 series CPU interface)
(write timing)
tAS8
tAH8
CS
RS
WR
tWRLW8
tWRHW8
tDS8
tDH8
D0 ∼ D15
tCYC8
SYMBOL
tAH8
tAS8
System cycle timing
Write ”L” pulse width
Write ”H” pulse width
tCYC8
tWRLW8
tWRHW8
TBD
TBD
TBD
ns
ns
ns
tDS8
tDH8
TBD
TBD
ns
ns
Data setup timing
Data hold timing
CONDITION
MIN.
TBD
TBD
(VDD=2.7∼3.3V, Ta=-30∼+85°C)
MAX.
UNIT
PORT
ns
CS
ns
RS
ITEM
Address hold timing
Address setup timing
SYMBOL
tAH8
tAS8
System cycle timing
Write ”L” pulse width
Write ”H” pulse width
tCYC8
tWRLW8
tWRHW8
TBD
TBD
TBD
ns
ns
ns
tDS8
tDH8
TBD
TBD
ns
ns
Data setup timing
Data hold timing
MIN.
TBD
TBD
D0 ∼ D15
(VDD=2.4∼2.7V, Ta=-30∼+85°C)
MAX.
UNIT
PORT
ns
CS
ns
RS
ITEM
Address hold timing
Address setup timing
CONDITION
WR
WR
D0 ∼ D15
(VDD=1.7∼2.4V, Ta=-30∼+85°C)
ITEM
Address hold timing
Address setup timing
SYMBOL
tAH8
tAS8
System cycle timing
Write ”L” pulse width
Write ”H” pulse width
tCYC8
tWRLW8
tWRHW8
TBD
TBD
TBD
ns
ns
ns
tDS8
tDH8
TBD
TBD
ns
ns
Data setup timing
Data hold timing
notice)
CONDITION
MIN.
TBD
TBD
MAX.
UNIT
ns
ns
PORT
CS
RS
WR
D0 ∼ D15
All timing reference is 20% and 80% of VDD and 80%.
- 97 -
HM17CM256
Ø
read timing
Ù
tAH8
tAS8
CS
RS
tWRLR8
RD
tWRHR8
tRDH8
D0 ∼ D15
tRDD8
tCYC8
ITEM
Address hold timing
Address setup timing
SYMBOL
tAH8
tAS8
System cycle timing
Write ”L” pulse width
Write ”H” pulse width
tCYC8
tWRLR8
tWRHR8
TBD
TBD
TBD
tDS8
tDH8
TBD
Data setup timing
Data hold timing
CONDITION
MIN.
TBD
TBD
ns
ns
ns
TBD
ITEM
Address hold timing
Address setup timing
SYMBOL
tAH8
tAS8
System cycle timing
Write ”L” pulse width
Write ”H” pulse width
tCYC8
tWRLR8
tWRHR8
TBD
TBD
TBD
tDS8
tDH8
TBD
Data setup timing
Data hold timing
(VDD=2.7∼3.3V, Ta=-30∼+85°C)
MAX.
UNIT
PORT
ns
CS
ns
RS
CONDITION
MIN.
TBD
TBD
ns
ns
RD
D0 ∼ D15
(VDD=2.4∼2.7V, Ta=-30∼+85°C)
MAX.
UNIT
PORT
ns
CS
ns
RS
ns
ns
ns
TBD
ns
ns
RD
D0 ∼ D15
(VDD=1.7∼2.4V, Ta=-30∼+85°C)
ITEM
Address hold timing
Address setup timing
SYMBOL
tAH8
tAS8
System cycle timing
Write ”L” pulse width
Write ”H” pulse width
tCYC8
tWRLR8
tWRHR8
TBD
TBD
TBD
tDS8
tDH8
TBD
Data setup timing
Data hold timing
notice)
- 98 -
CONDITION
All timing reference is 20% and 80% of VDD and 80%.
MIN.
TBD
TBD
MAX.
UNIT
ns
ns
ns
ns
ns
TBD
ns
ns
PORT
CS
RS
RD
D0 ∼ D15
HM17CM256
•
SYSTEM BUS READ / WRITE TIMING (68 series CPU interface)
(write timing
Ú
tAS6
tAH6
CS
RS
R/W
(WR)
tELW6
tEHW6
E
(RD)
tDS6
tDH6
D0 ∼ D15
tCYC6
ITEM
Address hold timing
Address setup timing
System cycle timing
Enable ”L” pulse width
Enable ”H” pulse width
Data setup timing
Data hold timing
ITEM
Address hold timing
Address setup timing
System cycle timing
Enable ”L” pulse width
Enable ”H” pulse width
Data setup timing
Data hold timing
SYMBOL
tAH6
tAS6
CONDITION
MIN.
TBD
TBD
(VDD=2.7∼3.3V, Ta=-30∼+85°C)
MAX.
UNIT
PORT
ns
CS
ns
RS
tCYC6
tELW6
tEHW6
TBD
TBD
TBD
ns
ns
ns
tDS6
tDH6
TBD
TBD
ns
ns
SYMBOL
tAH6
tAS6
CONDITION
MIN.
TBD
TBD
E
D0 ∼ D15
(VDD=2.4∼2.7V, Ta=-30∼+85°C)
MAX.
UNIT
PORT
ns
CS
ns
RS
tCYC6
tELW6
tEHW8
TBD
TBD
TBD
ns
ns
ns
tDS6
tDH6
TBD
TBD
ns
ns
E
D0 ∼ D15
(VDD=1.7∼2.4V, Ta=-30∼+85°C)
ITEM
Address hold timing
Address setup timing
System cycle timing
Enable ”L” pulse width
Enable ”H” pulse width
Data setup timing
Data hold timing
notice)
SYMBOL
tAH6
tAS6
CONDITION
MIN.
TBD
TBD
MAX.
UNIT
ns
ns
tCYC6
tELW6
tEHW6
TBD
TBD
TBD
ns
ns
ns
tDS6
tDH6
TBD
TBD
ns
ns
PORT
CS
RS
E
D0 ∼ D15
All timing reference is 20% and 80% of VDD and 80%.
- 99 -
HM17CM256
(read timing)
tAS6
tAH6
CS
RS
R/W
(WR)
tELR6
tEHR6
E
(RD)
tRDH6
D0 ∼ D15
tRDD6
tCYC6
ITEM
Address hold timing
Address setup timing
SYMBOL
tAH6
tAS6
CONDITION
MIN.
TBD
TBD
System cycle timing
Enable ”L” pulse width
Enable ”H” pulse width
tCYC6
tELR6
tEHR6
TBD
TBD
TBD
Data setup timing
Data hold timing
tDS6
tDH6
TBD
ITEM
Address hold timing
Address setup timing
SYMBOL
tAH6
tAS6
(VDD=2.7∼3.3V, Ta=-30∼+85°C)
MAX.
UNIT
PORT
ns
CS
ns
RS
ns
ns
ns
TBD
CONDITION
MIN.
TBD
TBD
System cycle timing
Enable ”L” pulse width
Enable ”H” pulse width
tCYC6
tELR6
tEHR8
TBD
TBD
TBD
Data setup timing
Data hold timing
tDS6
tDH6
TBD
ns
ns
E
D0 ∼ D15
(VDD=2.4∼2.7V, Ta=-30∼+85°C)
MAX.
UNIT
PORT
ns
CS
ns
RS
ns
ns
ns
TBD
ns
ns
E
D0 ∼ D15
(VDD=1.7∼2.4V, Ta=-30∼+85°C)
ITEM
Address hold timing
Address setup timing
SYMBOL
tAH6
tAS6
CONDITION
MIN.
TBD
TBD
MAX.
UNIT
ns
ns
System cycle timing
Enable ”L” pulse width
Enable ”H” pulse width
tCYC6
tELR6
tEHR6
TBD
TBD
TBD
ns
ns
ns
Data setup timing
Data hold timing
tDS6
tDH6
TBD
TBD
ns
ns
notice)
- 100 -
All timing reference is 20% and 80% of VDD and 80%.
PORT
CS
RS
E
D0 ∼ D15
HM17CM256
•
SERIAL INTERFACE TIMING
CS
tCSH
tCSS
RS
tASS
SCL
tAHS
tSLW
tSHW
tCYCS
tDSS
tDHS
SDA
ITEM
Serial clock cycle
SCL ”H” pulse width
SCL ”L” pulse width
Address setup timing
Address hold timing
Data setup timing
Data hold timing
CS – SCL timing
CS hold timing
ITEM
Serial clock cycle
SCL ”H” pulse width
SCL ”L” pulse width
Address setup timing
Address hold timing
Data setup timing
Data hold timing
CS – SCL timing
CS hold timing
notice)
SYMBOL
tCYCS
tSHW
tSLW
tASS
tAHS
tDSS
tDHS
CONDITION
tCSS
tCSH
SYMBOL
tCYCS
tSHW
tSLW
tASS
tAHS
tDSS
tDHS
tCSS
tCSH
MIN.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
CONDITION
MIN.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
(VDD=2.7∼3.3V, Ta=-30∼+85°C)
MAX.
UNIT
PORT
ns
ns
SCL
ns
ns
RS
ns
ns
SDA
ns
ns
ns
CS
(VDD=2.4∼2.7V, Ta=-30∼+85°C)
MAX.
UNIT
PORT
ns
ns
SCL
ns
ns
RS
ns
ns
SDA
ns
ns
CS
ns
All timing reference is 20% and 80% of VDD and 80%.
- 101
-
HM17CM256
ITEM
Serial clock cycle
SCL ”H” pulse width
SCL ”L” pulse width
Address setup timing
Address hold timing
Data setup timing
Data hold timing
CS – SCL timing
CS hold timing
notice)
- 102 -
SYMBOL
tCYCS
tSHW
tSLW
tASS
tAHS
tDSS
tDHS
tCSS
tCSH
CONDITION
All timing reference is 20% and 80% of VDD and 80%.
MIN.
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
(VDD=1.7∼2.4V, Ta=-30∼+85°C)
MAX.
UNIT
PORT
ns
ns
SCL
ns
ns
RS
ns
ns
SDA
ns
ns
CS
ns
HM17CM256
•
DISPLAY CONTROL TIMING
tCLLW
tCLHW
CL
tDFLM
tDFLM
FLM
tDM
FR
INPUT TIMING ( slave mode )
ITEM
SYMBOL
CL ”H” pulse width
tCLHW
CL ”L” pulse width
tCLLW
FLM delay time
tDFLM
FR delay time
tFR
INPUT TIMING ( slave mode )
ITEM
SYMBOL
CL ”H” pulse width
tCLHW
CL ”L” pulse width
tCLLW
FLM delay time
tDFLM
FR delay time
tFR
OUTPUT TIMING ( master mode )
ITEM
SYMBOL
FLM delay time
tDFLM
FR delay time
tFR
OUTPUT TIMING ( master mode )
ITEM
SYMBOL
FLM delay time
tDFLM
FR delay time
tFR
notice)
CONDITION
CONDITION
CONDITION
CL=15pF
CONDITION
CL=15pF
MIN.
80
80
-1.0
-1.0
(VDD=2.4∼3.3V, Ta=-30∼+85°C)
MAX.
UNIT
PORT
µs
CL
µs
1.0
FLM
µs
1.0
FR
µs
MIN.
80
80
-1.0
-1.0
(VDD=1.7∼2.4V, Ta=-30∼+85°C)
MAX.
UNIT
PORT
µs
CL
µs
1.0
FLM
µs
1.0
CL
µs
MIN.
10
10
(VDD=2.4∼3.3V, Ta=-30∼+85°C)
MAX.
UNIT
PORT
500
ns
FLM
500
ns
FR
MIN.
10
10
(VDD=1.7∼2.4V, Ta=-30∼+85°C)
MAX.
UNIT
PORT
1000
ns
FLM
1000
ns
FR
All timing reference is 20% and 80% of VDD and 80%.
- 103
-
HM17CM256
SOURCE CLOCK INPUT TIMING
•
tCKLW
tCKHW
OSC1
ITEM
OSC1 “H” pulse width (1)
OSC1 “L” pulse width (1)
OSC1 “H” pulse width (2)
OSC1 “L” pulse width (2)
OSC1 “H” pulse width (3)
OSC1 “L” pulse width (3)
SYMBOL
tCKHW1
tCKLW1
tCKHW2
tCKLW2
tCKHW3
tCKLW3
CONDITION
MIN.
TBD
TBD
TBD
TBD
TBD
TBD
(VDD=2.4∼3.3V, Ta=-30∼+85°C)
MAX.
UNIT
PORT
TBD
OSC1
µs
TBD
µs
∗1
TBD
OSC1
µs
TBD
µs
∗2
TBD
OSC
µs
1
TBD
µs
∗3
ITEM
OSC1 “H” pulse width (1)
OSC1 “L” pulse width (1)
OSC1 “H” pulse width (2)
OSC1 “L” pulse width (2)
OSC1 “H” pulse width (3)
OSC1 “L” pulse width (3)
SYMBOL
tCKHW1
tCKLW1
tCKHW2
tCKLW2
tCKHW3
tCKLW3
CONDITION
MIN.
TBD
TBD
TBD
TBD
TBD
TBD
(VDD=1.7∼2.4V, Ta=-30∼+85°C)
MAX.
UNIT
PORT
TBD
OSC1
µs
TBD
µs
∗1
TBD
OSC1
µs
TBD
µs
∗2
TBD
OSC1
µs
TBD
µs
∗3
notice)
∗1
∗2
∗3
- 104 -
All timing reference is 20% and 80% of VDD and 80%.
applicable under gradation display , MON=”0”, PWM=”0”
applicable under fixed gradation display , MON=”0”,PWM=”1”
applicable under BW display , MON=”1”
HM17CM256
•
RESET INPUT TIMING
tRW
RES
tR
Internal status
ITEM
Reset time
RES “L”
pulse width
Reset time
notice)
SYMBOL
CONDITION
Reset completion
MIN.
tR
ITEM
RES “L”
resetting
pulse width
1.0
tRW
SYMBOL
(VDD=2.4∼3.3V, Ta=-30∼+85°C)
MAX.
UNIT
PORT
µs
10.0
CONDITION
MIN.
tR
tRW
RES
(VDD=1.7∼2.4V, Ta=-30∼+85°C)
MAX.
UNIT
PORT
1.5
10.0
µs
µs
µs
RES
All timing reference is 20% and 80% of VDD and 80%.
- 105
-
HM17CM256
■ APPLICATION EXAMPLE
Û
Û
reference
Ü
Ü
(1) connection with CPU
a) 80 series CPU interface
1.7V ~ 3.3V
VCC
(80 series CPU)
A0
A1 ~ A7
IORQ
D0 ~ D7
VDD
RS
7
Decoder
8
RD
WR
RES
CS
D0 ~ D7
RD
WR
RES
GND
VSS
Reset input
b) 68 series CPU interface
1.7V ~ 3.3V
VCC
(68 series CPU)
A0
A1 ~ A15
VMA
RS
15
D0 ~ D7
Decoder
8
E
R/W
RES
CS
D0 ~ D7
RD(E)
WR(R/W)
RES
GND
VDD
VSS
Reset input
c) CPU connection with serial interface
1.7V ~ 3.3V
VCC
A0
A1 ~ A7
(CPU)
RS
7
Decoder
SDA
SCL
RES
RES
Reset input
- 106 -
CS
PORT1
PORT2
GND
VDD
VSS
HM17CM256
(2) MULTI CHIP INTERFACE
a) connection example of input interface
(parallel interface)
D0 ~ D7
RD
P/S
SEL68
M/S
RS
CS
RES
D0 ~ D7
RD
WR
P/S
SEL68
M/S
RS
CS
RES
VDD
RES
CS1
CS2
RS
WR(R/W)
RD(E)
D0 ~ D7
SEL68
WR
(Slave)
(Master)
8
(4-line type serial interface)
SMODE
EXCS
SMODE
EXCS
SPOL
SCL
SDA
RD
WR
P/S
SEL68
M/S
RS
CS
RES
EXCS
(Slave)
SMODE
SPOL
SCL
SDA
RD
WR
P/S
SEL68
M/S
RS
CS
RES
(Master)
VDD
RES
CS1
CS2
RS
SDA
SCL
(4-line type serial interface, CS1 common)
SPOL
SCL
SDA
RD
WR
P/S
SEL68
M/S
RS
CS
RES
EXCS
(Slave)
SMODE
SPOL
SCL
SDA
RD
WR
P/S
SEL68
M/S
RS
CS
RES
(Master)
VDD
RES
CS
RS
SDA
SCL
- 107
-
VDD
RES
CS
SDA
SCL
- 108 (Slave)
SPOL
SCL
EXCS
(3-line type serial interface, CS1 common)
EXCS
SDA
SCL
SMODE
VDD
RES
CS1
CS2
SMODE
SPOL
SCL
(Master)
SDA
RD
WR
P/S
SEL68
M/S
RS
CS
RES
EXCS
SMODE
SPOL
SCL
SDA
RD
WR
P/S
SEL68
M/S
RS
CS
RES
(Master)
SDA
RD
WR
P/S
SEL68
M/S
RS
CS
RES
EXCS
SMODE
SPOL
SCL
SDA
RD
WR
P/S
SEL68
M/S
RS
CS
RES
HM17CM256
(3-line type serial interface)
(Slave)
HM17CM256
a) connection example of power supply
VDD
VDD
VEE
VBA
VREF
C1+
C1C2+
C1C2+
C2C3+
C2C3+
C3C4+
C3C4+
C4C5+
C4C5+
CA1
CA1
CA1
CA1
C5C6+
CA1
(Master)
CA1
C5C6+
C6VOUT
CA1
VSS
CA3
VSS
(Slave)
VDD
VDD
VEE
VBA
VREF
C1+
C6VOUT
VREG
CA2
CA2
CA2
CA2
CA2
VLCD
VLCD
VREG
VLCD
V1
V1
V1
V2
V2
V2
V3
V3
V3
V4
V4
V4
CLK
CL
FLM
FR
CLK
CL
FLM
FR
Be cautious of using as following description when LCD panel is connected with master/slave structure.
1)
2)
3)
4)
5)
Display timing is controlled by master chip.
The CL, FLM, FR, CLK signals are stopped when master
chip is display OFF.
When you are going to OFF the display, please OFF the display of slave chip first
before master chip display is OFF.
Boosting circuit and voltage converting circuit is OFF after execution HALT command at master chip,
then LCD driving output is VSS level and so display is OFF. And Voltage common is stopped. Because
the voltage common of slave chip is stopped, please run slave chip display OFF first and then run master
chip HALT command.
The electric volume setting is valid at master chip only(at upper structure).
To protect that VOUT is being floated, please connect VOUT with VLCD voltage level.
Please use under condition that OSC1 and OSC2 port of slave chip is OFF.
- 109
-
HM17CM256
•
•
Typical characteristic
ITEM
Basic delay time of gate
CONDITION
Ta=+25°C, VSS=0V, VDD=3.0V
MIN
TYP
10
MAX
IN/OUTPUT CIRCUIT STRUCTURE
(a) input circuit 1
VDD
port :
CS, RS, RD, WR, SEL68, M/S
P/S, RES
I
Input signal
VSS(0V)
(b-1) in/out circuit 1
VDD
port :
FLM, LP, FR, CLK
I/O
Input signal
VSS(0V)
VDD
Output control signal
Output signal
VSS(0V)
(b-2) in/out circuit 2
VDD
port :
D0~D15
I/O
Input signal
VSS(0V)
VSS(0V)
Input control signal
VDD
Output control signal
Output signal
VSS(0V)
- 110 -
UNIT
ns
HM17CM256
(c) LCD driver output circuit
VLCD
O
VLCD
V1/V2
output control
signal 1
output control
signal 2
output control
signal 3
output control
signal 4
VSS(0V)
Port :
VLCD
V3/V4
VSS(0V)
VSS(0V)
SEGA0~SEGA127
SEGB0~SEGB127
SEGC0~SEGC127
COM0~COM79
COMI0, COMI1
SEGSA0, SEGSR1
SEGSB0, SEGSB1
SEGSC0, SEGSC1
<precautions>
The details of this specification was written
sincerely, but it is not a letter of guarantee of
legal.
Especially, the application circuit is just
for reference.
This specification do not guarantee that we did
not use others patent or intellectural property.
- 111
-