WIRELESS
IA4420 Universal ISM Band
FSK Transceiver
IA4420
PIN ASSIGNMENT
revC and later
DESCRIPTION
Integration’s IA4420 is a single chip, low power, multi-channel FSK transceiver
designed for use in applications requiring FCC or ETSI conformance for unlicensed
use in the 315, 433, 868 and 915 MHz bands. The IA4420 transceiver is a part of
Integration’s EZRadioTM product line, which produces a flexible, low cost, and
highly integrated solution that does not require production alignments. The chip
is a complete analog RF and baseband transceiver including a multi-band PLL
synthesizer with PA, LNA, I/Q down converter mixers, baseband filters and
amplifiers, and an I/Q demodulator. All required RF functions are integrated.
Only an external crystal and bypass filtering are needed for operation.
The IA4420 features a completely integrated PLL for easy RF design, and its rapid
settling time allows for fast frequency-hopping, bypassing multipath fading and
interference to achieve robust wireless links. The PLL’s high resolution allows the
usage of multiple channels in any of the bands. The receiver baseband bandwidth
(BW) is programmable to accommodate various deviation, data rate and crystal
tolerance requirements. The transceiver employs the Zero-IF approach with I/Q
demodulation. Consequently, no external components (except crystal and
decoupling) are needed in most applications.
The IA4420 dramatically reduces the load on the microcontroller with the
integrated digital data processing features: data filtering, clock recovery, data
pattern recognition, integrated FIFO and TX data register. The automatic frequency
control (AFC) feature allows the use of a low accuracy (low cost) crystal. To
minimize the system cost, the IA4420 can provide a clock signal for the
microcontroller, avoiding the need for two crystals.
For low power applications, the IA4420 supports low duty cycle operation based
on the internal wake-up timer.
FUNCTIONAL BLOCK DIAGRAM
MIX
I
AMP
OC
7
clk
RF1 13
MIX
Q
AMP
Data Filt
CLK Rec
I/Q
DEMOD
Self cal.
LNA
RF2 12
data
6
DCLK /
CFIL /
FFIT /
FSK /
DATA /
nFFS
OC
FIFO
RSSI
PLL & I/Q VCO
with cal.
RF Parts
COMP
DQD
AFC
BB Amp/Filt./Limiter
Xosc
WTM
with cal.
Data processing units
LBD
Controller
Bias
Low Power parts
8
9
15
1
2
CLK
XTL /
REF
ARSSI
SDI
SCK
3
4
nSEL SDO
SDI
SCK
nSEL
SDO
nIRQ
FSK / DATA / nFFS
DCLK / CFIL / FFIT
CLK
nINT / VDI
ARSSI
VDD
RF1
RF2
VSS
nRES
XTL / REF
See back page for ordering information.
FEATURES
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Fully integrated (low BOM, easy design-in)
No alignment required in production
Fast-settling, programmable, high-resolution PLL synthesizer
Fast frequency-hopping capability
High bit rate (up to 115.2 kbps in digital mode and 256 kbps
in analog mode)
Direct differential antenna input/output
Integrated power amplifier
Programmable TX frequency deviation (15 to 240 KHz)
Programmable RX baseband bandwidth (67 to 400 kHz)
Analog and digital RSSI outputs
Automatic frequency control (AFC)
Data quality detection (DQD)
Internal data filtering and clock recovery
RX synchron pattern recognition
SPI compatible serial control interface
Clock and reset signals for microcontroller
16 bit RX Data FIFO
Two 8 bit TX data registers
Low power duty cycle mode
Standard 10 MHz crystal reference
Wake-up timer
2.2 to 5.4 V supply voltage
Low power consumption
Low standby current (0.3 µA)
Compact 16 pin TSSOP package
TYPICAL APPLICATIONS
PA
CLK div
DATASHEET
5
10
16
11
14
nIRQ
nRES
nINT /
VDI
VSS
VDD
•
•
•
•
•
•
•
•
•
Remote control
Home security and alarm
Wireless keyboard/mouse and other PC peripherals
Toy controls
Remote keyless entry
Tire pressure monitoring
Telemetry
Personal/patient data logging
Remote automatic meter reading
1
IA4420-DS Rev 1.4r 0705
PRELIMINARY
www.integration.com
IA4420
DETAILED FEATURE-LEVEL DESCRIPTION
The IA4420 FSK transceiver is designed to cover the unlicensed
frequency bands at 315, 433, 868 and 915 MHz. The devices
facilitate compliance with FCC and ETSI requirements.
The receiver block employs the Zero-IF approach with I/Q
demodulation, allowing the use of a minimal number of external
components in a typical application. The IA4420 incorporates a
fully integrated multi-band PLL synthesizer, PA with antenna tuning,
an LNA with switchable gain, I/Q down converter mixers, baseband
filters and amplifiers, and an I/Q demodulator followed by a data
filter.
PLL
The programmable PLL synthesizer determines the operating
frequency, while preserving accuracy based on the on-chip crystalcontrolled reference oscillator. The PLL’s high resolution allows the
usage of multiple channels in any of the bands.
The RF VCO in the PLL performs automatic calibration, which requires
only a few microseconds. Calibration always occurs when the
synthesizer starts. If temperature or supply voltage changes
significantly, VCO recalibration can be invoked easily. Recalibration
can be initiated at any time by switching the synthesizer off and
back on again.
RF Power Amplifier (PA)
The power amplifier has an open-collector differential output and
can directly drive a loop antenna with a programmable output power
level. An automatic antenna tuning circuit is built in to avoid costly
trimming procedures and the so-called “hand effect.”
LNA
The LNA has 250 Ohm input impedance, which functions well with
the proposed antennas (see: Application Notes available from
http://www.integration.com)
If the RF input of the chip is connected to 50 Ohm devices, an
external matching circuit is required to provide the correct matching
and to minimize the noise figure of the receiver.
The LNA gain can be selected (0, –6, –14, –20 dB relative to the
highest gain) according to RF signal strength. It can be useful in an
environment with strong interferers.
Data Filtering and Clock Recovery
Output data filtering can be completed by an external capacitor or by
using digital filtering according to the final application.
Analog operation: The filter is an RC type low-pass filter followed
by a Schmitt-trigger (St). The resistor (10 kOhm) and the St are
integrated on the chip. An (external) capacitor can be chosen according
to the actual bit rate. In this mode, the receiver can handle up to 256
kbps data rate. The FIFO can not be used in this mode and clock is
not provided for the demodulated data.
Digital operation: A digital filter is used with a clock frequency at
29 times the bit rate. In this mode there is a clock recovery circuit
(CR), which can provide synchronized clock to the data. Using this
clock the received data can fill a FIFO. The CR has three operation
modes: fast, slow, and automatic. In slow mode, its noise immunity
is very high, but it has slower settling time and requires more accurate
data timing than in fast mode. In automatic mode the CR automatically
changes between fast and slow mode. The CR starts in fast mode,
then after locking it automatically switches to slow mode
(Only the digital data filter and the clock recovery use the bit rate
clock. For analog operation, there is no need for setting the correct
bit rate.)
Baseband Filters
The receiver bandwidth is selectable by programming the bandwidth
(BW) of the baseband filters. This allows setting up the receiver
according to the characteristics of the signal to be received.
An appropriate bandwidth can be chosen to accommodate various
FSK deviation, data rate and crystal tolerance requirements. The
filter structure is 7th order Butterworth low-pass with 40 dB
suppression at 2*BW frequency. Offset cancellation is done by
using a high-pass filter with a cut-off frequency below 7 kHz.
2
IA4420
Data Validity Blocks
RSSI
A digital RSSI output is provided to monitor the input signal level. It
goes high if the received signal strength exceeds a given
preprogrammed level. An analog RSSI signal is also available. The
RSSI settling time depends on the external filter capacitor. Pin 15 is
used as analog RSSI output. The digital RSSI can be can be monitored
by reading the status register.
When the microcontroller turns the crystal oscillator off by clearing
the appropriate bit using the Configuration Setting Command, the
chip provides a fixed number (196) of further clock pulses (“clock
tail”) for the microcontroller to let it go to idle or sleep mode.
Low Battery Voltage Detector
The low battery detector circuit monitors the supply voltage and
generates an interrupt if it falls below a programmable threshold
level. The detector circuit has 50 mV hysteresis.
Analog RSSI Voltage vs. RF Input Power
Wake-Up Timer
P1
RSSI
voltage
[V]
P2
P3
P4
The wake-up timer has very low current consumption (1.5 uA typical)
and can be programmed from 1 ms to several days with an accuracy
of ±5%.
It calibrates itself to the crystal oscillator at every startup, and then
at every 30 seconds. When the crystal oscillator is switched off, the
calibration circuit switches it back on only long enough for a quick
calibration (a few milliseconds) to facilitate accurate wake-up timing.
Input Power [dBm]
Event Handling
P1
-65 dBm
1300 mV
P2
-65 dBm
1000 mV
P3
-100 dBm
600 mV
P4
-100 dBm
300 mV
DQD
The Data Quality Detector is based on counting the spikes on the
unfiltered received data. For correct operation, the “DQD threshold”
parameter must be filled in by using the Data Filter Command.
In order to minimize current consumption, the transceiver supports
different power saving modes. Active mode can be initiated by several
wake-up events (negative logical pulse on nINT input, wake-up timer
timeout, low supply voltage detection, on-chip FIFO filled up or
receiving a request through the serial interface).
If any wake-up event occurs, the wake-up logic generates an interrupt
signal, which can be used to wake up the microcontroller, effectively
reducing the period the microcontroller has to be active. The source
of the interrupt can be read out from the transceiver by the
microcontroller through the SDO pin.
Interface and Controller
AFC
By using an integrated Automatic Frequency Control (AFC) feature,
the receiver can minimize the TX/RX offset in discrete steps, allowing
the use of:
·
Inexpensive, low accuracy crystals
·
Narrower receiver bandwidth (i.e. increased sensitivity)
·
Higher data rate
Crystal Oscillator
The IA4420 has a single-pin crystal oscillator circuit, which provides
a 10 MHz reference signal for the PLL. To reduce external parts and
simplify design, the crystal load capacitor is internal and
programmable. Guidelines for selecting the appropriate crystal can
be found later in this datasheet.
The transceiver can supply the clock signal for the microcontroller;
so accurate timing is possible without the need for a second crystal.
An SPI compatible serial interface lets the user select the frequency
band, center frequency of the synthesizer, and the bandwidth of the
baseband signal path. Division ratio for the microcontroller clock,
wake-up timer period, and low supply voltage detector threshold are
also programmable. Any of these auxiliary functions can be disabled
when not needed. All parameters are set to default after power-on;
the programmed values are retained during sleep mode. The interface
supports the read-out of a status register, providing detailed
information about the status of the transceiver and the received
data.
The transmitter block is equipped with an 8 bit wide TX data register.
It is possible to write 8 bits into the register in burst mode and the
internal bit rate generator transmits the bits out with the predefined
rate.
It is also possible to store the received data bits into a FIFO register
and read them out in a buffered mode.
3
IA4420
PACKAGE PIN DEFINITIONS
Pin type key: D=digital, A=analog, S=supply, I=input, O=output, IO=input/output
SDI
SCK
nSEL
SDO
nIRQ
FSK / DATA / nFFS
DCLK / CFIL / FFIT
CLK
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
SDI
SCK
nSEL
SDO
nIRQ
FSK
DATA
nFFS
DLCK
CFIL
Type
DI
DI
DI
DO
DO
DI
DO
DI
DO
AIO
FFIT
DO
CLK
XTL
REF
nRES
VSS
RF2
RF1
VDD
ARSSI
nINT
VDI
DO
AIO
AIO
DIO
S
AIO
AIO
S
AO
DI
DO
nINT / VDI
ARSSI
VDD
RF1
RF2
VSS
nRES
XTL / REF
Function
Data input of the serial control interface (SPI compatible)
Clock input of the serial control interface
Chip select input of the serial control interface (active low)
Serial data output with bus hold
Interrupt request output (active low)
Transmit FSK data input
Received data output (FIFO not used)
FIFO select input (active low) In FIFO mode, when bit ef is set in Configuration Setting Command
Received data clock output (Digital filter used, FIFO not used)
External data filter capacitor connection (Analog filter used)
FIFO interrupt (active high) Number of the bits in the RX FIFO that reach the preprogrammed limit
In FIFO mode, when bit ef is set in Configuration Setting Command
Microcontroller clock output
Crystal connection (the other terminal of crystal to VSS) or external reference input
External reference input. Use 33 pF series coupling capacitor
Open drain reset output with internal pull-up and input buffer (active low)
Ground reference voltage
RF differential signal input/output
RF differential signal input/output
Positive supply voltage
Analog RSSI output
Interrupt input (active low)
Valid data indicator output
Note: The actual mode of the multipurpose pins (pin 6 and 7) is determined by the TX/RX data I/O settings of the
transceiver.
4
IA4420
Typical Application
Typical application with FIFO usage
VCC
Microcontroller
C1
1u
P7
P6
P5
P4
P3
P2
P1
P0
CLKin
nRES
VDI
SDI
C2
100p
C3
10p
(optional)
16
15
1
SCK
nSEL
2
3
SDO
nIRQ
4
5
nFFS
FFIT
(optional)
(optional)
CLK
(optional)
nRES
(optional)
6
7
8
Transmit mode
el=0 in Configuration Setting Command
Transmit mode
el=1 in Configuration Setting Command
Receive mode
ef=0 in Configuration Setting Command
Receive mode
ef=1 in Configuration Setting Command
(optional)
C4
2.2n
TP
14
IA4420
13
12
11
10
9
X1
10MHz
PCB
Antenna
Pin 6
Pin 7
TX Data input
-
Connect to logic high
-
RX Data output
RX Data clock output
nFFS input
FFIT output
5
IA4420
GENERAL DEVICE SPECIFICATION
All voltages are referenced to Vss, the potential on the ground reference pin VSS.
Absolute Maximum Ratings (non-operating)
Symbol
Vdd
Vin
Voc
Iin
ESD
Tst
Tld
Parameter
Positive supply voltage
Voltage on any pin (except RF1 and RF2)
Voltage on open collector outputs (RF1, RF2)
Input current into any pin except VDD and VSS
Min
-0.5
-0.5
-0.5
-25
Max
6
Vdd+0.5
Vdd+1.5 (Note 1)
25
Electrostatic discharge with human body model
Storage temperature
-55
1000
125
o
260
o
Lead temperature (soldering, max 10 s)
Units
V
V
V
mA
V
C
C
Recommended Operating Range
Symbol
Vdd
VocDC
VocAC
Top
Parameter
Positive supply voltage
DC voltage on open collector outputs (RF1, RF2)
AC peak voltage on open collector outputs (RF1, RF2)
Ambient operating temperature
Min
2.2
Vdd-1.5 (Note 1)
-40
Max
5.4
Vdd+1.5 (Note 2)
Vdd+1.5
85
Units
V
V
V
o
C
No
Notte 1: At maximum, Vdd+1.5 V cannot be higher than 7 V. At minimum, Vdd - 1.5 V cannot be lower than 1.2 V.
No
Notte 2: At maximum, Vdd+1.5 V cannot be higher than 5.5 V.
6
IA4420
ELECTRICAL SPECIFICATION
(Min/max values are valid over the whole recommended operating range. Typical conditions: Top = 27 oC; Vdd = Voc = 2.7 V)
DC Characteristics
Symbol
Parameter
Idd_TX_0
Supply current
(TX mode, Pout = 0 dBm)
Idd_TX_PMAX
Supply current
(TX mode, Pout = Pmax)
Idd_RX
Ipd
Ilb
Supply current
(RX mode)
Standby current (Sleep mode)
Low battery voltage detector current
consumption
Iwt
Wake-up timer current consumption
Ix
Idle current
Vlb
Low battery detect threshold
Vlba
Low battery detection accuracy
Vil
Digital input low level voltage
Vih
Digital input high level voltage
Conditions/Notes
315/433 MHz bands
868 MHz band
915 MHz band
315/433 MHz bands
Typ
13
16
17
21
Max
14
18
19
22
Units
868 MHz band
23
25
mA
915 MHz band
315/433 MHz bands
868 MHz band
915 MHz band
All blocks disabled
24
11
12
13
0.3
26
13
14
15
Crystal oscillator and baseband
parts are on
Programmable in 0.1 V steps
Min
mA
mA
µA
0.5
µA
1.5
µA
3
2.2
3.5
mA
5.3
V
+/-75
mV
0.3*Vdd
0.7*Vdd
V
V
Iil
Digital input current
Vil = 0 V
-1
1
µA
Iih
Digital input current
Vih = Vdd, Vdd = 5.4 V
-1
1
µA
Vol
Digital output low level
I ol = 2 mA
0.4
V
Voh
Digital output high level
I oh = -2 mA
Vdd-0.4
V
7
IA4420
AC Characteristics (PLL parameters)
Symbol
fref
Parameter
PLL reference frequency
fo
Receiver LO/Transmitter carrier
frequency
tlock
PLL lock time
tst, P
PLL startup time
Conditions/Notes
(Note 1)
315 MHz band, 2.5 kHz resolution
433 MHz band, 2.5 kHz resolution
868 MHz band, 5.0 kHz resolution
915 MHz band, 7.5 kHz resolution
Frequency error < 1kHz
after 10 MHz step
With a running crystal oscillator
Min
8
310.24
430.24
860.48
900.72
Typ
10
Max
12
319.75
439.75
879.51
929.27
20
Units
MHz
MHz
us
250
us
Max
75
150
225
300
375
450
115.2
Units
256
kbps
-100
dBm
AC Characteristics (Receiver)
Symbol
Parameter
BW
Receiver bandwidth
BR
FSK bit rate
Conditions/Notes
mode 0
mode 1
mode 2
mode 3
mode 4
mode 5
With internal digital filters
BRA
Pmin
FSK bit rate
With analog filter
Receiver Sensitivity
AFCrange
AFC locking range
BER 10-3, BW=67 kHz, BR=1.2 kbps (Note 2)
dfFSK: FSK deviation in the received signal
IIP3inh
Input IP3
IIP3outh
Input IP3
IIP3inl
IIP3 (LNA –6 dB gain)
IIP3outl
IIP3 (LNA –6 dB gain)
Pmax
Maximum input power
Cin
RSa
RF input capacitance
RSSI accuracy
RSr
RSSI range
CARSSI
Filter capacitor for ARSSI
RSstep
RSSI programmable level steps
RSresp
DRSSI response time
Min
60
120
180
240
300
360
Typ
67
134
200
270
350
400
0.6
-109
0.8*dfFSK
kHz
kbps
In band interferers in high bands (868, 915 MHz)
Out of band interferers
l f-fo l > 4 MHz
-21
dBm
-18
dBm
In band interferers in low bands (315, 433 MHz)
Out of band interferers
l f-fo l > 4 MHz
-15
dBm
-12
dBm
LNA: high gain
0
dBm
1
pF
+/-5
dB
46
dB
1
Until the RSSI signal goes high after the input signal
exceeds the preprogrammed limit CARRSI = 5 nF
nF
6
dB
500
us
All notes for tables above are on page 10.
8
IA4420
AC Characteristics (Transmitter)
Symbol
IOUT
Pmax
Pout
Psp
Co
Qo
Parameter
Conditions/Notes
Min
Open collector output DC current
Programmable
0.5
Available output power with optimal
antenna impedance
(Note 3, 4)
In low bands
8
In high bands
4
Typical output power
Spurious emission
Output capacitance
(set by the automatic antenna tuning
circuit)
Quality factor of the output
capacitance
Lout
Output phase noise
BR
dffsk
FSK bit rate
FSK frequency deviation
Typ
Max
Units
6
mA
dBm
Selectable in 3 dB steps (Note 5)
At max power with loop antenna
(Note 6)
In low bands
Pmax-21
Pmax
dBm
-50
dBc
2
2.6
3.2
In high bands
2.1
2.7
3.3
In low bands
In high bands
100 kHz from carrier
1 MHz from carrier
13
8
15
10
-75
-85
17
12
Programmable in 15 kHz steps
15
pF
dBc/Hz
256
kbps
240
kHz
Max
5
Units
ms
AC Characteristics (Turn-on/Turnaround timings)
Symbol
tsx
Parameter
Crystal oscillator startup time
Conditions/Notes
Crystal ESR < 100
Min
Typ
Ttx_rx_XTAL_ON
Transmitter - Receiver turnover time
Synthesizer off, crystal oscillator on during
TX/RX change with 10 MHz step
450
us
Trx_tx_XTAL_ON
Receiver - Transmitter turnover time
Synthesizer off, crystal oscillator on during
RX/TX change with 10 MHz step
350
us
Ttx_rx_SYNT_ON
Transmitter - Receiver turnover time
Synthesizer and crystal oscillator on
during TX/RX change with 10 MHz step
425
us
Trx_tx_SYNT_ON
Receiver - Transmitter turnover time
Synthesizer and crystal oscillator on
during RX/TX change with 10 MHz step
300
us
AC Characteristics (Others)
Symbol
Cxl
Parameter
Crystal load capacitance,
see crystal selection guide
tPOR
Internal POR timeout
tPBt
Wake-up timer clock period
Cin, D
Digital input capacitance
tr, f
Digital output rise/fall time
Conditions/Notes
Programmable in 0.5 pF steps, tolerance
+/- 10%
After Vdd has reached 90% of final value
(Note 7)
Calibrated every 30 seconds
15 pF pure capacitive load
Min
8.5
0.95
Typ
Max
Units
16
pF
100
ms
1.05
ms
2
pF
10
ns
All notes for tables above are on page 10.
9
IA4420
AC Characteristics (continued)
Note 1: Not using a 10 MHz crystal is allowed but not recommended because all crystal referred timing and frequency parameters will
change accordingly.
Note 2: See the BER diagrams in the measurement results section for detailed information (Not available at this time).
Note 3: See matching circuit parameters and antenna design guide for information.
Note 4: Optimal antenna admittance/impedance:
IA4420
315 MHz
433 MHz
868 MHz
915 MHz
Yantenna [S]
1.5E-3 - j5.14E-3
1.4E-3 - j7.1E-3
2E-3 - j1.5E-2
2.2E-3 - j1.55E-2
Zantenna [Ohm]
52 + j179
27 + j136
8.7 + j66
9 + j63
Lantenna [nH]
98.00
52.00
12.50
11.20
Note 5: Adjustable in 8 steps.
Note 6: With selective resonant antennas (see: Application Notes available from http://www.integration.com).
No
Nott e 7
7:: During this period, commands are not accepted by the chip.
10
IA4420
CONTROL INTERFACE
Commands to the transmitter are sent serially. Data bits on pin SDI are shifted into the device upon the rising edge of the clock on pin SCK
whenever the chip select pin nSEL is low. When the nSEL signal is high, it initializes the serial interface. All commands consist of a command
code, followed by a varying number of parameter or data bits. All data are sent MSB first (e.g. bit 15 for a 16-bit command). Bits having no
influence (don’t care) are indicated with X. The Power On Reset (POR) circuit sets default values in all control and command registers.
The receiver will generate an interrupt request (IT) for the microcontroller - by pulling the nIRQ pin low - on the following events:
·
·
·
·
·
·
·
The TX register is ready to receive the next byte (RGIT)
The FIFO has received the preprogrammed amount of bits (FFIT)
Power-on reset (POR)
FIFO overflow (FFOV) / TX register underrun (RGUR)
Wake-up timer timeout (WKUP)
Negative pulse on the interrupt input pin nINT (EXT)
Supply voltage below the preprogrammed value is detected (LBD)
FFIT and FFOV are applicable when the FIFO is enabled. RGIT and RGUR are applicable only when the TX register is enabled. To identify
the source of the IT, the status bits should be read out.
Timing Specification
Symbol
Parameter
Minimum Value [ns]
tCH
Clock high time
25
tCL
Clock low time
25
tSS
Select setup time (nSEL falling edge to SCK rising edge)
10
tSH
Select hold time (SCK falling edge to nSEL rising edge)
10
tSHI
Select high time
25
tDS
Data setup time (SDI transition to SCK rising edge)
5
tDH
Data hold time (SCK rising edge to SDI transition)
5
tOD
Data delay time
10
tBL
Push-button input low time
25
Timing Diagram
tSHI
tSS
nSEL
tCH
tOD
tCL
tSH
SCK
tDS
tDH
SDI
BIT 15
SDO
FFIT
BIT 14
FFOV
BIT 13
BIT 8
CRL
BIT 7
AT S
BIT 1
OFFS(0)
BIT 0
FIFO OUT
11
IA4420
Control Commands
Control Command
Related Parameters/Functions
Frequency band, crystal oscillator load capacitance,
baseband filter bandwidth, etc.
Receiver/Transmitter mode change, synthesizer, xtal
osc, PA, wake-up timer, clock output can be enabled
here
Data frequency of the local oscillator/carrier signal
Bit rate
Function of pin 16, Valid Data Indicator, baseband bw,
LNA gain, digital RSSI threshold
Data filter type, clock recovery parameters
Data FIFO IT level, FIFO start control, FIFO enable and
FIFO fill enable
Related control bits
1
Configuration Setting Command
2
Power Management Command
3
4
Frequency Setting Command
Data Rate Command
5
Receiver Control Command
6
Data Filter Command
7
FIFO and Reset Mode Command
8
Receiver FIFO Read Command
RX FIFO can be read with this command
9
10
11
12
13
AFC Command
TX Configuration Control Command
Transmitter Register Write Command
Wake-Up Timer Command
Low Duty-Cycle Command
Low Battery Detector and Microcontroller
Clock Divider Command
Status Read Command
AFC parameters
Modulation parameters, output power, ea
TX data register can be written with this command
Wake-up time period
Enable low duty-cycle mode. Set duty-cycle.
a1 to a0, rl1 to rl0, st, fi, oe, en
mp, m3 to m0, p2 to p0
t7 to t0
r4 to r0, m7 to m0
d6 to d0, en
LBD voltage and microcontroller clock division ratio
d2 to d0, v4 to v0
14
15
el, ef, b1 to b0, x3 to x0
er, ebb, et, es, ex, eb, ew, dc
f11 to f0
cs, r6 to r0
p16, d1 to d0, i2 to i0, g1 to g0, r2 to
r0
al, ml, s1 to s0, f2 to f0
f3 to f0, s1 to s0, ff, fe
Status bits can be read out
In general, setting the given bit to one will activate the related function. In the following tables, the POR column shows the default values of the
command registers after power-on.
Description of the Control Commands
1. Configuration Setting Command
Bit
15
1
14
0
13
0
12
0
11
0
10
0
9
0
8
0
7
el
6
ef
5
b1
4
b0
3
x3
2
x2
1
x1
0
x0
POR
8008h
Bit el enables the internal data register. If the data register is used the FSK pin must be connected to logic high level.
Bit ef enables the FIFO mode. If ef=0 then DATA (pin 6) and DCLK (pin 7) are used for data and data clock output.
b1
0
0
1
1
b0
0
1
0
1
Frequency Band {MHz]
315
433
868
915
x3
0
0
0
0
x2
0
0
0
0
x1
0
0
1
1
x0
0
1
0
1
Crystal Load Capacitance [pF]
8.5
9.0
9.5
10.0
…
1
1
1
1
1
1
0
1
15.5
16.0
12
IA4420
2. Power Management Command
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POR
1
0
0
0
0
0
1
0
er
ebb
et
es
ex
eb
ew
dc
8208h
Function of the control bit
Enables the whole receiver chain
The receiver baseband circuit can be separately
switched on
Switches on the PLL, the power amplifier, and starts
the transmission (If TX register is enabled)
Turns on the synthesizer
Turns on the crystal oscillator
Enables the low battery detector
Enables the wake-up timer
Disables the clock output (pin 8)
Bit
er
ebb
et
es
ex
eb
ew
dc
Related blocks
RF front end, baseband, synthesizer, oscillator
Baseband
Power amplifier, synthesizer, oscillator
Synthesizer
Crystal oscillator
Low battery detector
Wake-up timer
Clock output buffer
The ebb, es, and ex bits are provided to optimize the TX to RX or RX to TX turnaround time.
Logic connections between power control bits:
enable
power amplifier
et
start TX
Edge
detector
clear TX latch
(If TX latch is used)
es
enable
RF synthesizer
(osc.must be on)
er
enable
RF front end
enable baseband
circuits
ebb
(synt. must be on)
enable
oscillator
ex
13
IA4420
3. Frequency Setting Command
Bit
15
1
14
0
13
1
12
0
11
f11
10
f10
9
f9
8
f8
7
f7
6
f6
5
f5
4
f4
3
f3
2
f2
1
f1
0
f0
POR
A680h
The constants C1 and C2 are
determined by the selected
band as:
The 12-bit parameter F (bits f11 to f0) should be in
the range of 96 and 3903. When F value sent is out
of range, the previous value is kept. The synthesizer
center frequency f0 can be calculated as:
f0 = 10 * C1 * (C2 + F/4000) [MHz]
Band [MHz]
315
433
868
915
C1
1
1
2
3
C2
31
43
43
30
4. Data Rate Command
Bit
15
1
14
1
13
0
12
0
11
0
10
1
9
1
8
0
7
cs
6
r6
5
r5
4
r4
3
r3
2
r2
1
r1
0
r0
POR
C623h
The actual bit rate in transmit mode and the expected bit rate of the received data stream in receive mode is determined by the 7-bit
parameter R (bits r6 to r0) and bit cs.
BR = 10000 / 29 / (R+1) / (1+cs*7) [kbps]
In the receiver set R according to the next function:
R= (10000 / 29 / (1+cs*7) / BR) – 1, where BR is the expected bit rate in kbps.
Apart from setting custom values, the standard bit rates from 600 bps to 115.2 kbps can be approximated with small error.
Data rate accuracy requirements:
Clock recovery in slow mode: ∆BR/BR < 1/(29*Nbit)
Clock recovery in fast mode: ∆BR/BR < 3/(29*Nbit)
BR is the bit rate set in the receiver and ∆BR is the bit rate difference between the transmitter and the receiver. Nbit is the maximal number
of consecutive ones or zeros in the data stream. It is recommended for long data packets to include enough 1/0 and 0/1 transitions, and be
careful to use the same division ratio in the receiver and in the transmitter.
5. Receiver Control Command
Bit
15
1
14
0
13
0
12
1
11
0
10
p16
9
d1
8
d0
7
i2
6
i1
5
i0
4
g1
3
g0
2
r2
1
r1
0
r0
POR
9080h
Bit 10 (p16): pin16 function select
p16
0
1
Function of pin 16
Interrupt input
VDI output
14
IA4420
Bits 9-8 (d1 to d0): VDI (valid data indicator) signal response time setting:
d1
0
0
1
1
d0
0
1
0
1
Response
Fast
Medium
Slow
Always on
CR_LOCK
DQD
d0
CR_LOCK
d1
DRSSI
MEDIUM
FAST
SLOW
DQD
LOGIC HIGH
SEL0
SEL1
IN0
IN1
Y
VDI
IN2
IN3
MUX
DRSSI
DQD
CR_LOCK
SET
Q
R/S FF
CLR
Bits 7-5 (i2 to i0): Receiver baseband bandwidth (BW) select:
i2
0
0
0
0
1
1
1
1
i1
0
0
1
1
0
0
1
1
i0
0
1
0
1
0
1
0
1
BW [kHz]
reserved
400
340
270
200
134
67
reserved
15
IA4420
Bits 4-3 (g1 to g0): LNA gain select:
g1
0
0
1
1
g0
0
1
0
1
relative to maximum [dB]
0
-6
-14
-20
Bits 2-0 (r2 to r0): RSSI detector threshold:
r2
0
0
0
0
1
1
1
1
r1
0
0
1
1
0
0
1
0
r0
0
1
0
1
0
1
0
1
RSSIsetth [dBm]
-103
-97
-91
-85
-79
-73
-67
-61
The RSSI threshold depends on the LNA gain, the real RSSI threshold can be calculated:
RSSIth=RSSIsetth+GLNA
6. Data Filter Command
Bit
15
1
14
1
13
0
12
0
11
0
10
0
9
1
8
0
7
al
6
ml
5
1
4
s
3
1
2
f2
1
f1
0
f0
POR
C22Ch
Bit 7 (al): Clock recovery (CR) auto lock control, if set.
CR will start in fast mode, then after locking it will automatically switch to slow mode.
Bit 6 (ml): Clock recovery lock control
1: fast mode, fast attack and fast release (6 to 8 bit preamble (1010...) is recommended)
0: slow mode, slow attack and slow release (12 to 16 bit preamble is recommended)
Using the slow mode requires more accurate bit timing (see Data Rate Command).
Bits 4 (s): Select the type of the data filter:
s
0
1
Filter Type
Digital filter
Analog RC filter
Digital: This is a digital realization of an analog RC filter followed by a comparator with hysteresis. The time constant is automatically
adjusted to the bit rate defined by the Data Rate Command.
Note: Bit rate can not exceed 115 kpbs in this mode.
Analog RC filter: The demodulator output is fed to pin 7 over a 10 kOhm resistor. The filter cut-off frequency is set by the external
capacitor connected to this pin and VSS.
C = 1 / (3 * R * Bit Rate), therefore the suggested value for 9600 bps is 3.3 nF
Note: If analog RC filter is selected the internal clock recovery circuit and the FIFO can not be used.
16
IA4420
Bits 2-0 (f2 to f0): DQD threshold parameter.
Note
Note: To let the DQD report "good signal quality" the threshold parameter should be less than 4 in the case when
the bitrate is close to the deviation. At higher deviation/bitrate settings higher threshold parameter can report
"good signal quality" as well.
7. FIFO and Reset Mode Command
Bit
15
1
14
1
13
0
12
0
11
1
10
0
9
1
8
0
7
f3
6
f2
5
f1
4
f0
3
0
2
al
1
ff
0
dr
POR
CA80h
Bits 7-4 (f4 to f0): FIFO IT level. The FIFO generates IT when the number of received data bits reaches this level.
Bit 2 (al): Set the input of the FIFO fill start condition:
al
0
1
Synchron pattern
Always fill
Note: Synchron pattern in microcontroller mode is 2DD4h.
FIFO_LOGIC
al
FIFO_WRITE _EN
FFOV
SYNCHRON
PATTERN
ff
FFIT
ef*
nFIFO_RESET
er**
Note:
* For details see the Configuration Setting Command
** For deatils see the Power Management Command
Bit 1 (ff): FIFO fill will be enabled after synchron pattern reception. The FIFO fill stops when this bit is cleared.
Bit 0 (dr): Disables the highly sensitive RESET mode. If this bit is cleared, a 200 mV glitch in the power supply may cause a system reset.
No
Notte: To restart the synchron pattern recognition, bit 1 should be cleared and set.
17
IA4420
8. Receiver FIFO Read Command
Bit
15
1
14
0
13
1
12
1
11
0
10
0
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
POR
B000h
With this command, the controller can read 8 bits from the receiver FIFO. Bit 6 (ef) must be set in Configuration Setting Command.
nSEL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
SDI
received bits out
SDO
MSB
FFIT in RX mode / RGIT otherwise
LSB
Note: The transceiver is in receive (RX) mode when bit er is set using the Power Management Command
9. AFC Command
Bit
15
1
14
1
13
0
12
0
11
0
10
1
9
0
8
0
7
a1
6
a0
5
rl1
4
rl0
3
st
2
fi
1
oe
0
en
POR
C4F7h
Bit 7-6 (a1 to a0): Automatic operation mode selector:
a1
a0
0
0
Auto mode off (Strobe is controlled by microcontroller)
0
1
1
0
Runs only once after each power-up
Keep the foffset only during receiving (VDI=high)
1
1
Keep the foffset value independently from the state of the VDI signal
Bit 5-4 (rl1 to rl0): Range limit. Limits the value of the frequency offset register to the next values:
rl1
0
0
1
1
rl0
0
1
0
1
Max deviation
No restriction
+15 fres to -16 fres
+7 fres to -8 fres
+3 fres to -4 fres
fres:
315, 433 MHz bands: 2.5 kHz
868 MHz band: 5 kHz
915 MHz band: 7.5 kHz
Bit 3 (st): Strobe edge, when st goes to high, the actual latest calculated frequency error is stored into the offset register of the AFC block.
Bit 2 (fi): Switches the circuit to high accuracy (fine) mode. In this case, the processing time is about twice longer, but the measurement
uncertainty is about the half.
Bit 1 (oe): Enables the frequency offset register. It allows the addition of the offset register to the frequency control word of the PLL.
Bit 0 (en): Enables the calculation of the offset frequency by the AFC circuit.
18
IA4420
ATGL**
BASEBAND SIGNAL IN
ASAME***
FINE
fi
SEL
Y
10MHz CLK
CLK
/4
DIGITAL AFC
I1
MUX
7
ENABLE CALCULATION
en
CORE LOGIC
VDI*
a1 to a0
DIGITAL LIMITER
7 BIT
IF IN>MaxDEV THEN
OUT=MaxDEV
FREQ.
OFFSET
REGISTER
OFFS
<6:0>
12 BIT
I0
7
ADDER
Fcorr<11:0>
Corrected frequency
parameter to
synthesizer
IF IN<MinDEV THEN
OUT=MinDEV
AUTO OPERATION
ELSE
OUT=IN
singals for auto
operation modes
Power-on reset
(POR)
CLK CLR
RANGE LIMIT
rl1 to rl0
strobe
st
STROBE
oe
F<11:0>
OUTPUT ENABLE
output enable
NOTE:
* VDI (valid data indicator) is an internal signal of the
controller. See the Receiver Setting Command for details.
** ATGL: toggling in each measurement cycle
*** ASAME: logic high when the result is stable
Parameter from
Frequency control word
Note: Lock bit is high when the AFC loop is locked, f_same bit indicates when two subsequent measuring results are the same, toggle bit
changes state in every measurement cycle.
In automatic operation mode (no strobe signal is needed from the microcontroller to update the output offset register) the AFC circuit is
automatically enabled when the VDI indicates potential incoming signal during the whole measurement cycle and the circuit measures the
same result in two subsequent cycles.
There are three operation modes, example from the possible application:
1, (a1=0, a0=1) The circuit measures the frequency offset only once after power up. In this way extended TX-RX maximum distance can be
achieved.
Possible application:
In the final application, when the user inserts the battery, the circuit measures and compensates for the frequency offset caused by the crystal
tolerances. This method allows for the use of a cheaper quartz in the application and provides protection against tracking an interferer.
2a, (a1=1, a0=0) The circuit automatically measures the frequency offset during an initial effective low data rate pattern –easier to receive(i.e.: 00110011) of the package and changes the receiving frequency accordingly. The further part of the package can be received by the
corrected frequency settings.
2b, (a1=1, a0=0) The transmitter must transmit the first part of the packet with a step higher deviation and later there is a possibility to reduce
it.
In both cases (2a and 2b), when the VDI indicates poor receiving conditions (VDI goes low), the output register is automatically cleared. Use
these settings when receiving signals from different transmitters transmitting in the same nominal frequencies.
3, (a1=1, a0=1) It’s the same as 2a and 2b modes, but suggested to use when a receiver operates with only one transmitter. After a complete
measuring cycle, the measured value is kept independently of the state of the VDI signal.
10. TX Configuration Control Command
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POR
1
0
0
1
1
0
0
mp
m3
m2
m1
m0
0
p2
p1
p0
9800h
19
IA4420
Bits 8-4 (mp, m3 to m0): FSK modulation parameters:
The resulting output frequency can be calculated as:
Pout
fout = f0 + (-1) SIGN * (M + 1) * (15 kHz)
where:
f0 is the channel center frequency (see the
Frequency Setting Command)
M is the four bit binary number <m3 : m0>
SIGN = (mp) XOR (FSK input)
df fsk
df fsk
f out
f0
Bits 2-0 (p2 to p0): Output power:
p2
p1
p0
Relative Output Power [dB]
0
0
0
0
0
1
0
-3
0
0
1
1
0
1
-6
-9
1
1
1
1
0
0
1
1
0
1
0
1
-12
-15
-18
-21
mp=0 and FSK=0
or
mp=1 and FSK=1
mp=0 and FSK=1
or
mp=1 and FSK=0
The output power given in the table is relative to the maximum available power, which depends on the actual antenna impedance.
(See: Antenna Application Note: IA ISM-AN1)
11. Transmitter Register Write Command
Bit
15
1
14
0
13
1
12
1
11
1
10
0
9
0
8
0
7
t7
6
t6
5
t5
4
t4
3
t3
2
t2
1
t1
0
t0
POR
B8AAh
With this command, the controller can write 8 bits (t7 to t0) to the transmitter data register. Bit 7 (el) must be set in Configuration Setting
Command.
12. Wake-Up Timer Command
Bit
15
1
14
1
13
1
12
r4
11
r3
10
r2
9
r1
8
r0
7
m7
6
m6
5
m5
4
m4
3
m3
2
m2
1
m1
0
m0
POR
E196h
The wake-up time period can be calculated by (m7 to m0) and (r4 to r0):
Twake-up = M * 2R [ms]
Note:
• For continual operation the et bit should be cleared and set at the end of every cycle.
• For future compatibility, use R in a range of 0 and 29.
20
IA4420
13. Low Duty-Cycle Command
Bit
15
1
14
1
13
0
12
0
11
1
10
0
9
0
8
0
7
d6
6
d5
5
d4
4
d3
3
d2
2
d1
1
d0
0
en
POR
C80Eh
With this command, Low Duty-Cycle operation can be set in order to decrease the average power consumption in receiver mode.
The time cycle is determined by the Wake-Up Timer Command.
The Duty-Cycle can be calculated by using (d6 to d0) and M. (M is parameter in a Wake-Up Timer Command.)
Duty-Cycle= (D * 2 +1) / M *100%
Xtal osc.
enable
Receiver
On
2.25ms
2.25ms
Ton
Ton
Ton
Twake-up
Twake-up
Twake-up
DQD
Bit 0 (en): Enables the Low Duty-Cycle Mode. Wake-up timer interrupt not generated in this mode.
Note: In this operation mode, bit er must be cleared and bit ew must be set in the Power Management Command.
14. Low Battery Detector and Microcontroller Clock Divider Command
Bit
15
1
14
1
13
0
12
0
11
0
10
0
9
0
8
0
7
d2
6
d1
5
d0
4
v4
3
v3
2
v2
1
v1
0
v0
POR
C000h
The 5 bit parameter (v4 to v0) represents the value V, which defines the threshold voltage Vlb of the detector:
Vlb= 2.2 + V * 0.1 [V]
Clock divider configuration:
d2
d1
d0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Clock O utput
Frequency [ M H z]
1
1.25
1.66
2
2.5
3.33
5
10
The low battery detector and the clock output can be enabled or disabled by bits eb and dc, respectively, using the Power Management
Command.
21
IA4420
15. Status Read Command
The read command starts with a zero, whereas all other control commands start with a one. If a read command is identified, the status bits
will be clocked out on the SDO pin as follows:
Status Register Read Sequence with FIFO Read Example:
nSEL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
SCK
command
SDI
interrupt bits out
SDO
FFIT*
RGIT**
POR
FFOV*
WKUP
RGUR**
status bits out
EXT
LBD
FFEM
RSSI*
ATS**
DQD
CRL
ATGL
(Latched) (Latched) (Latched) (Latched) (Latched)
OFFS<6> OFFS<3> OFFS<2> OFFS<1> OFFS<0>
FIFO out
FO
FO+1
FO+2
(Sign)
Notes: * Applicable when the transceiver is in receive (RX) mode i.e. bit er is set using the Power Management Command
** Applicable when bit er is cleared using the Power Management Command
Bits marked are internally latched, the others are only multiplexed out
RGIT
TX register is ready to receive the next byte (Can be cleared by Transmitter Register Write Command )
FFIT
The number of data bits in the RX FIFO has reached the pre-programmed limit (Can be cleared by any of the FIFO read methods)
POR
Power-on reset (Cleared after Status Read Command )
RGUR
TX register under run, register over write (Cleared after Status Read Command )
FFOV
RX FIFO overflow (Cleared after Status Read Command )
WKUP
Wake-up timer overflow (Cleared after Status Read Command )
EXT
Logic level on interrupt pin (pin 16) changed to low (Cleared after Status Read Command )
LBD
Low battery detect, the power supply voltage is below the pre-programmed limit
FFEM
ATS
FIFO is empty
Antenna tuning circuit detected strong enough RF signal
RSSI
The strength of the incoming signal is above the pre-programmed limit
DQD
Data quality detector output
CRL
Clock recovery locked
ATGL
OFFS(6)
OFFS(3) -OFFS(0)
Toggling in each AFC cycle
MSB of the measured frequency offset (sign of the offset value)
Offset value to be added to the value of the frequency control parameter (Four LSB bits)
22
IA4420
TX REGISTER BUFFERED DATA TRANSMISSION
In this operating mode (enabled by bit el, the Configuration Control Command) the TX data is clocked into one of the two 8-bit data registers.
The transmitter starts to send out the data from the first register (with the given bit rate) when bit et is set with the Power Management
Command. The initial value of the data registers (AAh) can be used to generate preamble. During this mode, the SDO pin can be monitored to
check whether the register is ready (SDO is high) to receive the next byte from the microcontroller.
TX register simplified block diagram (before transmit)
et=0
(register initial
fillup)
Di
CLK
Serial bus data
Di
Serial bus clk
CLK
8 bit shift register
(default: AAh)
Do
8 bit shift register
(default: AAh)
Do
TX_DATA
TX register simplified block diagram (during transmit)
et=1
(during TX)
Di
SEL
Bit rate
8 bit shift register
Do
CLK
Y
I0
I1
MUX
SEL
Y
I0
1:8
MUX
divider
Di
SEL
8 bit shift register
Do
CLK
Y
Serial bus
clk
TX_DATA
I1
I0
I1
MUX
Serial bus
data
Typical TX register usage
SPI commands
Conf. cnt.
TX latch wr
TX latch wr
Power Man
TX latch wr
TX latch wr
Power Man
el=1
TX byte1
TX byte2
et=1
TX byte3
Dummy
TX byte
et=0
(nSEL, SCK, SDI)
et bit
(enable transmitter)
enable
Synthesizer / PA
TX data
Synt.
PA
tsp*
80us
TX byte1
TX byte2
TX byte3 Dummy byte
nIRQ
SDO**
Note:
*tsp is the start-up time of the PLL
** SDO is tri-state if nSEL is logic high.
Note: The content of the data registers are initialized by clearing bit et.
23
IA4420
RX FIFO BUFFERED DATA READ
In this operating mode, incoming data are clocked into a 16 bit FIFO buffer. The receiver starts to fill up the FIFO when the Valid Data Indicator
(VDI) bit and the synchron pattern recognition circuit indicates potentially real incoming data. This prevents the FIFO from being filled with
noise and overloading the external microcontroller.
Polling Mode:
The nFFS signal selects the buffer directly and its content can be clocked out through pin SDO by SCK. Set the FIFO IT level to 1. In this case,
as long as FFIT indicates received bits in the FIFO, the controller may continue to take the bits away. When FFIT goes low, no more bits need
to be taken. An SPI read command is also available.
Interrupt Controlled Mode:
The user can define the FIFO level (the number of received bits) which will generate the nFFIT when exceeded. The status bits report the
changed FIFO status in this case.
FIFO Read Example with FFIT Polling
nSEL
0
1
2
3
4
SCK
nFFS
FIFO read out
SDO
FIFO OUT
FO+1
FO+2
FO+3
FO+4
FFIT
During FIFO access fSCK cannot be higher than fref /4, where fref is the crystal oscillator frequency.
24
IA4420
CRYSTAL SELECTION GUIDELINES
The crystal oscillator of the IA4420 requires a 10 MHz parallel mode crystal. The circuit contains an integrated load capacitor in order to
minimize the external component count. The internal load capacitance value is programmable from 8.5 pF to 16 pF in 0.5 pF steps. With
appropriate PCB layout, the total load capacitance value can be 10 pF to 20 pF so a variety of crystal types can be used.
When the total load capacitance is not more than 20 pF and a worst case 7 pF shunt capacitance (C0) value is expected for the crystal, the
oscillator is able to start up with any crystal having less than 300 ohms ESR (equivalent series loss resistance). However, lower C0 and ESR
values guarantee faster oscillator startup.
The crystal frequency is used as the reference of the PLL, which generates the local oscillator frequency (fLO). Therefore fLO is directly
proportional to the crystal frequency. The accuracy requirements for production tolerance, temperature drift and aging can thus be determined
from the maximum allowable local oscillator frequency error.
Whenever a low frequency error is essential for the application, it is possible to “pull” the crystal to the accurate frequency by changing the
load capacitor value. The widest pulling range can be achieved if the nominal required load capacitance of the crystal is in the “midrange”,
for example 16 pF. The “pull-ability” of the crystal is defined by its motional capacitance and C0.
Maximum XTAL Tolerances Including Temperature and Aging [ppm]
Bit Rate: 2.4kbps
Deviation [+/- kHz]
30
45
60
75
90
105
120
315 MHz
25
50
75
100
100
100
100
433 MHz
20
30
50
70
90
100
100
868 MHz
10
20
25
30
40
50
60
915 MHz
10
15
25
30
40
50
50
Bit Rate: 9.6kbps
Deviation [+/- kHz]
30
45
60
75
90
105
120
315 MHz
20
50
70
75
100
100
100
433 MHz
15
30
50
70
80
100
100
868 MHz
8
15
25
30
40
50
60
915 MHz
8
15
25
30
40
50
50
Bit Rate: 38.3kbps
Deviation [+/- kHz]
30
45
60
75
90
105
120
315 MHz
don't use
7
30
50
75
100
100
433 MHz
don't use
5
20
30
50
75
75
868 MHz
don't use
3
10
20
25
30
40
915 MHz
don't use
3
10
15
25
30
40
25
IA4420
RX-TX ALIGNMENT PROCEDURES
RX-TX frequency offset can be caused only by the differences in the actual reference frequency. To minimize these errors it is suggested to use
the same crystal type and the same PCB layout for the crystal placement on the RX and TX PCBs.
To verify the possible RX-TX offset it is suggested to measure the CLK output of both chips with a high level of accuracy. Do not measure the
output at the XTL pin since the measurement process itself will change the reference frequency. Since the carrier frequencies are derived from
the reference frequency, having identical reference frequencies and nominal frequency settings at the TX and RX side there should be no
offset if the CLK signals have identical frequencies.
It is possible to monitor the actual RX-TX offset using the AFC status report included in the status byte of the receiver. By reading out the status
byte from the receiver the actual measured offset frequency will be reported. In order to get accurate values the AFC has to be disabled during
the read by clearing the "en" bit in the AFC Control Command (bit 0).
TYPICAL APPLICATIONS
REPEATER DEMO (915 MHZ)
VCC
FFS
FFE
INT/VDI
ARSSI
P3.0/C2D
/RST/C2CK
VDD
820
R5
6
820
5
R6
820
4
VCC
R7
1k
C1
GND
3
100nF
SEL
3
MISO
4
IRQ
5
FFS
6
FFE
7
CLK
8
SDI
NINT/VDI
SCK
ARSSI
NSEL
VDD
SDO
RF1
NIRQ
RF2
FSK/DATA/NFFS
VSS
DCLK/CFIL
CLK
NRES
XTL/REF
INT/VDI
15
ARSSI
14
VCC
13
12
11
IA4420-REVC
GND
GND
3 TX
2 RX
1
3
2
1
J1
X1
10
9
C2
C8051F311
4,7nF
GND
Q1
10MHz
GND
GND
DEBUG
GND
IC3
BATTERY
1
2
1 IN
OUT 5
2 GND
R8
C3
2,2uF
3 ON POK 4
VCC
VCC
GND
6V
16
C8
2
GND
R4
SCK
L1
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
820
1
C9
22
21
20
19
18
17
16
15
SCK
MISO
MOSI
R3 GND
MOSI
L3
GND
IC2
5
VCC
IRQ
SW1
1
4
3
6
14
13
12
11
10
9
8
7
GND
TX
RX
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
D3
Yellow
R2
2
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
D4
Red
1
CLK
2
1
28
27
26
25
24
23
D2
Green
SJ1
D1
Red
IC1
SEL
100k
R1
VCC
Schematics
3,3V
C4
C5
C6
C7
2,2uF
1uF
100pF
10pF
IA2112-3.3V
GND
GND
26
IA4420
PCB Layout
Top View
Bottom View
27
IA4420
PACKAGE INFORMATION
16-pin TSSOP
16-pin TSSOP updated
See Detail “A”
Section B-B
Gauge Plane
0.25
Detail “A”
Symbol
A
A1
A2
b
b1
c
c1
D
e
E
E1
L
L1
R
R1
ș1
ș2
ș3
Min.
0,05
0,80
0,19
0,19
0,09
0,09
4,90
4,30
0,50
Dimensions in mm
Nom.
Max.
1,20
0,15
0,90
1,05
0,30
0,22
0,25
0,20
0,16
5,00
5,10
0.65 BSC.
6.40 BSC.
4,40
4,50
0,60
0,75
1.00 REF.
0,09
0,09
0
8
12 REF.
12 REF.
Dimensions in Inches
Nom.
Max.
0,047
0,002
0,006
0,031
0,035
0,041
0,007
0,012
0,007
0,009
0,010
0,004
0,008
0,004
0,006
0,193
0,197
0,201
0.026 BSC.
0.252 BSC.
0,169
0,173
0,177
0,020
0,024
0,030
0.39 REF.
0,004
0,004
0
8
12 REF.
12 REF.
Min.
28
IA4420
RELATED PRODUCTS AND DOCUMENTS
IA 4420 Universal ISM Band FSK Transceiver
DESCRIPTION
ORDERING NUMBER
IA 4420 16 pin TSSOP
IA 4420-IC CC16
Revision #
Demo Boards and Development Kits
DESCRIPTION
ORDERING NUMBER
Development Kit
IA ISM – DK
ISM Repeater Demo
IA ISM – DARP
Related Resources
DESCRIPTION
ORDERING NUMBER
Antenna Selection Guide
IA ISM – AN1
Antenna Development Guide
IA ISM – AN2
IA 4220/21 Universal ISM Band FSK Transmitters
see http://www.integration.com for details
IA 4320 Universal ISM Band FSK Receiver
see http://www.integration.com for details
Note: Volume orders must include chip revision to be accepted.
Integration Associates, Inc.
110 Pioneer Way, Unit L
Mountain View, California 94041
Tel: 650.969.4100
Fax: 650.969.4582
www.integration.com
[email protected]
[email protected]
P694
This document may contain preliminary information and is subject to change by
Integration Associates, Inc. without notice. Integration Associates assumes no
responsibility or liability for any use of the information contained herein. Nothing in
this document shall operate as an express or implied license or indemnity under
the intellectual property rights of Integration Associates or third parties. The products
described in this document are not intended for use in implantation or other direct
life support applications where malfunction may result in the direct physical harm
or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED
TO, THE IMPLIED WARRANTIES OF MECHANTABILITY OR FITNESS FOR A PARTICULAR
PURPOSE, ARE OFFERED IN THIS DOCUMENT.
©2005, Integration Associates, Inc. All rights reserved. Integration Associates and EZRadio are trademarks of Integration Associates,
Inc. All other trademarks belong to their respective owners.
29