Discontinued (8/99 - last order; 12/99 - last ship) IBM13T4644MPC2M x 6411/8/1, 3.3V 14. IBM13T4644MPC 4M x 64 SDRAM SO DIMM Features • 144 Pin (emerging) JEDEC Standard, 8 Byte Small Outline Dual-In-line Memory Module • 4Mx64 Synchronous DRAM SO DIMM • Performance: −10 CAS Latency Units 3 fCK Clock Frequency 100 tCK Clock Cycle 10 ns tAC Clock Access Time 7 ns MHz • Inputs and outputs are LVTTL (3.3V) compatible • • • • • Single 3.3V ±0.3V Power Supply Single Pulsed RAS interface SDRAMs have four internal banks Fully Synchronous to positive Clock Edge Data Mask for Byte Read/Write control • Programmable Operation: - CAS Latency: 2, 3 - Burst Type: Sequential or Interleave - Burst Length: 1, 2, 4, 8, Full-Page (FullPage supports Sequential burst only) - Operation: Burst Read and Write or Multiple Burst Read with Single Write • Auto Refresh (CBR) and Self Refresh • Automatic and controlled Precharge Commands • Suspend Mode and Power Down Mode • 12/8/2 Addressing (Row/Column/Bank) • 4096 refresh cycles distributed across 64ms • Serial Presence Detect • Card size: 2.66" x 1.0" x 0.149" • Gold contacts • SDRAMS in TSOP Type II Package Description IBM13T4644MPC is a 144-pin Synchronous DRAM Small Outline Dual In-line Memory Module (SO DIMM) which is organized as a 4Mx64 high-speed memory array. The SO DIMM uses four 4Mx16 SDRAMs in 400mil TSOP II packages and achieves high speed data transfer rates of up to 100MHz by employing a prefetch/pipeline hybrid architecture that supports the JEDEC 1N rule while allowing very low burst power. The SO DIMM is intended to comply with all JEDEC standards set for 144 pin SDRAM SO DIMMs. All control, address, and data input/output circuits are synchronized with the positive edge of the externally supplied clock inputs. All inputs are sampled at the positive edge of the externally supplied clock (CK0). Internal operating modes are defined by combinations of the RAS, CAS, WE, S0, DQMB, and CKE0 signals. A command decoder initiates the necessary timings for each operation. A 14 bit address bus accepts address information in a row/column multiplexing arrangement. Prior to any access operation, the CAS latency, burst type, burst length, and burst operation type must be programmed into the SO DIMM by address inputs A0-A9 during the mode register set cycle. The SO DIMM uses serial presence detects implemented via a serial EEPROM using the two pin IIC protocol. The first 128 bytes of serial PD data are used by the DIMM manufacturer. The last 128 bytes are available to the customer. All IBM 144-pin SO DIMMs provide a high performance, flexible 8-byte interface in a 2.66" long space-saving footprint. Related products are in the EDO DRAM SO DIMM family. Card Outline (Front) (Back) 29L6293.E93850A 3/99 1 2 59 61 60 62 143 144 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 1 of 14 Discontinued (8/99 - last order; 12/99 - last ship) IBM13T4644MPC 4M x 64 SDRAM SO DIMM Pin Description CK0 Clock Input DQ0 - DQ63 Data Input/Output CKE0 Clock Enable RAS Row Address Strobe VDD Power (3.3V) CAS Column Address Strobe VSS Ground WE Write Enable NC No Connect S0 Chip Selects SCL Serial Presence Detect Clock Input Address Inputs SDA Serial Presence Detect Data Input/Output A0 - A9, A11 A10/AP DQMB0 - DQMB7 Data Mask Address Input/Autoprecharge BA0, BA1 SDRAM Bank Addresses Pinout Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side Pin# Front Side Pin# Back Side Pin# 1 3 VSS DQ0 2 4 VSS DQ32 37 39 DQ8 DQ9 38 40 DQ40 DQ41 71 73 NC NC 72 74 NC NC 107 109 5 DQ1 6 DQ33 41 DQ10 42 DQ42 75 VSS 76 VSS 111 7 DQ2 8 DQ34 43 DQ11 44 DQ43 77 NC 78 NC 113 9 DQ3 10 DQ35 45 VDD 46 VDD 79 NC 80 NC 115 11 VDD 12 VDD 47 DQ12 48 DQ44 81 VDD 82 VDD 117 13 15 17 19 21 23 25 27 29 31 33 35 DQ4 DQ5 DQ6 DQ7 VSS 14 16 18 20 22 24 26 28 30 32 34 36 DQ36 DQ37 DQ38 DQ39 VSS 49 51 53 55 57 59 DQ13 DQ14 DQ15 VSS DQ45 DQ46 DQ47 VSS 83 85 87 89 91 93 95 97 99 101 103 105 DQ16 DQ17 DQ18 DQ19 VSS 84 86 88 90 92 94 96 98 100 102 104 106 DQ48 DQ49 DQ50 DQ51 VSS 119 121 123 125 127 129 131 133 135 137 139 141 143 DQMB0 DQMB1 VDD A0 A1 A2 VSS DQMB4 DQMB5 VDD A3 A4 A5 VSS 61 63 65 67 69 50 52 54 56 NC 58 NC 60 VOLTAGE KEY CK0 62 VDD 64 RAS 66 WE 68 S0 70 NC NC CKE0 VDD CAS NC NC DQ20 DQ21 DQ22 DQ23 VDD A6 A8 DQ52 DQ53 DQ54 DQ55 VDD A7 BA0 Front Side VSS A9 A10/A P VDD DQMB 2 DQMB 3 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS SDA VDD Pin# Back Side 108 110 VSS BA1 112 A11 114 VDD DQMB 6 DQMB 7 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 SCL VDD All pin assignments are consistent for all 8 Byte versions. Ordering Information Part Number Organization Clock Cycle Leads Dimension Power IBM13T4644MPC-10T 4Mx64 10ns gold 2.66" x1.0" x 0.149" 3.3V ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 2 of 14 29L6293.E93850A 3/99 Discontinued (8/99 - last order; 12/99 - last ship) IBM13T4644MPC 4M x 64 SDRAM SO DIMM 4Mx64 SDRAM DIMM Block Diagram (x16 SDRAMs) WE S0 CS DQMB0 WE DQMB4 LDQM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB1 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D0 DQMB5 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 D2 UDQM WE DQMB6 LDQM DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB3 WE DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 CS DQMB2 CS LDQM CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D1 DQMB7 UDQM DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 WE LDQM D3 UDQM DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 10 Ohm * CLOCK WIRING CLOCK SDRAMS INPUT CK1 CK0 D0 - 3 10 pf BA0 A0 - A10, A11 VDD VSS 29L6293.E93850A 3/99 BA0-BAN: SDRAMS D0 - D3 SERIAL PD A0-AN: SDRAMS D0 - D3 D0 - D3 D0 - D3 RAS RAS: SDRAMs D0 - D3 CAS CAS: SDRAMs D0 - D3 CKE0 CKE: SDRAMs D0 - D3 SCL SDA A0 A1 A2 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 3 of 14 Discontinued (8/99 - last order; 12/99 - last ship) IBM13T4644MPC 4M x 64 SDRAM SO DIMM Input/Output Functional Description Symbol Type Signal Polarity Function CK0 Input Pulse Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of their associated clock. CKE0 Input Level Activates the CK0 signal when high and deactivates it when low. Active High By deactivating the clock, CKE0 low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. S0 Input Pulse Enables the associated SDRAM command decoder when low and disables the command Active Low decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. RAS, CAS WE Input Pulse Active Low BA0 Input Level — Selects which SDRAM bank is to be active. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. A0 - A9, A11, A10/AP Input Level — During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A7 defines the column address (CA0-CA8) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke autoprecharge operation at the end of the burst read or write cycle. If AP is high, autoprecharge is selected and BA0 defines the bank to be precharged (low=bank A, high=bank B). If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0 to control which bank(s) to precharge. If AP is high, both bank A and bank B will be precharged regardless of the state of BA0. If AP is low, then BA0 is used to define which bank to precharge. DQ0 - DQ63 Input Output Level — Data Input/Output pins operate in the same manner as on conventional DRAMs. DQMB0 DQMB7 Input VCC, VSS Supply Pulse The Data Input/Output mask places the DQ buffers in a high impedance state when sampled high. In Read mode, DQM has a latency of two clock cycles and controls the output Active High buffers like an output enable. In Write mode, DQM has a latency of zero and operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if DQM is high. Power and ground for the module. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 4 of 14 29L6293.E93850A 3/99 Discontinued (8/99 - last order; 12/99 - last ship) IBM13T4644MPC 4M x 64 SDRAM SO DIMM Serial Presence Detect Byte # Description SPD Entry Value 0 Number of Serial PD Bytes Written during Production 1 Total Number of Bytes in Serial PD device 128 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly 12 4 Number of Column Addresses on Assembly 8 5 Number of DIMM Banks 1 6-7 Data Width of Assembly x64 256 SDRAM 8 Voltage Interface Level of this Assembly LVTTL 9 SDRAM Device Cycle Time at CL=3 10.0ns 10 SDRAM Device Access Time from Clock at CL=3 11 DIMM Configuration Type 12 Refresh Rate/Type 13 Primary SDRAM Device Width x16 14 Error Checking SDRAM Device Width N/A 15 SDRAM Device Attr: Min Clk Delay, Random Col Access 16 SDRAM Device Attributes: Burst Lengths Supported 17 SDRAM Device Attributes: Number of Device Banks 4 18 SDRAM Device Attributes: CAS Latencies Supported 2, 3 19 SDRAM Device Attributes: CS Latency 0 20 SDRAM Device Attributes: WE Latency 0 21 SDRAM Module Attributes 7.0ns Non-Parity SR/1x(15.625µs) 1 Clock 1,2,4,8, Full Page Unbuffered Wr-1/Rd Burst, Precharge All, Auto-Precharge, VDD ±10% 22 SDRAM Device Attributes: General 23 Minimum Clock Cycle at CL=2 15.0ns 24 Maximum Data Access Time (tAC) from Clock at CL=2 8.0ns 25 Minimum Clock Cycle Time at CL=1 N/A 26 Maximum Data Access Time (tAC) from Clock at CL=1 N/A 27 Minimum Row Precharge Time (tRP) 30ns 28 Minimum Row Active to Row Active delay (tRRD) 20ns 29 Minimum RAS to CAS delay (tRCD) 30ns 30 Minimum RAS Pulse width (tRAS) 60ns 31 Module Bank Density 32MB 32 Address and Command Setup Time Before Clock 3.0 33 Address and Command Setup Time After Clock 1.0 34 Data Input Setup Time Before Clock 3.0 35 Data Input Hold Time After Clock 36 - 61 62 SPD Revision 63 Checksum for bytes 0 - 62 64 - 71 Manufacturers’ JEDEC ID Code 72 Module Manufacturing Location 73 - 90 Module Part Number 91 - 92 Module Revision Code 1. 2. 3. 4. 5. 6. 1.0 Reserved Undefined 02 Checksum Data IBM Toronto, Canada Vimercate, Italy ASCII ‘13T4644MP”R”-10T’ “R” plus ASCII blank Serial PD Data Entry (Hexadecimal) 80 08 04 0C 08 01 4000 01 A0 70 00 80 10 00 01 8F 04 06 01 01 00 Notes 0E F0 80 00 00 1E 14 1E 3C 08 30 10 30 10 00 02 cc A400000000000000 91 53 313354343634344D50 rr2D31305420202020 rr20 1 2, 3 2, 3 cc = Checksum Data byte, 00-FF (Hex) “R” = Alphanumeric revision code, A-Z, 0-9 rr = ASCII coded revision code byte “R” yy = Binary coded decimal year code, 00-99 (Decimal) ‘00-63 (Hex) ww = Binary coded decimal week code, 01-52 (Decimal) ‘01-34 (Hex) ss = Serial number data byte, 00-FF (Hex) 29L6293.E93850A 3/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 5 of 14 Discontinued (8/99 - last order; 12/99 - last ship) IBM13T4644MPC 4M x 64 SDRAM SO DIMM Serial Presence Detect Byte # 93 - 94 95 - 98 99 - 125 126 127 128 - 255 1. 2. 3. 4. 5. 6. Description Module Manufacturing Date Module Serial Number Reserved Module Supports this Clock Frequency Attributes for Clock Frequency defined in byte 126 Open for Customer Use SPD Entry Value Serial PD Data Entry (Hexadecimal) Year/Week Code Serial Number Undefined 66 MHz 2, 3 Undefined yyww ssssssss 00 66 06 00 Notes 4, 5 6 cc = Checksum Data byte, 00-FF (Hex) “R” = Alphanumeric revision code, A-Z, 0-9 rr = ASCII coded revision code byte “R” yy = Binary coded decimal year code, 00-99 (Decimal) ‘00-63 (Hex) ww = Binary coded decimal week code, 01-52 (Decimal) ‘01-34 (Hex) ss = Serial number data byte, 00-FF (Hex) Absolute Maximum Ratings Symbol Parameter VDD Power Supply Voltage VIN Input Voltage −0.3 to +4.6 SDRAM Devices −0.3 to +4.6 Serial PD Device −0.3 to +6.5 SDRAM Devices −0.3to +4.6 Serial PD Device −0.3 to +6.5 1 0 to +70 °C 1 -55 to +125 °C 1 Power Dissipation 0.8 W 1, 2 Short Circuit Output Current 50 mA 1 Output Voltage TOPR Operating Temperature TSTG Storage Temperature IOUT Units Notes V VOUT PD Rating 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. Power is calculated using IDD1 @ 3.6Volt. Recommended DC Operating Conditions (TA= 0 to 70°C) Rating Symbol Parameter Min. Typ. Max. Units Notes VDD Supply Voltage 3.0 3.3 3.6 V 1 VIH Input High Voltage 2.0 3.0 VDD + 0.3 V 1 VIL Input Low Voltage −0.3 0.0 0.8 V 1 1. All voltages referenced to VSS. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 6 of 14 29L6293.E93850A 3/99 Discontinued (8/99 - last order; 12/99 - last ship) IBM13T4644MPC 4M x 64 SDRAM SO DIMM Capacitance (TA= 25°C, f=1MHz, VDD= 3.3V ± 0.3V) Symbol Parameter Max. Capacitance Units CI1 Input Capacitance (A0 - A9, A10/AP, A11, BA0, BA1, RAS, CAS, WE) 37 pF CI2 Input Capacitance (CKE) 33 pF CI3 Input Capacitance (S0, S1) 34 pF CI4 Input Capacitance (CK0) 40 pF CI5 Input Capacitance (DQMB0 - DQMB7) 8 pF CI6 Input Capacitance (SCL) 12 pF CIO1 Input/Output Capacitance (DQ0 - DQ63) 12 pF CIO2 Input/Output Capacitance (SDA) 15 pF DC Output Load Circuit 3.3 V 1200 VOH (DC) = 2.4V, IOH = −2mA Output VOL (DC) = 0.4V, IOL = 2mA 870 50pF Output Characteristics (TA= 0 to +70°C, VDD= 3.3V ±0.3V) Symbol II(L) Parameter Input Leakage Current, any input (0.0V ≤ VIN ≤ VDD), All Other Pins Not Under Test = 0V Min. Max. RAS, CAS, WE, CKE0, CK0, A0-A9, A10/AP, A11, BA0, BA1 −8 +8 S0 −8 +8 DQMB0-7 −2 +2 DQ0 - 63 −2 +2 SCL −2 +2 DQ0 - 63, SDA −2 +2 IO(L) Output Leakage Current (DOUT is disabled, 0.0V ≤ VOUT ≤ VDD) VOH Output Level (LVTTL) Output “H” Level Voltage (IOUT = -2.0mA) 2.4 — VOL Output Level (LVTTL) Output “L” Level Voltage (IOUT = +2.0mA) — 0.4 Units Notes µA V 1 1. See DC output load circuit. 29L6293.E93850A 3/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 7 of 14 Discontinued (8/99 - last order; 12/99 - last ship) IBM13T4644MPC 4M x 64 SDRAM SO DIMM Operating, Standby and Refresh Currents (TA= 0 to +70°C, VDD= 3.3V ± 0.3V) Parameter Symbol Test Condition Current Units Notes IDD1 1 bank operation 220 mA 1, 2 IDD2P CKE ≤ VIL(max), tCK = min, S0 = VIH(min) 4 mA IDD2Ps CKE ≤ VIL(max), tCK = Infinity, S0 = VIH(min) 4 mA IDD2N CKE ≥ VIH(min), tCK = min, S0 = VIH (min) 100 mA 5 IDD2NS CKE ≥ VIH(min), tCK = Infinity, S0 = VIH (min) 20 mA 8 IDD3N CKE ≥ VIH(min), tCK = min, S0 = VIH (min) 120 mA 5 IDD3P CKE ≤ VIL(max), tCK = min, S0 = VIH (min) (Power Down Mode) 28 mA 7 Burst Operating Current IDD4 tCK = min, Read/ Write command cycling 360 mA 2, 6 Auto (CBR) Refresh Current IDD5 tCK = min, CBR command cycling 440 mA Self Refresh Current IDD6 CKE0 ≤ 0.2V 1.6 mA Serial PD Device Standby Current ISB5 VIN = GND or VDD 10 µA 3 Serial PD Device Active Power Supply Current ICCA SCL Clock Frequency = 100KHz 1 mA 4 Operating Current tRC = tRC(min), tCK = min Active-Precharge command cycling without Burst operation Precharge Standby Current in Power Down Mode Precharge Standby Current in NonPower Down Mode No Operating Current (Active state: 4 bank) 1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of tCK and tRC. Input signals are changed once during tCK (min). 2. The specified v(alues are obtained with the output open. 3. VDD = 3.3V. 4. Input pulse levels VDD x 0.1 to VDD x 0.9, input rise and fall times 10ns, input and output timing levels VDD x 0.5, output load 1 TTL gate and CL=100pf. 5. Input signals are changed once during three clock cycles. 6. Input signals are changed once during tCK (min). 7. Active Standby current will be higher if clock suspend is entered during a Burst Read cycle (add 1mA per DQ). 8. Input signals are stable. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 8 of 14 29L6293.E93850A 3/99 Discontinued (8/99 - last order; 12/99 - last ship) IBM13T4644MPC 4M x 64 SDRAM SO DIMM AC Characteristics (TA= 0 to +70°C, VDD= 3.3V ± 0.3V) 1. An initial pause of 100µs is required after power-up, then a Precharge All Banks command must be given followed by a minimum of two Auto (CBR) Refresh cycles before the Mode Register Set operation can begin. 2. AC timing tests have VIL = 0.8V and VIH = 2.0V with the timing referenced to the 1.40V crossover point 3. The Transition time is measured between VIH and VIL (or between VIL and VIH). 4. AC measurements assume tT=1ns. 5. In addition to meeting the transition rate specification, the clock and CKEn must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. AC Characteristics Diagrams tT 2.0V 1.4V 0.8V Clock tSETUP Vtt=1.4V 50 Output tHOLD Zo = 50Ω 50pF Input 1.4V tAC AC Output Load Circuit tOH tLZ 1.4V Output Clock and Clock Enable Parameters Symbol Parameter −10 Min. Max. Units Notes tCK3 Clock Cycle Time, CAS Latency = 3 10 1000 ns tCK2 Clock Cycle Time, CAS Latency = 2 15 1000 ns 1 tAC3 Clock Access Time, CAS Latency = 3 — 7 ns 2 tAC2 Clock Access Time, CAS Latency = 2 — 8 ns 2 tCKH Clock High Pulse Width 3 — ns 3 tCKL Clock Low Pulse Width 3 — ns 3 tCES Clock Enable Set-up Time 3 — ns tCEH Clock Enable Hold Time 1 — ns tSB Power down mode Entry Time 0 10 ns tT Transition Time (Rise and Fall) 0.5 10 ns 1. For 66 MHz clock, CAS Latency = 2. 2. Access time is measured at 1.4V. See AC output load circuit above. 3. tCKH is the pulse width of CK measured from the positive edge to the negative edge referenced to VIH (min). tCKL is the pulse width of CK measured from the negative edge to the positive edge referenced to VIL (max). 29L6293.E93850A 3/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 9 of 14 Discontinued (8/99 - last order; 12/99 - last ship) IBM13T4644MPC 4M x 64 SDRAM SO DIMM Common Parameters −10 Symbol Parameter Units Min. Max. Notes tCS Command Setup Time 3 — ns tCH Command Hold Time 1 — ns tAS Address and Bank Select Set-up Time 3 — ns tAH Address and Bank Select Hold Time 1 — ns RAS to CAS Delay 30 — ns 1 tRC Bank Cycle Time 90 ns 1 tRAS Active Command Period 60 100000 ns 1 tRP Precharge Time 30 — ns 1 tRRD Bank to Bank Delay Time 20 — ns 1 tCCD CAS to CAS Delay Time 1 — CK tRSC Mode Register Set Cycle Time 20 — ns tRCD 1 1. These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: the number of clock cycles = specified value of timing / clock period (count fractions as a whole number). Refresh Cycle −10 Symbol Parameter Min. Max. Units Notes 1 tREF Refresh Period — 64 ms tSREX Self Refresh Exit Time 10 — ns 1. 4096 cycles. Read Cycle −10 Symbol Parameter Units Min. Max. Notes tOH Data Out Hold Time 3 — ns tLZ Data Out to Low Impedance Time 0 — ns tHZ3 Data Out to High Impedance Time 3 7 ns 1 tHZ2 Data Out to High Impedance Time 3 8 ns 1 tDQZ DQM Data Out Disable Latency 2 — CK 1. Referenced to the time at which the output achieves the open circuit condition, not to output voltage levels ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 10 of 14 29L6293.E93850A 3/99 Discontinued (8/99 - last order; 12/99 - last ship) IBM13T4644MPC 4M x 64 SDRAM SO DIMM Write Cycle −10 Symbol Parameter Units Min. Max. tDS Data In Set-up Time 3 — ns tDH Data In Hold Time 1 — ns tDPL3 Data input to Precharge, CL=3 10 — ns tDPL2 Data input to Precharge, CL=2 15 — ns tDQW DQM Write Mask Latency 0 — CK Max. Units 100 kHz Presence Detect Read and Write Cycle Symbol fSCL Parameter Min. SCL Clock Frequency TI Noise Suppression Time Constant at SCL, SDA Inputs tAA SCL Low to SDA Data Out Valid 0.3 tBUF Time the Bus Must Be Free before a New Transmission Can Start 4.7 µs Start Condition Hold Time 4.0 µs tLOW Clock Low Period 4.7 µs tHIGH Clock High Period 4.0 µs tSU:STA Start Condition Setup Time (for a Repeated Start Condition) 4.7 µs tHD:DAT Data in Hold Time 0 µs tSU:DAT Data in Setup Time 250 tHD:STA 100 ns 3.5 µs ns tr SDA and SCL Rise Time 1 µs tf SDA and SCL Fall Time 300 ns Stop Condition Setup Time 4.7 µs tDH Data Out Hold Time 300 ns tWR Write Cycle Time tSU:STO Notes 15 ms 1 1. The Write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal Erase/Program cycle. During the Write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave address. Functional Description and Timing Diagrams Refer to the IBM 64Mb Synchronous DRAM data sheet, document 19L3264.E35855A for the functional description and timing diagrams for SDRAM operation. Refer to the IBM Application Notes: Serial Presence Detect on Memory DIMMs and SDRAM Presence Detect Definitions for the Serial Presence Detect functional description and timings. All AC timing information refers to the timings at the SDRAM devices. 29L6293.E93850A 3/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 11 of 14 Discontinued (8/99 - last order; 12/99 - last ship) IBM13T4644MPC 4M x 64 SDRAM SO DIMM Layout Drawing 67.60 2.661 2.00 min. .0787 Front 24.5 .9646 25.4 1.00 6.00 .236 23.2 .9134 2.55 .1004 3.30 .1299 20.00 .7874 (2X) 0 1.800 .0709 4.60 .1811 32.80 1.293 2.50 .0984 1.50+/- 0.10 .0591+/-.0039 0.60+/- .05 Width .0236 0.25 max. 0.009 4.00 .157 63.60 2.504 0.80 Typ. Pitch .0315 4M x 64 Side 3.80 max. 6.215 .2447 min. 4.00+/- 0.10 .1575+/-.0039 0.1496 _ 0.10 1.00 + _ .0039 .039 + Note: All dimensions are typical unless otherwise stated. ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 12 of 14 MILLIMETERS INCHES 29L6293.E93850A 3/99 Discontinued (8/99 - last order; 12/99 - last ship) IBM13T4644MPC 4M x 64 SDRAM SO DIMM Revision Log Rev Contents of Modification 9/98 Initial Release. 3/99 Change ICC2P, ICC2PS, ICC3P, ICC5; Change DQ Capacitance. 29L6293.E93850A 3/99 ©IBM Corporation. All rights reserved. Use is further subject to the provisions at the end of this document. Page 13 of 14 Discontinued (8/99 - last order; 12/99 - last ship) International Business Machines Corp.1999 Copyright Printed in the United States of America All rights reserved IBM and the IBM logo are registered trademarks of the IBM Corporation. This document may contain preliminary information and is subject to change by IBM without notice. IBM assumes no responsibility or liability for any use of the information contained herein. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life support applications where malfunction may result in direct physical harm or injury to persons. NO WARRANTIES OF ANY KIND, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, ARE OFFERED IN THIS DOCUMENT. For more information contact your IBM Microelectronics sales representative or visit us on World Wide Web at http://www.chips.ibm.com IBM Microelectronics manufacturing is ISO 9000 compliant.