Integrated Circuit Systems, Inc. ICS83021I 1-TO-1 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR GENERAL DESCRIPTION FEATURES T h e I C S 8 3 021I i s a 1 - t o -1 Differential-toLVCMOS/LVTTL Translator and a member of the HiPerClockS™ HiPerClockS™family of High Perfor mance Clock Solutions from ICS. The differential input is highly flexible and can accept the following input types: LVPECL, LVDS, LVHSTL, SSTL, and HCSL. The small 8-lead SOIC footprint makes this device ideal for use in applications with limited board space. • 1 LVCMOS / LVTTL output ICS • Differential CLK, nCLK input pair • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL • Maximum output frequency: 350MHz (typical) • Part-to-part skew: 500ps (maximum) • Small 8 lead SOIC package saves board space • Full 3.3V, 2.5V operating supply • -40°C to 85°C ambient operating temperature • Pin-to-pin compatible with MC100EPT21 BLOCK DIAGRAM CLK nCLK PIN ASSIGNMENT nc CLK nCLK nc Q0 1 2 3 4 8 7 6 5 VDD Q0 nc GND ICS83021I 8-Lead SOIC 3.8mm x 4.8mm, x 1.47mm package body M Package Top View 83021AMI www.icst.com/products/hiperclocks.html 1 REV. B JUNE 30, 2004 ICS83021I Integrated Circuit Systems, Inc. 1-TO-1 2.5V 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR TABLE 1. PIN DESCRIPTIONS Number Name 1, 4, 6 nc Type Unused Description No connect. 2 CLK Input 3 nCLK Input Pulldown Non-inver ting differential clock input. 5 GND Power 7 Q0 Output Single clock output. LVCMOS / LVTTL interface levels. 8 VDD Power Positive supply pin. Pullup Inver ting differential clock input. Power supply ground. NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN RPULLUP Input Capacitance Power Dissipation Capacitance (per output) Input Pullup Resistor RPULLDOWN Input Pulldown Resistor ROUT Output Impedance CPD 83021AMI Test Conditions Minimum VDD = 3.6V 5 www.icst.com/products/hiperclocks.html 2 Typical Maximum Units 4 pF 23 pF 51 KΩ 51 KΩ 7 12 Ω REV. B JUNE 30, 2004 ICS83021I Integrated Circuit Systems, Inc. 1-TO-1 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V Inputs, VI -0.5V to VDD + 0.5 V Outputs, VO -0.5V to VDD + 0.5V Package Thermal Impedance, θJA 112.7°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±0.3V or 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions VDD Positive Supply Voltage IDD Power Supply Current Minimum Typical Maximum Units 3.0 3.3 3.6 V 2.375 2.5 2.625 V 20 mA TABLE 3BC. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±0.3V or 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter VOH Output High Voltage; NOTE 1 Test Conditions Minimum Typical Maximum VDD = 3.6V 2.6 V VDD = 2.625V 1.8 V VOL Output Low Voltage; NOTE 1 0.5 NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information, Output Load Test Circuit Diagrams. Units V TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±0.3V or 2.5V±5%, TA = -40°C TO 85°C Symbol IIH IIL Parameter Input High Current Input Low Current Test Conditions nCLK Minimum Typical VIN = VDD = 3.6V or 2.625V Units 5 µA 150 µA CLK VIN = VDD = 3.6V or 2.625V nCLK VIN = 0V, VDD = 3.6V or 2.625V -150 µA CLK VIN = 0V, VDD = 3.6V or 2.625V -5 µA Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR GND + 0.5 NOTE 1, 2 NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V. NOTE 2: Common mode voltage is defined as VIH. VPP 83021AMI Maximum www.icst.com/products/hiperclocks.html 3 1.3 V VDD - 0.85 V REV. B JUNE 30, 2004 Integrated Circuit Systems, Inc. ICS83021I 1-TO-1 2.5V 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR TABLE 4A. AC CHARACTERISTICS, VDD = 3.3V±0.3V, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay, NOTE 1 tsk(pp) Par t-to-Par t Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical Maximum 350 ƒ≤ 350MHz 1.7 2.0 Units MHz 2.3 ns 500 ps 0.8V to 2V 100 250 400 ps ƒ≤ 166MHz 45 50 55 % 166MHz < ƒ ≤ 350MHz 40 50 60 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDD/2. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. % TABLE 4B. AC CHARACTERISTICS, VDD = 2.5V±5%, TA = -40°C TO 85°C Symbol Parameter fMAX Output Frequency tPD Propagation Delay, NOTE 1 tsk(pp) Par t-to-Par t Skew; NOTE 2, 3 tR / tF Output Rise/Fall Time odc Output Duty Cycle Test Conditions Minimum Typical Maximum 350 ƒ≤ 350MHz 1.9 20% to 80% 250 ƒ≤ 250MHz 45 2.2 50 MHz 2.5 ns 500 ps 550 ps 55 % 250MHz < ƒ ≤ 350MHz 40 50 60 All parameters measured at fMAX unless noted otherwise. NOTE 1: Measured from the differential input crossing point to the output at VDD/2. NOTE 2: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2. NOTE 3: This parameter is defined in accordance with JEDEC Standard 65. 83021AMI www.icst.com/products/hiperclocks.html 4 Units % REV. B JUNE 30, 2004 Integrated Circuit Systems, Inc. ICS83021I 1-TO-1 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR PARAMETER MEASUREMENT INFORMATION 1.65V ± 0.15V 1.25V ± 5% SCOPE V DD Qx LVCMOS SCOPE VDD Qx LVCMOS GND GND -1.25V ± 5% -1.65V ± 0.15V 3.3V OUTPUT LOAD AC TEST CIRCUIT 2.5V OUTPUT LOAD AC TEST CIRCUIT VDD PART 1 V DD Qx 2 nCLK V V Cross Points PP V PART 2 CMR DD Qy 2 t sk(pp) CLK GND PART-TO-PART SKEW DIFFERENTIAL INPUT LEVEL nCLK V DD 2 Q0 CLK Pulse Width t VDD 2 t Q0 PD odc = PERIOD t PW t PERIOD PROPAGATION DELAY 2V Clock Outputs OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 2V 80% 0.8V 0.8V tR Clock Outputs tF 20% 20% tR tF 2.5V OUTPUT RISE/FALL TIME 3.3V OUTPUT RISE/FALL TIME 83021AMI 80% www.icst.com/products/hiperclocks.html 5 REV. B JUNE 30, 2004 Integrated Circuit Systems, Inc. ICS83021I 1-TO-1 2.5V 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR APPLICATION INFORMATION WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609. VDD R1 1K Single Ended Clock Input CLK V_REF nCLK C1 0.1u R2 1K FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT 83021AMI www.icst.com/products/hiperclocks.html 6 REV. B JUNE 30, 2004 ICS83021I Integrated Circuit Systems, Inc. 1-TO-1 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR DIFFERENTIAL CLOCK INPUT INTERFACE The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 2A to 2E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 2A, the input termination applies for ICS HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation. 3.3V 3.3V 3.3V 1.8V Zo = 50 Ohm CLK Zo = 50 Ohm CLK Zo = 50 Ohm nCLK Zo = 50 Ohm LVPECL nCLK HiPerClockS Input LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R1 50 HiPerClockS Input R2 50 R2 50 R3 50 FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY ICS HIPERCLOCKS LVHSTL DRIVER FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER 3.3V 3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm 3.3V R4 125 LVDS_Driv er Zo = 50 Ohm CLK CLK R1 100 Zo = 50 Ohm nCLK LVPECL R1 84 HiPerClockS Input nCLK Receiv er Zo = 50 Ohm R2 84 FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY 3.3V LVDS DRIVER 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 Zo = 50 Ohm C2 R3 125 R4 125 CLK nCLK R5 100 - 200 R6 100 - 200 R1 84 HiPerClockS Input R2 84 R5,R6 locate near the driver pin. FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY 3.3V LVPECL DRIVER WITH AC COUPLE 83021AMI www.icst.com/products/hiperclocks.html 7 REV. B JUNE 30, 2004 Integrated Circuit Systems, Inc. ICS83021I 1-TO-1 2.5V 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR RELIABILITY INFORMATION TABLE 5. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC θJA by Velocity (Linear Feet per Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 0 200 500 153.3°C/W 112.7°C/W 128.5°C/W 103.3°C/W 115.5°C/W 97.1°C/W NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs. TRANSISTOR COUNT The transistor count for ICS83021I is: 416 83021AMI www.icst.com/products/hiperclocks.html 8 REV. B JUNE 30, 2004 Integrated Circuit Systems, Inc. ICS83021I 1-TO-1 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC TABLE 6. PACKAGE DIMENSIONS SYMBOL Millimeters MINIMUM N MAXIMUM 8 A 1.35 1.75 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 5.00 E 3.80 e H 4.00 1.27 BASIC 5.80 6.20 h 0.25 0.50 L 0.40 1.27 α 0° 8° Reference Document: JEDEC Publication 95, MS-012 83021AMI www.icst.com/products/hiperclocks.html 9 REV. B JUNE 30, 2004 ICS83021I Integrated Circuit Systems, Inc. 1-TO-1 2.5V 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package ICS83021AMI 83021AMI 8 lead SOIC ICS83021AMIT 83021AMI 8 lead SOIC on Tape and Reel Count 96 per tube 2500 Temperature -40°C to 85°C -40°C to 85°C The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 83021AMI www.icst.com/products/hiperclocks.html 10 REV. B JUNE 30, 2004 Integrated Circuit Systems, Inc. ICS83021I 1-TO-1 2.5V, 3.3V DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR REVISION HISTORY SHEET Rev B B 83021AMI Table T2 T3B T3C T3D T4B T4A Page 2 3 3 3 4 5 6 7 2 4 Description of Change Pin Characteristics table - added 2.5V CPD. Added 2.5V Power Supply table. LVCMOS table - added 2.5V VOH. Differential table - added 2.5V. Added 2.5V AC Characteristics table. Added 2.5V Output Load AC Test Circuit Diagram and 2.5V Output Rise/Fall Time Diagrams. Updated Figure 1. Added Differential Clock Input Interface section. Pin Characteristics Table - changed CIN 4pF max. to 4pF typical. 3.3V AC Characteristics Table - changed odc Test Conditions. www.icst.com/products/hiperclocks.html 11 Date 6/3/04 6/30/04 REV. B JUNE 30, 2004