PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR GENERAL DESCRIPTION FEATURES The ICS843011C is a Fibre Channel Clock Generator and a member of the HiPerClocksTM HiPerClockS™ family of high performance devices from ICS. The ICS843011C uses a 26.5625MHz crystal to synthesize 106.25MHz or a 25MHz crystal to synthesize 100MHz. The ICS843011C has excellent <1ps phase jitter performance, over the 637kHz – 10MHz integration range. The ICS843011C is packaged in a small 8-pin TSSOP, making it ideal for use in systems with limited board space. • One differential 3.3V LVPECL output ICS • Crystal oscillator interface designed for 26.5625MHz 18pF parallel resonant crystal • Output frequency: 106.25MHz or 100MHz • VCO range: 560MHz - 680MHz • RMS phase jitter @ 100MHz, using a 25MHz crystal (637kHz - 10MHz): 0.29ps (typical) • 3.3V operating supply • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS compliant packages FREQUENCY TABLE Crystal (MHz) Output Frequency (MHz) 26.5625 106.25 25 100 BLOCK DIAGRAM XTAL_IN OSC XTAL_OUT PIN ASSIGNMENT Phase Detector VCO 637.5MHz w/ 26.5625MHz Ref. ÷6 Q nQ VCCA VEE XTAL_OUT XTAL_IN 1 2 3 4 8 7 6 5 VCC Q nQ nc ICS843011C M = ÷24 (fixed) 8-Lead TSSOP 4.40mm x 3.0mm x 0.925mm package body G Package Top View The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 843011CG www.icst.com/products/hiperclocks.html REV. A JANUARY 25, 2006 1 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TABLE 1. PIN DESCRIPTIONS Number Name Type 1 VCCA Power Analog supply pin. 2 3, 4 5 VEE XTAL_OUT, XTAL_IN nc Power Unused Negative supply pin. Crystal oscillator interface. XTAL_IN is the input, XTAL_OUT is the output. No connect. 6, 7 nQ, Q Output Differential clock outputs. LVPECL interface levels. 8 VCC Power Core supply pin. Input Description TABLE 2. PIN CHARACTERISTICS Symbol Parameter CIN Input Capacitance 843011CG Test Conditions Minimum Typical 4 www.icst.com/products/hiperclocks.html 2 Maximum Units pF REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC 4.6V Inputs, VI -0.5V to VCC + 0.5V Outputs, IO Continuous Current Surge Current 50mA 100mA Package Thermal Impedance, θJA 101.7°C/W (0 mps) Storage Temperature, TSTG -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter VCC Core Supply Voltage VCCA Analog Supply Voltage ICCA Analog Supply Current IEE Power Supply Current Test Conditions Minimum Typical Maximum Units 3.135 3.3 3.465 V 3.135 3.3 3.465 included in IEE V 10 mA 68 mA TABLE 3B. LVPECL DC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VOH Output High Voltage; NOTE 1 VCC - 1.4 VCC - 0.9 V VOL Output Low Voltage; NOTE 1 VCC - 2.0 VCC - 1.7 V VSWING Peak-to-Peak Output Voltage Swing 0.6 1.0 V Maximum Units NOTE 1: Outputs terminated with 50Ω to VCC - 2V. TABLE 4. CRYSTAL CHARACTERISTICS Parameter Test Conditions Minimum Mode of Oscillation Typical Fundamental Frequency 26.5625 MHz Equivalent Series Resistance (ESR) 25 50 Ω Shunt Capacitance 7 pF TABLE 5. AC CHARACTERISTICS, VCC = 3.3V±5%, TA = -40°C TO 85°C Symbol Parameter FOUT tjit(Ø) Test Conditions Minimum Output Frequency RMS Phase Jitter (Random); NOTE 1 t R / tF Output Rise/Fall Time odc Output Duty Cycle Typical 93.33 106.25MHz; Integration Range: 637kHz - 10MHz 100MHz; Integration Range: 637kHz - 10MHz 20% to 80% Maximum Units 113.33 MHz 0.29 ps 0.29 ps 400 ps 50 % NOTE 1: Please refer to the Phase Noise Plot. 843011CG www.icst.com/products/hiperclocks.html 3 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR PARAMETER MEASUREMENT INFORMATION 2V Phase Noise Plot Qx SCOPE Noise Power VCC LVPECL Phase Noise Mask nQx VEE f1 -1.3V ± 0.165V Offset Frequency f2 RMS Jitter = Area Under the Masked Phase Noise Plot 3.3V OUTPUT LOAD AC TEST CIRCUIT RMS PHASE JITTER nQ 80% Q 80% VSW I N G t PW t odc = Clock Outputs PERIOD t PW 20% 20% tR tF x 100% t PERIOD OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 843011CG OUTPUT RISE/FALL TIME www.icst.com/products/hiperclocks.html 4 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. The ICS843011C provides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V CC and V CCA should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. To achieve optimum jitter performance, power supply isolation is required. Figure 1 illustrates how a 10Ω resistor along with a 10μF and a .01μF bypass capacitor should be connected to each VCCA pin. 3.3V VCC .01μF 10Ω V CCA .01μF 10μF FIGURE 1. POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE parallel resonant crystal and were chosen to minimize the ppm error. The optimum C1 and C2 values can be slightly adjusted for different board layouts. The ICS843011C has been characterized with 18pF parallel resonant crystals. The capacitor values, C1 and C2, shown in Figure 2 below were determined using a 26.5625MHz, 18pF XTAL_OUT C1 33p X1 18pF Parallel Crystal XTAL_IN C2 22p Figure 2. CRYSTAL INPUt INTERFACE 843011CG www.icst.com/products/hiperclocks.html 5 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR APPLICATION SCHEMATIC generating 106.25MHz output frequency. The C1 = 27pF and C2 = 33pF are recommended for frequency accuracy. For different board layout, the C1 and C2 values may be slightly adjusted for optimizing frequency accuracy. Figure 3A shows a schematic example of the ICS843011C. An example of LVEPCL termination is shown in this schematic. Additional LVPECL termination approaches are shown in the LVPECL Termination Application Note. In this example, an 18 pF parallel resonant 26.5625MHz crystal is used for VCCA VCC VCC R2 10 C3 10uF C4 0.1u R3 133 U2 R5 133 Zo = 50 Ohm Q XTAL_OUT C2 33pF X1 26.5625MHz 18pF 1 2 3 4 VCCA VEE XTAL_OUT XTAL_IN VCC Q nQ nc 8 7 6 5 VCC + Zo = 50 Ohm - nQ XTAL_IN 843011C R4 82.5 C5 0.1u C1 27pF R6 82.5 Zo = 50 Ohm Q + Zo = 50 Ohm nQ R5 50 Optional Y-Termination R6 50 R7 50 FIGURE 3A. ICS843011C SCHEMATIC EXAMPLE PC BOARD LAYOUT EXAMPLE Figure 3B shows an example of ICS843011C P.C. board layout. The crystal X1 footprint shown in this example allows installation of either surface mount HC49S or through-hole HC49 package. The footprints of other components in this example are listed in the Table 6. There should be at least one decoupling capacitor per power pin. The decoupling capacitors should be located as close as possible to the power pins. The layout assumes that the board has clean analog power ground plane. TABLE 6. FOOTPRINT TABLE Reference Size C1, C2 0402 C3 0805 C4, C5 0603 R2 0603 NOTE: Table 6, lists component sizes shown in this layout example. FIGURE 3B. ICS843011 PC BOARD LAYOUT EXAMPLE 843011CG www.icst.com/products/hiperclocks.html 6 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR POWER CONSIDERATIONS This section provides information on power dissipation and junction temperature for the ICS843011C. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS843011C is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. • • Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 68mA = 235.6mW Power (outputs)MAX = 30mW/Loaded Output pair Total Power_MAX (3.465V, with all outputs switching) = 235.6mW + 30mW = 265.6mW 2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C. The equation for Tj is as follows: Tj = θJA * Pd_total + TA Tj = Junction Temperature θJA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 90.5°C/W per Table 7 below. Therefore, Tj for an ambient temperature of 85°C with all outputs switching is: 85°C + 0.266W * 90.5°C/W = 109.1°C. This is well below the limit of 125°C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer). TABLE 7. THERMAL RESISTANCE θJA FOR 8-PIN TSSOP, FORCED CONVECTION θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 843011CG 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W www.icst.com/products/hiperclocks.html 7 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR 3. Calculations and Equations. The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 4. VCC Q1 VOUT RL 50 VCC - 2V FIGURE 4. LVPECL DRIVER CIRCUIT AND TERMINATION To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination voltage of V - 2V. CC • For logic high, VOUT = V OH_MAX (V CCO_MAX • -V OH_MAX OL_MAX CCO_MAX -V OL_MAX CC_MAX – 0.9V ) = 0.9V For logic low, VOUT = V (V =V =V CC_MAX – 1.7V ) = 1.7V Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low. Pd_H = [(V OH_MAX – (V CC_MAX - 2V))/R ] * (V CC_MAX L -V OH_MAX ) = [(2V - (V CC_MAX -V OH_MAX ))/R ] * (V CC_MAX L -V OH_MAX )= [(2V - 0.9V)/50Ω] * 0.9V = 19.8mW Pd_L = [(V OL_MAX – (V CC_MAX - 2V))/R ] * (V L CC_MAX -V OL_MAX ) = [(2V - (V CC_MAX -V OL_MAX ))/R ] * (V L CC_MAX -V OL_MAX )= [(2V - 1.7V)/50Ω] * 1.7V = 10.2mW Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW 843011CG www.icst.com/products/hiperclocks.html 8 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR RELIABILITY INFORMATION TABLE 8. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP θJA by Velocity (Meters per Second) Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 101.7°C/W 90.5°C/W 89.8°C/W TRANSISTOR COUNT The transistor count for ICS843011C is: 2436 843011CG www.icst.com/products/hiperclocks.html 9 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. PACKAGE OUTLINE - G SUFFIX FOR ICS843011C FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR 8 LEAD TSSOP TABLE 9. PACKAGE DIMENSIONS SYMBOL Millimeters Minimum N A Maximum 8 -- 1.20 A1 0.05 0.15 A2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 D 2.90 3.10 E E1 6.40 BASIC 4.30 e 4.50 0.65 BASIC L 0.45 0.75 α 0° 8° aaa -- 0.10 Reference Document: JEDEC Publication 95, MO-153 843011CG www.icst.com/products/hiperclocks.html 10 REV. A JANUARY 25, 2006 PRELIMINARY Integrated Circuit Systems, Inc. ICS843011C FEMTOCLOCKS™ CRYSTAL-TO3.3V LVPECL CLOCK GENERATOR TABLE 10. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS843011CG 3011C 8 lead TSSOP tube -40°C to 85°C ICS843011CGT 3011C 8 lead TSSOP 2500 tape & reel -40°C to 85°C ICS843011CGLF TBD 8 lead "Lead-Free" TSSOP tube -40°C to 85°C ICS843011CGLFT TBD 8 lead "Lead-Free" TSSOP 2500 tape & reel -40°C to 85°C NOTE: Par ts that are ordered with an "LF suffix to the par t number are the Pb-Free configuration and are RoHS compliant. The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial applications. Any other applications such as those requiring ehigh reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 843011CG www.icst.com/products/hiperclocks.html 11 REV. A JANUARY 25, 2006