ICS ICS9248-128

Integrated
Circuit
Systems, Inc.
ICS9248-128
Frequency Generator & Integrated Buffers
Block Diagram
48MHz
/2
SIO
SEL24_14#
XTAL
OSC
3
REF(2:0)
IOAPIC
PLL1
Spread
Spectrum
MODE
FS(2:0)
CPU3.3#_2.5
SD_SEL#
STOP
3
CPUCLK (3:1)
13
SDRAM (12:0)
CPU_STOP
3
LATCH
5
PCI
CLOCK
DIVDER
STOP
POR
SDRAM_STOP#
CPU_STOP#
PCI_STOP#
PD#
SDATA
SCLK
VDDR/X
*MODE/REF0
GNDREF
X1
X2
VDDPCI
*FS1/PCICLK_F
*FS2.PCICLK0
GNDPCI
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
SDRAM12
GNDSDR
*CPU_STOP# /SDRAM11
*PCI_STOP# /SDRAM10
VDDSD/C
*SDRAM_STOP# /SDRAM9
*PD# /SDRAM8
GNDFIX
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDLAPIC
IOAPIC
REF1/SD_SEL#*
GNDLAPIC
REF2/CPU2.5_3.3#*
CPUCLK1
VDDLCPU
CPUCLK2
CPUCLK3
GNDCPU
SDRAM0
SDRAM1
VDDSDR
SDRAM2
SDRAM3
GNDSDR
SDRAM4
SDRAM5
VDDSDR
SDRAM6
SDRAM7
GNDSDR
48MHz/FS0*
SIO/SEL24_14#MHz*
48-Pin SSOP
* Internal Pull-up Resistor of
120K to 3.3V on indicated inputs
Functionality
PLL2
X1
X2
Pin Configuration
ICS9248-128
Recommended Application:
SIS 530/620 style chipset
Output Features:
•
- 3 CPU @ 2.5V/3.3V up to 133.3 MHz.
•
- 6 PCI @ 3.3V (including 1 free-running)
•
- 13 SDRAMs @ 3.3V up to 133.3MHz.
•
- 3 REF @ 3.3V, 14.318MHz
•
- 1 clock @ 24/14.3 MHz selectable output for SIO
•
- 1 Fixed clock at 48MHz (3.3V)
•
- 1 IOAPIC @ 2.5V / 3.3V
Features:
•
Up to 133MHz frequency support
•
Support power management: CPU, PCI, SDRAM stop and
Power down Mode from I2C programming.
•
Spread spectrum for EMI control ( ± 0.25% center spread
& 0 to -0.5% down spread).
•
Uses external 14.318MHz crystal
•
FS pins for frequency select
Key Specifications:
•
CPU – CPU<175ps
•
SDRAM – SDRAM < 350ps
•
CPU–SDRAM < 500ps
•
CPU(early) – PCI : 1-4ns (typ. 2ns)
•
PCI – PCI <500ps
Control
5
PCICLK (4:0)
PCICLK_F
PCI_STOP
Logic
Config.
Reg.
SD_SEL FS2
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
FS1
FS0
CPU
MHZ
SDRAM
MHZ
PCI
MHZ
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
90.00
66.70
95.00
100.00
100.00
112.00
124.00
97.00
66.70
75.00
83.30
95.00
100.00
112.00
124.00
133.30
90.00
100.05
63.33
66.66
75.00
74.66
82.66
97.00
66.70
75.00
83.30
95.00
100.00
112.00
124.00
133.30
30.00
33.35
31.66
33.33
30.00
37.33
31.00
32.33
33.35
30.00
33.32
31.66
33.33
37.33
31.00
33.33
Note: REF, IOAPIC = 14.318MHz
9248-128 Rev B 11/16/00
Third party brands and names are the property of their respective owners.
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS9248-128
Pin Descriptions
P in number
P in name
Type
D escription
1
V DDR/X
RE F0
M ode
P ower
Output
Input
Is olated 3.3 V power for crys tal & referenc e
3.3V , 14.318 M Hz referenc e clock output.
Function s elec t pin, 1= des k top m ode, 0= m obile m ode. Latc hed input.
GND
P ower
3.3 V Ground
X1
X2
V DDP CI
FS 1
P CICLK _F
P CICLK 0
FS 2
P CICLK (4:1)
S DRA M 12,
S DRA M (7:0)
S DRA M 11
Input
Output
P ower
Input
Output
Output
Input
Output
14.318 M Hz crys tal input
14.318 M Hz crys tal output
3.3 V power for the P CI clock outputs
Logic input frequency s elec t bit. Input latched at power-on.
3.3 V free running P CI c loc k output, will not be stopped by the P CI_S TOP #
3.3 V P CI cloc k outputs, generating tim ing requirem ents for P entium II
Logic input frequency s elec t bit. Input latched at power-on.
3.3 V P CI cloc k outputs, generating tim ing requirem ents for P entium II
Output
S DRA M c lock outputs . Frequency is s elec ted by S D-S el latched input.
Output
S DRA M c lock outputs . Frequency is s elec ted by S D-S el latched input.
CP U_S TOP #
Input
S DRA M 10
Output
P CI-S TOP #
Input
V DDS D/C
S DRA M 9
P ower
Output
S DRA M _S TOP #
Input
S DRA M 8
Output
P D#
Input
S DA TA
S CLK
Input
Input
S E L24_14#
Input
SIO
Output
FS0
Input
48 M Hz
Output
V DDS DR
CP UCLK (3:1)
V DDLCP U
RE F2
P ower
0utput
P ower
Output
CP U3.3#_2.5
Input
GNDL
RE F1
S D_S E L#
IOA P IC
V DDLA P IC
P ower
Output
Input
Output
P ower
2 1,2
3,9,16,22,
27,33,39
4
5
6,14
7 1,2
8 1,2
13, 12, 11, 10
15,28,29,31,32,
34,35,37,38
17
1
18
1
19
20
1
21
1
23
24
25
26
1,2
1,2
30,36
40,41,43
42
44
1,2
45
46
1,2
47
48
A s ynchronous ac tiv e low input pin used to s top the CP UCLK in low state,
all other cloc ks will c ontinue to run. The CP UCLK will have a "Turnon" latency
of at least 3 CP U clock s.
SDRA M c lock outputs . Frequency is s elec ted by S D-S E L latched input.
Sy nc hronous active low input used to s top the P CICLK in a low state. It will not
effect P CICLK _F or any other outputs.
3.3 V power for S DRA M outputs and c ore
S DRA M c lock outputs . Frequency is s elec ted by S D-S el latched input.
As ynchronous ac tiv e low input us ed to stop the S DRA M in a low s tate.
It will not effec t any other outputs.
S DRA M c lock outputs . Frequency is s elec ted by S D-S el latched input.
As ynchronous ac tiv e low input pin used to power down the devic e into a low
power state. The internal c lock s are dis abled and the V CO and the c ry stal are
stopped. The latenc y of the power down will not be greater than 3m s .
Data input for I 2 C serial input.
Clock input of I 2 C input
This input pin controls the frequency of the S IO. If logic 0 at power on
S IO= 14.318 M Hz . If logic 1 at power-on S IO= 24M Hz .
Super I/O output. 24 or 14.318 M Hz. S electable at power-up by S E L24_14M Hz
Logic input frequency s elec t bit. Input latched at power-on.
3.3 V 48 M Hz c lock output, fixed frequenc y cloc k ty pic ally us ed with
US B dev ices
3.3 V power for S DRA M outputs
2.5 V CPU and Host c loc k outputs
2.5 V power for CP U
3.3V , 14.318 M Hz referenc e clock output.
This pin selects the operating voltage for the CP U. If logic 0 at power on
CP U= 3.3 V and if logic 1 at power on CP U= 2.5 V operating voltage.
2.5 V Ground for the IOA P IC or CP U
3.3V , 14.318 M Hz referenc e clock output.
This input pin controls the frequency of the S DRA M .
2.5V fixed 14.318 M Hz IOA P IC clock outputs
2.5 V power for IOA P IC
Notes:
1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs
2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
2
ICS9248-128
General Description
The ICS9248-128 is the single chip clock solution for Desktop/Notebook designs using the SIS style chipset. It provides all
necessary clock signals for such a system.
Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB.
This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-128 employs a
proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. The SD_SEL
latched input allows the SDRAM frequency to follow the CPUCLK frequency(SD_SEL=1) or other clock frequencies
(SD_SEL=0)
Mode Pin - Power Management Input Control
MODE, Pin 2
(Latched Input)
0
1
Pin 17
Pin 18
Pin 20
Pin 21
CPU_STOP#
(INPUT)
SDRAM 11
(OUTPUT)
PCI_STOP#
(INPUT)
SDRAM 10
(OUTPUT)
SDRAM_STOP#
(INPUT)
SDRAM9
(OUTPUT)
PD#
(INPUT)
SDRAM8
(OUTPUT)
Power Management Functionality
PD#
CPU_STOP# PCI_STOP# SDRAM_STOP
PCICLK
(0:4)
SDRAM
(0:12)
PCICLK_F
CPUCLK
Crystal
OSC
VCO
Stopped
Low
Running
Stopped
Low
Stopped
Low
Running
Stopped
Low
Running
Stopped
Low
Running
Stopped
Low
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Stopped
Low
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
Running
0
X
X
X
1
1
1
1
Stopped
Low
Running
1
1
1
0
Running
1
1
0
1
1
1
0
0
1
0
1
1
Running
Running
Running
1
0
1
0
Running
Stopped
Low
Running
1
0
0
1
Running
Running
1
0
0
0
Stopped
Low
Running
Stopped
Low
Stopped
Low
Stopped
Low
Stopped
Low
Stopped
Low
Stopped
Low
Stopped
Low
Stopped
Low
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5
Input level
(Latched Data)
Buffer Selected
for operation at:
1
2.5V VDD
0
3.3V VDD
Third party brands and names are the property of their respective owners.
3
ICS9248-128
Serial Configuration Command Bitmap
Byte 0: Functionality and frequency select register (Default = 0)
Bit
Bit 7
Bit
(2, 6:4)
Bit 3
Bit 1
Bit 0
Description
0 - ±0.25% Center Spread Spectrum
1 - 0 to -0.5% Down Spread Spectrum
Bit (2, 6:4)
CPUCLK
SDRAM
PCICLK
0000
90.00
30.00
90.00
0001
66.70
33.35
100.05
0010
95.00
31.66
63.33
0011
100.00
33.33
66.66
0100
100.00
30.00
75.00
0101
112.00
37.33
74.66
0110
124.00
31.00
82.66
0111
97.00
32.33
97.00
1000
66.70
33.35
66.70
1001
75.00
30.00
75.00
1010
83.30
33.32
83.30
1011
95.00
31.66
95.00
1100
100.00
33.33
10 0 . 0 0
1101
112.00
37.33
112.00
1110
124.00
31.00
12 4 . 0 0
1111
133.30
33.33
133.30
0 - Frequency is selected by hardware select, latched inputs
1 - Frequency is selected by Bit 2, 6:4
0 - Normal
1 - Spread spectrum enabled
0 - Running
1 - Tristate all outputs
PWD
1
0,001
Note 1
0
1
0
Note 1: Default at power-up will be for latched logic inputs to define frequency.
I2C readback of the power up default indicates the revision ID code in bit 2, 6:4 as shown.
Third party brands and names are the property of their respective owners.
4
ICS9248-128
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
40
41
43
-
PWD
1
1
1
1
1
1
1
X
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Description
(Reserved)
(Reserved)
(Reserved)
(Reserved)
CPUCLK3
CPUCLK2
CPUCLK1
FS0#
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Pin #
28
29
31
32
34
35
37
38
PWD
1
1
1
1
1
1
1
1
Description
SDRAM7
SDRAM6
SDRAM5
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
1
X
1
1
X
1
1
1
Pin #
25
26
15
17
18
20
21
PWD
1
1
1
1
1
1
1
1
Description
(Reserved)
24/14MHz
48MHz
SDRAM12
SDRAM11
SDRAM10
SDRAM9
SDRAM8
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Pin #
47
44
46
2
Description
FS1#
PCICLK_F
(Reserved)
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PWD
X
1
1
1
1
1
1
1
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Byte 3: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
7
13
12
11
10
8
Description
(Reserved)
FS2#
(Reserved)
IOAPIC
SD_SEL#
REF2
REF1
REF0
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Third party brands and names are the property of their respective owners.
5
ICS9248-128
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . .
Case Temperature . . . . . . . . . . . . . . . . . . . . . . . . . .
5.5 V
GND –0.5 V to VDD +0.5 V
0°C to +70°C
–65°C to +150°C
115°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = VDDL = 3.3 V +/-5% (unless otherwise stated)
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
Input Low Current
Operating Supply
Current
Powerdown Current
Input Frequency
1
Input Capacitance
1
Transition time
Clk Stabilization
Skew
1
1
SYMBOL
VIH
VIL
IIH
IIL1
IIL2
IDD3.3OP66
IDD3.3OP100
IDD3.3PD
CONDITIONS
VIN = VDD
VIN = 0V; Inputs with no pull-up resistors
VIN = 0V; Inputs with pull-up resistors
CL = 0 pF; Select @ 66 MHz
CL = 0 pF; Select @ 100 MHz
CL = 0 pF; Input address to VDD or GND
Fi
CIN
CINX
VDD = 3.3 V
Logic Inputs
X1 & X2 pins
Ttrans
To 1st crossing of target frequency
TSTAB
TCPU100SDRAM100
TCPU-PCI
MIN
2
VSS-0.3
TYP
MAX
VDD+0.3
0.8
5
150
170
180
180
UNITS
V
V
µA
µA
µA
mA
mA
260
600
µA
14.318
16
5
45
MHz
pF
pF
3
ms
300
3
500
ms
ps
2.6
4
ns
-5
-200
11
27
From VDD = 3.3 V to 1% target frequency
VT = 1.5V
VT = 1.5V
1
1
Guaranteed by design, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/- 5%, VDDL = 2.5V +/- 5% (unless otherwise stated).
PARAMETER
Operating Supply
Current
1
Skew
1
SYMBOL
IDD2.5OP 66
IDD2.5OP 100
CONDITIONS
C L = 0 pF; Select @ 66 MHz
C L = 0 pF; Select @ 100 MHz
TCP U100SDRAM100 VT = 1.5V; VTL = 1.25V
VT = 1.5V; VTL = 1.25V
TCP U-P CI
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
6
MIN
1
TYP
60
80
MAX
72
100
UNITS
mA
mA
230
2.6
500
4
ps
ns
ICS9248-128
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = VDDL = 3.3 V +/-5%; C L = 10 - 20 pF (unless otherwise stated).
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SYMBOL
VOH2B
VOL2B
IOH2B
IOL2B
Rise Time
tr2B1
Fall Time
tf2B1
Duty Cycle
Skew
d t2B
CONDITIONS
TYP
2.2
0.3
-16
22
MAX
VOL = 0.4 V, VOH = 2.4 V
1.45
2
mA
mA
ns
VOH = 2.4 V, VOL = 0.4 V
0.95
2
ns
46
55
%
65
175
ps
210
250
ps
TYP
2.2
0.25
-15
23
1.4
MAX
UNITS
V
V
1.6
mA
mA
ns
1.2
1.6
ns
48
55
%
50
175
ps
210
250
ps
IOH = -12 mA
IOL = 12 mA
VOH = 2 V
VOL = 0.8 V
19
1
VT = 1.5 V
1
VT = 1.5 V
VT = 1.5 V @ CPU & SDRAM = 100 MHz
t sk2B
tjcyc-cyc2B1
MIN
2.4
45
Jitter, Cycle-to-cycle
Guaranteed by design, not 100% tested in production.
0.4
-19
UNITS
V
V
1
Electrical Characteristics - CPUCLK
TA = 0 - 70º C; VDD = 3.3 V +/-5%, VDDL = 2.5V +/- 5 %; C L = 10 - 20 pF (unless otherwise stated).
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
Rise Time
SYMBOL
VOH2B
VOL2B
IOH2B
IOL2B
tr2B1
Fall Time
t f2B1
VT = 1.25 V
1
VT = 1.25 V
VT = 1.25 V @ CPU &
SDRAM = 100 MHz
t sk2B
Jitter, Cycle-to-cycle
tjcyc-cyc2B1
MIN
2
19
VOH = 2.0 V, VOL = 0.4 V
1
Duty Cycle
Skew
1
d t2B
CONDITIONS
IOH = -12 mA
IOL = 12 mA
VOH = 1.7 V
VOL = 0.7 V
VOL = 0.4 V, VOH = 2.0 V
45
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
7
0.4
-19
ICS9248-128
Electrical Characteristics - PCICLK
TA = 0 - 70º C; VDD = 3.3 V +/- 5%, VDDL = 2.5 V +/- 5 %; C L = 30 pF (unless otherwise stated).
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SYMBOL
VOH1
VOL1
IOH1
IOL1
Rise Time
t r1 1
Fall Time
t f1
1
Duty Cycle
Skew
d t1 1
tsk1
CONDITIONS
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
MIN
2.4
16
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4V, VOL = 0.4 V
VT = 1.5 V
1
1
45
VT = 1.5 V
VT = 1.5 V
tjcyc-cyc
Jitter, Cycle-to-cycle
Guaranteed by design, not 100% tested in production.
TYP
2.6
0.3
-18
24
MAX
1.8
2
mA
mA
ns
1.7
2
ns
49
55
%
260
500
ps
150
500
ps
TYP
2.6
0.3
-18
24
MAX
UNITS
V
V
1.6
2
mA
mA
ns
0.4
22
UNITS
V
V
1
Electrical Characteristics - SDRAM
TA = 0 - 70º C; VDD = 3.3 V +/- 5%, VDDL = 2.5 V +/- 5 %; C L = 30 pF (unless otherwise stated).
PARAMETER
Output High Voltage
Output Low Voltage
Output High Current
Output Low Current
SYMBOL
VOH1
VOL1
IOH1
IOL1
Rise Time
t r1 1
Fall Time
1
t f1
16
VOH = 2.4V, VOL = 0.4 V
0.4
22
1.6
2
ns
VT = 1.5 V; divide by 2 selects < 124 MHz
47
50
57
%
d t2
1
VT = 1.5 V; divide by 3 selects
45
50
55
%
d t3
1
VT = 1.5 V; selects >= 124 MHz
43
50
53
%
1
VT = 1.5 V; SDRAM 8, 9, 11 & 12
110
250
ps
VT = 1.5 V; all except SDRAM 8, 9, 11 & 12
100
250
ps
VT = 1.5 V; all SDRAMs
VT = 1.5 V
220
350
ps
200
500
ps
tsk1
Skew
IOH = -11 mA
IOL = 9.4 mA
VOH = 2.0 V
VOL = 0.8 V
MIN
2.4
VOL = 0.4 V, VOH = 2.4 V
d t1 1
Duty Cycle
CONDITIONS
tsk2 1
tsk3
1
1
tjcyc-cyc
Jitter, Cycle-to-cycle
Guaranteed by design, not 100% tested in production.
1
Third party brands and names are the property of their respective owners.
8
ICS9248-128
Electrical Characteristics - REF/48MHz/SIO
TA = 0 - 70º C; VDD = 3.3 V +/- 5%, VDDL = 2.5 V +/- 5 %; C L = 20 pF (unless otherwise stated).
PARAMETER
Output High
Voltage
SYMBOL
VOH5
IOH = -12 mA
Output Low Voltage
VOL5
IOL = 10 mA
0.3
0.4
V
Output High Current
IOH5
VOH = 2.0 V
-18
22
mA
Output Low Current
Rise Time
Fall Time
Duty Cycle
IOL5
VOL = 0.8 V
VOL = 0.4 V, VOH = 2.4 V
VOH = 2.4V, VOL = 0.4 V
VT = 1.5 V
24
2.1
2.1
51
4
4
55
mA
ns
ns
%
600
1000
ps
400
500
ps
1
t r5
t f5 1
d t5 1
CONDITIONS
Jitter, Cycle-toVT = 1.5 V
t jcyc-cyc, REF1
Cycle, REF
Jitter, Cycle-toVT = 1.5 V
t jcyc-cyc, fixed 1
Cycle, fixed clock
1
Guaranteed by design, not 100% tested in production.
Third party brands and names are the property of their respective owners.
9
MIN
TYP
2.4
2.6
16
45
MAX
UNITS
V
ICS9248-128
General I2C serial interface information
The information in this section assumes familiarity with I2C programming.
For more information, contact ICS for an I2C programming application note.
How to Write:
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D2 (H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
• ICS clock will acknowledge each byte one at a time.
• Controller (host) sends a Stop bit
Controller (host) will send start bit.
Controller (host) sends the read address D3 (H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 6
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
How to Write:
Controller (Host)
Start Bit
Address
D2(H)
ICS (Slave/Receiver)
How to Read:
Controller (Host)
Start Bit
Address
D3(H)
ACK
Dummy Command Code
ICS (Slave/Receiver)
ACK
Byte Count
ACK
Dummy Byte Count
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
ACK
Stop Bit
Byte 0
Byte 0
Byte 1
Byte 1
Byte 2
Byte 2
Byte 3
Byte 3
Byte 4
Byte 4
Byte 5
Byte 5
Byte 6
Byte 6
Stop Bit
Notes:
1.
2.
3.
4.
5.
6.
The ICS clock generator is a slave/receiver, I2C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I2C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
Third party brands and names are the property of their respective owners.
10
ICS9248-128
CPU_STOP# Timing Diagram
CPU_STOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
CPU_STOP# is synchronized by the ICS9248-128. The minimum that the CPU clock is enabled (CPU_STOP# high pulse) is
100 CPU clocks. All other clocks will continue to run while the CPU clocks are disabled. The CPU clocks will always be stopped
in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPU clock on latency is less than
4 CPU clocks and CPU clock off latency is less than 4 CPU clocks.
Notes:
1. All timing is referenced to the internal CPU clock.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist. This signal is synchronized
to the CPU clocks inside the ICS9248-128.
3. All other clocks continue to run undisturbed. (including SDRAM outputs).
Third party brands and names are the property of their respective owners.
11
ICS9248-128
SDRAM_STOP# Timing Diagram
SDRAM_STOP# is an sychronous input to the clock synthesizer. It is used to turn off the CPU clocks for low power operation.
SDRAM_STOP# is synchronized by the ICS9248-128. All other clocks will continue to run while the SDRAM clocks are
disabled. The SDRAM clocks will always be stopped in a low state and start in such a manner that guarantees the high pulse
width is a full pulse.
Notes:
1. All timing is referenced to the internal CPU clock.
2. SDRAM is an asynchronous input and metastable conditions may exist. This signal is synchronized to
the SDRAM clocks inside the ICS9248-128.
3. All other clocks continue to run undisturbed.
Third party brands and names are the property of their respective owners.
12
ICS9248-128
PCI_STOP# Timing Diagram
PCI_STOP# is an synchronous input to the ICS9248-128. It is used to turn off the PCICLK (0:4) clocks for low power operation.
PCI_STOP# is synchronized by the ICS9248-128 internally. The minimum that the PCICLK (0:4) clocks are enabled (PCI_STOP#
high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with a full high pulse
width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one PCICLK clock.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. CPU_STOP# is shown in a high (true) state.
Third party brands and names are the property of their respective owners.
13
ICS9248-128
Shared Pin Operation Input/Output Pins
Figure 1 shows a means of implementing this function when
a switch or 2 pin header is used. With no jumper is installed
the pin will be pulled high. With the jumper in place the pin
will be pulled low. If programmability is not necessary, than
only a single resistor is necessary. The programming resistors
should be located close to the series termination resistor to
minimize the current loop area. It is more important to locate
the series termination resistor close to the driver than the
programming resistor.
The I/O pins designated by (input/output) on the ICS9248128 serve as dual signal functions to the device. During initial
power-up, they act as input pins. The logic level (voltage)
that is present on these pins at this time is read and stored
into a 5-bit internal data latch. At the end of Power-On reset,
(see AC characteristics for timing values), the device changes
the mode of operations for these pins to an output function.
In this mode the pins produce the specified buffered clocks
to external loads.
To program (load) the internal configuration register for these
pins, a resistor is connected to either the VDD (logic 1) power
supply or the GND (logic 0) voltage potential. A 10 Kilohm
(10K) resistor is used to provide both the solid CMOS
programming voltage needed during the power-up
programming period and to provide an insignificant load on
the output clock during the subsequent operating period.
Via to
VDD
Programming
Header
2K Via to Gnd
Device
Pad
8.2K Clock trace to load
Series Term. Res.
Fig. 1
Third party brands and names are the property of their respective owners.
14
ICS9248-128
General Layout Precautions:
1) Use a ground plane on the top layer
of the PCB in all areas not used by
traces.
Ferrite
Bead
VDD
2) Make all power traces and ground
traces as wide as the via pad for lower
inductance.
C1
Notes:
1) All clock outputs should have a
series terminating resistor, and a 20pF
capacitor to ground between the
resistor and clock pin. Not shown in
all places to improve readibility of
diagram.
C1
3.3V Power Route
2) Optional crystal load capacitors are
recommended. They should be
included in the layout but not
inserted unless needed.
Connections to VDD:
C2
22µF/20V
Tantalum
Ferrite
Bead
C2
22µF/20V
Tantalum
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
VDD
C3
2.5V Power Route
1
C4
Clock Load
C3
Ground
3.3V Power Route
= Routed Power
= Ground Connection Key (component side copper)
= Ground Plane Connection
= Power Route Connection
= Solder Pads
= Clock Load
Third party brands and names are the property of their respective owners.
15
ICS9248-128
SYMBOL
In Millimeters
In Inches
COMMON DIMENSIONS COMMON DIMENSIONS
MIN
MAX
MIN
MAX
A
2.413
2.794
.095
.110
A1
0.203
0.406
.008
.016
b
0.203
0.343
.008
.0135
c
0.127
0.254
.005
.010
D
SEE VARIATIONS
SEE VARIATIONS
E
10.033
10.668
.395
.420
E1
7.391
7.595
.291
.299
e
0.635 BASIC
h
0.381
0.635
L
0.508
1.016
N
SEE VARIATIONS
α
0°
0.025 BASIC
.015
.025
.020
.040
SEE VARIATIONS
8°
0°
8°
MIN
MAX
MIN
MAX
15.748
16.002
.620
.630
JEDEC MO-118
DOC# 10-0034
6/1/00
REV B
VARIATIONS
D mm.
N
48
D (inch)
Ordering Information
ICS9248yF-128
Example:
ICS XXXX y F - PPP
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
F=SSOP
Revision Designator
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Third party brands and names are the property of their respective owners.
16
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.