IMP IMP5112CDPT

IMP51 1 1/51 1 2
DATA COMMUNICATIONS
9-Line SCSI Terminator
Key Features
– 35MHz Channel Bandwidth
The 9-channel IMP5111/5112 SCSI terminator is part of IMP's family
of high-performance SCSI terminators that deliver true UltraSCSI performance. The BiCMOS design offers superior performance over first
generation linear regulator/resistor based terminators.
IMP's new architecture employs high-speed adaptive elements for each
channel, thereby providing the fastest response possible - typically
35MHz, which is 100 times faster than the older linear regulator terminator approach. The bandwidth of terminators based on the older
regulator/resistor terminator architecture is limited to 500kHz since a
large output stabilization capacitor is required. The IMP architecture
eliminates the external output compensation capacitor and the need
for transient output capacitors while maintaining pin compatibility
with first generation designs. Reduced component count is inherent
with the IMP5111/5112.
The IMP5111/5112 architecture tolerates marginal system designs. A key
improvement offered by the IMP5111/5112 lies in its ability to insure
reliable, error-free communications even in systems which do not adhere
to recommended SCSI hardware design guidelines, such as improper
cable lengths and impedance. Frequently, this situation is not controlled
by the peripheral or host designer.
Ultra-Fast response for Fast-20 SCSI applications
35MHz channel bandwidth
3.3V operation
Less than 3pF output capacitance
Sleep-mode current less than 275µA
Thermally self limiting
No external compensation capacitors
Implements 8-bit or 16-bit (wide) applications
Compatible with active negation drivers
(60mA/channel)
Compatible with passive and active terminations
Approved for use with SCSI 1, 2, 3 and UltraSCSI
Hot swap compatible
Pin-for-pin compatible with LX5211 and
UC5606 (IMP5111)
Pin-for-pin compatible with LX5212 and
UC5603/5613/5614 (IMP5112)
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For portable and configurable peripherals, the IMP5111/5112 can be
placed in a sleep mode with a disconnect signal. Quiescent current is less
than 275µA when disabled. When disabled, the outputs are in a high
impedance state with output capacitance less than 3pF.
Block Diagrams
Term Power
Thermal
Limiting
Circuit
Current
Biasing
Circuit
24mA Current
Limiting Circuit
DATA OUTPUT
PIN DB (0)
2.85V
DISCONNECT (IMP5111)
DISCONNECT (IMP5112)
–
1 of 9 Channels
+
1.4V
5111/5112_01.eps
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Pin Configuration
SO-16
T7
1
T8
2
T9
3
HEAT SINK/GND
4
IMP5111
IMP5112
TSSOP-24
16 T6
T7
1
24 T6
15 T5
T8
2
23 T5
14 NC
T9
3
22 NC
13 HEAT SINK/GND
NC
4
21 NC
12 HEAT SINK/GND
GND
5
20 HEAT SINK/GND
GND
5
DISCONNECT*
6
11 VTERM
HEAT SINK/GND
6
T1
7
10 T4
HEAT SINK/GND
7
18 HEAT SINK/GND
T2
8
9
HEAT SINK/GND
8
17 HEAT SINK/GND
HEAT SINK/GND
9
16 NC
* DISCONNECT (IMP5111)
DISCONNECT (IMP5112)
DW Package
T3
5111/5112__02.eps
IMP5111
IMP5112
DISCONNECT* 10
19 HEAT SINK/GND
15 VTERM
T1 11
14 T4
T2 12
13 T3
* DISCONNECT (IMP5111)
DISCONNECT (IMP5112)
PW Package
5111/5112_02a.eps
Ordering Information
Part Number
Temperature Range
Package
IMP5111CDP
0°C to 125°C
16-pin Plastic SO
IMP5111CDPT
0°C to 125°C
Tape and Reel, 16-pin Plastic SO
IMP5111CPWP
0°C to 125°C
24-pin Plastic TSSOP
IMP5111CPWPT
0°C to 125°C
Tape and Reel, 24-pin Plastic TSSOP
IMP5112CDP
0°C to 125°C
16-pin Plastic SO
IMP5112CDPT
0°C to 125°C
Tape and Reel, 16-pin Plastic SO
IMP5112CPWP
0°C to 125°C
24-pin Plastic TSSOP
IMP5112CPWPT
0°C to 125°C
Tape and Reel, 24-pin Plastic TSSOP
5111/5112_t01.at3
Absolute Maximum Ratings1
TermPwr Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . +7V
Signal Line Voltage . . . . . . . . . . . . . . . . . . . . . . . . 0V to +7V
Regulator Output Current . . . . . . . . . . . . . . . . . . 0.4A
Operating Junction Temperature
Plastic (DP, PWP Packages) . . . . . . . . . . . . . . . 150°C
Storage Temperature Range . . . . . . . . . . . . . . . . . -65°C to 150°C
Lead Temperature (Soldering, 10 seconds) . . . . . 300°C
Note: 1. Exceeding these ratings could cause damage to the device. All
voltages are with respect to Ground. Currents are positive
into, negative out of the specified terminal.
Thermal Data
DP Package:
Thermal Resistance Junction-to-Leads, θJL . . . . . . . . 20°C/W
Thermal Resistance Junction-to-Ambient, θJA . . . . . . 50°C/W
PW Package:
Thermal Resistance Junction-to-Leads, θJL . . . . . . . . 27°C/W
Thermal Resistance Junction-to-Ambient, θJA . . . . . . 100°C/W
2
Junction Temperature Calculation: TJ = TA + (PD x θJA).
The θJA numbers are guidelines for the thermal performance of the
device/pc-board system. All of the ambient airflow is assumed.
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Recommended Operating Conditions2
Parameter
Symbol
Min
VTERM
VIH
TermPwr Voltage
High Level Enable Input Voltage
IMP5111
IMP5112
IMP5111
Low Level Disable Input Voltage
VIL
IMP5112
Operating Junction Temperature Range
Note:
Typ
Max
Units
3.3
5.5
V
2
VTERM
V
0
0.8
0
0.8
2
VTERM
0
125
V
°C
5111/5112_t02.eps
2. Recommended operating conditions indicate the range over which the device is functional.
Electrical Characteristics
Unless otherwise specified, these specifications apply at an ambient operating temperature of TA = 25°C. TermPwr = 4.75V. Low duty cycle
pulse testing techniques are used which maintain junction and case temperatures equal to the ambient temperature.
Parameter
Symbol Conditions
Output High Voltage
VOUT
Output Leakage Current
2.65
2.85
Max
9
All data lines = 0.5V
215
225
IMP5111
DISCONNECT Pin < 0.8V
275
IMP5112
DISCONNECT Pin > 2.0V
275
IOUT
IMP5111
IMP5112
IMP5111
IIN
IIN
IOL
IMP5112
Capacitance in DISCONNECT Mode
COUT
Channel Bandwidth
BW
Termination Sink Current, per Channel
ISINK
VOUT = 0.5V
–21
–23
Units
V
6
ICC
Output Current
DISCONNECT Input Current
Typ
All data lines = Open
TermPwr Supply Current
DISCONNECT Input Current
Min
mA
µA
–24
mA
DISCONNECT Pin = 4.75V
10
nA
DISCONNECT Pin = 0V
–90
µA
DISCONNECT Pin = 0V
–90
µA
DISCONNECT Pin = 4.75V
10
nA
DISCONNECT Pin < 0.8V, VO = 0.5V
10
nA
DISCONNECT Pin > 2.0V, VO = 0.5V
10
VOUT = 0V, Frequency = 1MHz
3
pF
35
MHz
60
mA
VOUT = 4V
5111/5112_t03.eps
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Application Information
Figure 1. Receiving Waveform – 20MHz
Figure 2. Driving Waveform – 20MHz
Receiver
Driver
1 Meter, AWG 28
IMP5111
IMP5112
IMP5111
IMP5112
5111/5112_03.eps
Figure 3.
IMP5111/IMP5112 Maximizes Line Current
Disable /Sleep Mode
Cable transmission theory suggests to optimize signal speed and
quality, the termination should act both as an ideal voltage reference when the line is released (deasserted) and as an ideal
current source when the line is active (asserted). Common active
terminators which consist of linear regulators in series with resistors (typically 110Ω) are a compromise. With coventional linear
terminators as the line voltage increases the amount of current
decreases linearly by the equation;
The IMP5111 has an active LOW disconnect pin, and the IMP5112
has an active HIGH disconnect pin. The disable mode is entered
if the disconnect pin on either device is left open.
(VREF − VLINE) = I.
When disabled the termination lines are in a high impedance
state, and the power supply current drops to 275µA typically. The
disable mode can be used to save power or completely eliminate
the terminator from the SCSI bus.
Disabled terminators appear as distributed capacitance on the
bus. The IMP5111/5112 have been optimized to have only 3pF of
capacitance per output when in the disabled mode.
R
The IMP5111/5112, with their unique architecture, applies the
maximum amount of current regardless of line voltage until the
termination high threshold (2.85V) is reached.
The IMP5111/5112 are compatible with active negation drivers.
The devices will handle up to 60mA of sink current for drivers
which exceed the 2.85V output high level.
Table 1. Power Up/ Power Down Function Table
IMP5111
DISCONNECT
IMP5112
DISCONNECT
Outputs
Quiescent Current
H
L
Enabled
6mA
L
H
Disabled/High Impedance
275µA
Open
Open
Disabled/High Impedance
275µA
5111/5112_t04a.eps
4
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IMP51 1 1/51 1 2
Package Dimensions
SO (16-Pin)
Inches
Millimeters
Min
Max
0.053
0.004
0.014
0.007
0.385
0.150
0.069
0.010
0.018
0.010
0.394
0.158
Min
Max
1.35
0.10
0.35
0.19
9.78
3.81
1.75
0.25
0.46
0.25
10.01
4.01
SO (16-Pin)*
E
A
A1
B
C
D
E
H
D
M
A
C
e
L
B
A1
16-Pin (SO).eps
e
H
L
M
0.050 BSC
0.228
0.016
0°
0.244
0.050
8°
1.27 BSC
6.20
1.27
8°
5.79
0.40
0°
TSSOP (24-Pin)
A
B
C
D
E
TSSOP (24-Pin)
F
E
0.041
0.012
0.0071
0.311
0.176
1 2 3
E
F
0.80
0.19
0.09
7.70
4.30
0.025 BSC
G
0.002
0.005
0.0433
—
H
L
0.020
0.028
M
0°
8°
P
0.246
0.256
* JEDEC Drawing MS-012AC
P
D
0.032
0.007
0.0035
0.303
0.169
1.05
0.30
0.180
7.90
4.48
0.65 BSC
0.05
—
0.50
0°
6.25
0.15
1.10
0.70
8°
6.50
5111/5112_t06.at3
A H
SEATING PLANE B
G
L
M
C
24-Pin (TSSOP).eps
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Daily Silver IMP Microelectronics Co.,Ltd
7 Keda Road , Hi-Tech Park,
NingBo,Zhejiang, P.R.C.
Post Code : 315040
Tel:(086)-574-87906358
Fax:(086)-574-87908866
e-mail:[email protected]
http://www.ds-imp.com.cn
The IMP logo is a registered trademark of Daily Silver IMP.
All other company and product names are trademarks of their respective owners.
2005 Daily Silver IMP
Revision : A
Issue Date: 08 / 08 / 05
Type: Product