IPD80N06S3-09 OptiMOS®-T Power-Transistor Product Summary V DS 55 V R DS(on),max 8.4 mΩ ID 80 A Features • N-channel - Normal Level - Enhancement mode • Automotive AEC Q101 qualified PG-TO252-3-11 • MSL1 up to 260°C peak reflow • 175°C operating temperature • Green package (RoHS compliant) • Ultra low Rds(on) • 100% Avalanche tested Type Package Marking IPD80N06S3-09 PG-TO252-3-11 QN0609 Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Continuous drain current1) ID Conditions T C=25 °C, V GS=10 V T C=100 °C, V GS=10 V2) Value 80 Unit A 48 Pulsed drain current2) I D,pulse T C=25 °C 320 Avalanche energy, single pulse2) E AS I D=40 A 240 mJ Avalanche current, single pulse I AS 80 A Gate source voltage3) V GS ±20 V Power dissipation P tot 107 W Operating and storage temperature T j, T stg -55 ... +175 °C T C=25 °C IEC climatic category; DIN IEC 68-1 Rev. 1.1 55/175/56 page 1 2007-11-07 IPD80N06S3-09 Parameter Symbol Values Conditions Unit min. typ. max. - - 1.4 minimal footprint - - 62 6 cm2 cooling area4) - - 40 Thermal characteristics2) Thermal resistance, junction - case R thJC SMD version, device on PCB R thJA K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D= 1 mA 55 - - Gate threshold voltage V GS(th) V DS=V GS, I D=55 µA 2.1 3.0 4 Zero gate voltage drain current I DSS V DS=55 V, V GS=0 V, T j=25 °C - 0.01 1 - 1 100 V DS=55 V, V GS=0 V, T j=125 °C2) V µA Gate-source leakage current I GSS V GS=20 V, V DS=0 V - 1 100 nA Drain-source on-state resistance RDS(on) V GS=10 V, I D=40 A - 7.2 8.4 mΩ Rev. 1.1 page 2 2007-11-07 IPD80N06S3-09 Parameter Symbol Values Conditions Unit min. typ. max. - 5300 6100 - 800 1200 Dynamic characteristics2) Input capacitance C iss Output capacitance C oss Reverse transfer capacitance Crss - 780 1170 Turn-on delay time t d(on) - 23 - Rise time tr - 42 - Turn-off delay time t d(off) - 26 - Fall time tf - 37 - Gate to source charge Q gs - 38 51 Gate to drain charge Q gd - 20 30 Gate charge total Qg - 76 88 Gate plateau voltage V plateau - 7.0 - V - - 80 A - - 320 - 0.9 1.3 V - 43 - ns - 58 - nC V GS=0 V, V DS=25 V, f =1 MHz V DD=27.5 V, V GS=10 V, I D=80 A, R G=5.1 Ω pF ns Gate Charge Characteristics2) V DD=11 V, I D=80 A, V GS=0 to 10 V nC Reverse Diode Diode continous forward current2) IS Diode pulse current2) I S,pulse Diode forward voltage V SD Reverse recovery time2) t rr Reverse recovery charge2) Q rr T C=25 °C V GS=0 V, I F=80 A, T j=25 °C V R=27.5 V, I F=I S, di F/dt =100 A/µs 1) Current is limited by bondwire; with an R thJC = 1.4 K/W the chip is able to carry 84 A at 25°C. For detailed information see Application Note ANPS071E. 2) Defined by design. Not subject to production test. 3) Qualified at -5V and +20V. 4) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.1 page 3 2007-11-07 IPD80N06S3-09 1 Power dissipation 2 Drain current P tot = f(T C); V GS ≥ 6 V I D = f(T C); V GS ≥ 6 V 120 100 100 80 80 I D [A] P tot [W] 60 60 40 40 20 20 0 0 0 50 100 150 200 0 50 T C [°C] 100 150 200 T C [°C] 3 Safe operating area 4 Max. transient thermal impedance I D = f(V DS); T C = 25 °C; D = 0 Z thJC = f(t p) parameter: t p parameter: D =t p/T 1000 101 1 µs 100 10 µs 100 0.5 Z thJC [K/W] 100 µs I D [A] 1 ms 0.1 10-1 0.05 0.01 10 10-2 single pulse 10-3 1 0.1 1 10 100 10-6 10-5 10-4 10-3 10-2 10-1 100 t p [s] V DS [V] Rev. 1.1 10-7 page 4 2007-11-07 IPD80N06S3-09 5 Typ. output characteristics 6 Typ. drain-source on-state resistance I D = f(V DS); T j = 25 °C R DS(on) = f(I D); T j = 25 °C parameter: V GS parameter: V GS 320 20 6V 20 V 7V 10 V 8V 280 240 15 9V R DS(on) [mΩ] 200 I D [A] 9V 160 8V 120 10 V 10 7.5 V 7V 80 5 6.5 V 6V 40 5.5 V 0 0 0 2 4 6 8 10 0 50 100 V DS [V] 150 200 I D [A] 7 Typ. transfer characteristics 8 Typ. drain-source on-state resistance I D = f(V GS); V DS = 6 V R DS(on) = f(T j); I D = 80 A; V GS = 10 V parameter: T j 16 200 -55 °C 14 25 °C 150 12 R DS(on) [mΩ] I D [A] 175 °C 100 10 8 50 6 0 4 0 2 4 6 8 10 V GS [V] Rev. 1.1 -60 -20 20 60 100 140 180 T j [°C] page 5 2007-11-07 IPD80N06S3-09 9 Typ. gate threshold voltage 10 Typ. capacitances V GS(th) = f(T j); V GS = V DS C = f(V DS); V GS = 0 V; f = 1 MHz parameter: I D 104 4 Ciss 3.5 Coss 600µA 3 C [pF] V GS(th) [V] Crss 60µA 2.5 103 2 1.5 102 1 -60 -20 20 60 100 140 0 180 5 10 T j [°C] 15 20 25 V DS [V] 11 Typical forward diode characteristicis 12 Typ. avalanche characteristics IF = f(VSD) I AV = f(t AV) parameter: T j parameter: T j(start) 100 103 25°C 100°C 150°C I F [A] I AV [A] 102 101 175 °C 25 °C 0.6 0.8 100 1 0 0.2 0.4 1 1.2 1.4 V SD [V] Rev. 1.1 10 0.1 1 10 100 1000 t AV [µs] page 6 2007-11-07 IPD80N06S3-09 13 Typical avalanche Energy 14 Drain-source breakdown voltage E AS = f(T j) V BR(DSS) = f(T j); I D = 1 mA parameter: I D 65 600 500 20 A 60 300 V BR(DSS) [V] E AS [mJ] 400 40 A 55 200 50 80 A 100 45 0 0 50 100 150 -60 200 -20 T j [°C] 20 60 100 140 180 T j [°C] 15 Typ. gate charge 16 Gate charge waveforms V GS = f(Q gate); I D = 80 A pulsed parameter: V DD 12 V GS 11 V 44 V Qg 10 V GS [V] 8 V plateau 6 V g s(th) 4 2 Q g (th) Q sw Q gs 0 0 50 100 Q gate Q gd 150 Q gate [nC] Rev. 1.1 page 7 2007-11-07 IPD80N06S3-09 Published by Infineon Technologies AG 81726 Munich, Germany © Infineon Technologies AG 2007 All Rights Reserved. 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Rev. 1.1 page 8 2007-11-07 IPD80N06S3-09 Revision History Version Changes Date Revision 2.1 Eas @ Id = 38A instead of 50A, 26.07.2007 according to D²PAK product Revision 2.1 Update of diagram 12 and 13 26.07.2007 according to Eas @ Id = 38A Data Sheet version 1.1 Implementation of avalanche 07.11.2007 current single pulse Data Sheet version 1.1 07.11.2007 Update of package drawing Data Sheet version 1.1 Update of avalanche diagram 12 07.11.2007 and 13 Data Sheet version 1.1 implementation of footnote 2 for 07.11.2007 Eas specification Data Sheet version 1.1 07.11.2007 Vgsth measured at 55µA Rev. 1.1 page 9 2007-11-07