Data Sheet No. PD60233 revB IR2277S/IR2177S(PbF) Phase Current Sensor IC for AC motor control Features • Floating channel up to 600 V for IR2177 & 1200 V for Product Summary VOFFSET (max) IR2277 • • • • • • • IR2277 1200 V IR2177 600 V Vin range ±250mV Bootstrap supply range 8-20 V 2.2 mA Fast Over Current detection Floating channel quiescent current (max) Sensing latency (max) Suitable for bootstrap power supplies Throughput Synchronous sampling measurement system High PWM noise (ripple) rejection capability Digital PWM output Low sensing latency (<7.5 µsec @20kHz) Ratiometric analog output suitable for DSP A/D interface Over Current threshold (max) 7.5 µsec (@20kHz) 40ksample/sec (@20kHz) ±470 mV Description IR2177/IR2277 is a high voltage, high speed, single phase current sensor interface for AC motor drive applications. The current is sensed by an external shunt resistor. The IC converts the analog voltage into a time interval through a precise circuit that also performs a very good ripple rejection showing small group delay. The time interval is level shifted and given to the output both as a PWM signal (PO) and analog voltage (OUT). The analog voltage is proportional to the measured current and is ratio metric with respect to an externally provided voltage reference. The max throughput is 40 ksample/sec suitable for up to 20 kHz asymmetrical PWM modulation and max delay is <7.5 µsec (@20kHz). Also a fast over current signal is provided for IGBT protection. Package Typical Connection (Please refer to Lead Assignments for correct pin configuration. This diagram shows electrical connections only) 1 www.irf.com IR2277S/IR2177S(PbF) Absolute Maximum Ratings Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute voltages referenced to VSS, all currents are defined positive into any lead. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air conditions. Symbol Definition VB High Side Floating Supply Voltage VS Vin+ / VinG0 / G1 VCC Sync VRH/VRL Out PO OC dVS/dt PD RthJA TJ TS TL High Side Floating Ground Voltage High-Side Inputs Voltages High-Side Range Selectors Low-Side Fixed Supply Voltage Low-Side Input Synchronization Signal DSP Reference High and Low Voltages Analog Output Voltage PWM Output Over Current Output Voltage Allowable Offset Voltage Slew Rate Maximum Power Dissipation Thermal Resistance, Junction to Ambient Junction Temperature Storage Temperature Lead Temperature (Soldering, 10 seconds) IR2277 IR2177 Min. Max. - 0.3 - 0.3 VB - 25 VS - 5 VS - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 - 0.3 1225 625 VB + 0.3 VB + 0.3 VB + 0.3 25 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 VCC + 0.3 50 250 90 125 150 300 -40 -55 Units V V V V V V V V V V V/ns mW ºC/W ºC ºC ºC Recommended Operating Conditions For proper operation the device should be used within the recommended conditions. All voltage parameters are absolute voltages referenced to Vss. The Vs offset rating is tested with all supplies biased at 15V differential. Symbol VBS Definition High Side Floating Supply Voltage (VB- VS) VS High Side Floating Ground Voltage Vin+ / VinG0 / G1 VCC Sync fsync High-Side Inputs Voltages High-Side Range Selectors Low Side Logic Fixed Supply Voltage Low-Side Input Synchronization Signal Sync Input Frequency PO OC VRH VRL TA PWM Output Over Current Output Voltage OUT Reference High Voltage OUT Reference Low Voltage Ambient Temperature Note 1: Shorted to VS or VB Note 2: Pull-Up Resistor to VCC 2 IR2277 IR2177 Using PO Using OUT Min. Max. Units VS + 8.0 VS + 20 1200 600 VS + 5.0 Note1 20 VCC 20 20 Note 2 Note 2 VCC-2.5 VRH-3 125 V -5 VS - 5.0 Note 1 8 VSS 4 8 -0.3 -0.3 3 VSS -40 V V V V kHz V V V V ºC www.irf.com IR2277S/IR2177S(PbF) Static Electrical Characteristics VCC, VBS = 15V unless otherwise specified. Temp=27°C; Vin=Vin+ - Vin. Pin: VCC, VSS, VB, VS Symbol Definition IQBS Quiescent VBS supply current IQCC Quiescent VCC supply current ILK Offset supply leakage current Min. Typ. Max. Units Test Conditions 1 2.2 mA fsync = 10kHz, 20kHz 6 mA IR2277 50 IR2177 50 fsync = 10kHz, 20kHz VB = VS = 1200V µA VB = VS = 600V Pin: Vin+, Vin-, Sync, G0, G1, OC Symbol Definition Min. Typ. Max. 250 -250 Vinmax Vinmin VIH Maximum input voltage before saturation Minimum input voltage before saturation Sync Input High threshold VIL Sync Input Low threshold Vhy Sync Input Hysteresis 0.2 Ivinp Vin+ input current -18 -6 µA Ipu G0, G1 pull-up Current -20 -8 µA |Vocth| RSync Over Current Activation Threshold SYNC to VSS internal pull-down 300 6 470 12 mV kΩ RonOC Over Current On Resistance 25 75 Ω 2.2 0.8 Test Conditions Units mV mV V V See Figure 1 See Figure 1 V See Figure 1 fsync = 4kHz to 20kHz G1, G0 = VB5V @ I = 2mA See Figure 3 Schmitt trigger SYNC Rsync VIL VIH VSS Vhy Figure 1: Sync input thresholds Figure 2: Sync input circuit www.irf.com IR2277S/IR2177S(PbF) Pin: PO Symbol Definition Min. Typ. VPOs Input offset voltage measured by PWM output ∆VPOs / ∆Tj Input offset voltage temperature drift ∆VPOs ∆offset between samples on channel1 and channel2 measured at PO (See Note1) -10 Gp PWM Output Gain -38 ∆Gp / ∆Tj PWM Output Gain Temperature Drift CMRR PO PO Output common mode (VS) rejection 0.2 VPOlin PO Linearity 0.07 -50 -40.5 mV Rpull-up=500 Ω fsync = 4, 20kHz Vthreshold=2.75V Ext supply=5V (See Figure 6) mV fsync = 10kHz See Figure 6 -42.5 %/V Vin=±250mV %/(V*ºC) m%/V 0.2 0.8 1.6 0.2 PO On Resistance Test Conditions 10 TBD PO threshold for OC reset Units µV/°C TBD PSRR PO PSRR for PO Output RonPO 20 TBD ∆ Vlin/ ∆Tj PO Linearity Temperature Drift VthPO Max. 25 75 Vs-Vss = 0, 600V fsync = 10kHz % 10kHz %/ºC 10kHz OC active (See Figure 4) V %/V Ω VCC=VBS= 8,20V @ I = 2mA See Figure 3 Note1: Refer to PO output description for channels definition PO or OC RON VSS Internal signal Figure 3: PO and OC open collector circuit 4 www.irf.com IR2277S/IR2177S(PbF) Pin: OUT, VRH, VRL Symbol Definition Min. Typ. RREF VRH to VRL input resistance 36 Vaos Input offset voltage measured by analog output -100 ∆ Vaos / ∆Tj Input offset voltage temperature drift ∆Vaos ∆offset between samples on channel1 and channel2 measured at OUT (Note1) Ga Analog Output Gain ∆Ga / ∆Tj Analog Output Gain Temperature Drift TBD CMRR OUT Analog Output common mode (VS offset) rejection 100 VOUTlin Out Linearity 0.3 ∆ Vlin / ∆Tj PSRR OUT Max. Units 84 kΩ 50 TBD mV µV / ºC Test Conditions fsync = 8kHz, 20 kHz Measured by analog output fsync = 8kHz, 20 kHz -20% Out Linearity Temperature Drift 2VR +20% V/V ºC -1 dB 0.7 TBD VR=VRH-VRL=3V % %/ºC Vs-Vss=0V, 600V fsync = 10kHz fsync = 8kHz, 20kHz fsync = 8kHz, 20kHz VCC= VBS =8V, 20V PSRR for Analog Output 30 100 dB VOUTl Vout Low Saturation 0 50 mV Vin= -500mV VOUTh Vout High Saturation VRH+0.2 VRH+0.7 V Vin = +500mV Note1: Refer to PO output description for channels definition 5 www.irf.com IR2277S/IR2177S(PbF) AC Electrical Characteristics VBIAS (VCC, VBS) = 15V unless otherwise specified. Temp=27°C. Symbol Definition fsync PWM frequency fout Throughput BW Bandwidth (@ -3 dB) GD Group Delay (input filter) Dmin Min. Typ. Max. PO 4 20 OUT 8 20 Units Test Conditions kHz 2 ⋅ f sync ksample/sec f sync kHz 1 4 ⋅ f sync µs Minimum Duty Cycle (Note 1) 10 % Vin=+Vinmax Dmax Maximum Duty Cycle (Note 1) 30 % Vin=-Vinmin tdOCon De-bounce time of OC 4.7 µs See Figure 4 TOCoff Time to reset OC forcing PO 0.5 µs See Figure 4 Cload Analog output load capacitor 0 50 nF NOTE 2 SLOUT tsettl Analog output (OUT) Slew Rate Output settling time (1%) 0.2 5 V/µs µs Cout ≤ 5 nF Cout ≤ 5 nF MD Measure Delay 1 30 0.30 2 ⋅ f sync SR Step response (max time to reach steady state) for PO output SROUT Step response (max time to reach steady state) for OUT output 2.7 3.5 µs See 0.51 f sync 1. 3 f sync µs 0.51 + t settl f sync 1 .3 + t settl f sync µs Figure 5 See Figure 5 Note 1: negative logic, see Figure 4 on page 7 Note 2: Cload < 5 nF avoids overshoot 6 www.irf.com IR2277S/IR2177S(PbF) Figure 4: OC timing diagram Vmax Vin Vmin SYNC PO SR (PO full response time) VRH MD OUT tsettl VRL SROUT (OUT full response time) Figure 5: timing diagram 7 www.irf.com IR2277S/IR2177S(PbF) Vmax Vin Vmin SYNC Supply=5V PO Vth=2.75V GP *VPOs1 20% GP *VPOs1 GP *VPOs0 20% 20% GP *VPOs0 20% DVPOs= VPOs1-VPOs0 Figure 6: ∆offset between two consecutive samples measured at PO 8 www.irf.com IR2277S/IR2177S(PbF) Lead Assignments SOIC16WB Lead Definitions 9 Pin Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 VCC OUT VSS VRL VRH OC PO Sync NC NC G0 G1 VS VINVIN+ VB Description Low side voltage supply Analog output Low side ground supply Lower rail of A/D voltage range Higher rail of A/D voltage range Over current signal (open drain) PWM output (open drain) DSP synchronization signal No connection No connection Integrator gain lsb Integrator gain msb High side return Negative sense input Positive sense input High side supply www.irf.com IR2277S/IR2177S(PbF) Timing and logic state diagrams description ** See OC and PO detailed descriptions below in this document Functional block diagram 10 www.irf.com IR2277S/IR2177S(PbF) 1 Device Description 1.1 SYNC input Sync input clocks the whole device. In order to make the device work properly it must be synchronous with the triangular PWM carrier as shown in Figure 8. SYNC pin is internally pulled-down (10 kΩ) to VSS. 1.2 PWM Output (PO) PWM output is an open collector output (active low). It must be pulled-up to proper supply with an external resistor (suggested value between 500Ω and 10kΩ). τ Supply Vlow Figure 7: PO rising and falling slopes PO pull-up resistor determines the rising slope of the PO output and the lower value of PO as shown in Figure 7, where τ = RC , C is the total PO pin capacitance and R is the pull-up resistance. Vlow Ron = Supply ⋅ R on + R pull −up where Ron is the internal open collector resistance and Rpull-up is the external pull-up resistance. PO duty cycle is defined for active low logic by the following formula: Eq. 1 Dn = Toff _ cycle _ n +1 Tcycle _ n PO duty cycle (Dn) swings between 10% and 30%. Zero input voltage corresponds to 20% duty cycle. 11 A residual offset can be read in PO duty cycle according to VPOs (see Static electrical characteristics). According to Figure 8, it can be assumed that odd cycles are represented by SYNC at high level (let’s name channel 1 the output related to this state of SYNC) and even cycles represented by SYNC at low level (channel 2). The two channels are independent in order to provide the correct duty cycle value of PO even for non-50% duty cycle of SYNC signal. Small variation of SYNC duty cycle are then allowed and automatically corrected when calculating the duty cycle using Eq. 1. However, channel 1 and channel 2 can have a difference in offset value which is specified in ∆VPOS (see Static electrical characteristics). To implement a correct offset compensation of PO duty cycle and analog OUT, each channel must be compensated separately. 1.3 Over Current output (OC) OC output is an open drain pin (active low). A simplified block diagram of the over current circuit is shown in the Figure 9. Over current is detected when |Vin|=|Vinp-Vinm|>VOCth. If an event of over current lasts longer than tdOCon, OC pin is forced to VSS and remains latched until PO is externally forced low for at least tOCoff (see timing on Figure 4). During an over current event (OC is low), PO is off (pulled-up by external resistor). If OC is reset by PO and over current is still active, OC pin will be forced low again by the next edge of SYNC signal. To reset OC state PO must be forced to VSS for at least TOCoff. • Autoreset function The autoreset function consists in clearing automatically the OC fault. To enable the autoreset function, simply short circuit the OC pin with the PO pin. www.irf.com IR2277S/IR2177S(PbF) Cycle 1 Cycle 2 Cycle 3 Cycle 4 Triangular SYNC (0) PO Toff_cycle1 Tcycle1 Dn1 = Toff_cycle2 Toff _ cycle2 Tcycle2 Tcycle1 Dn2 = Toff_cycle3 Toff _ cycle3 Tcycle2 Tcycle3 Dn3 = Toff_cycle4 Toff _ cycle4 Tcycle3 Figure 8: PO Duty Cycle H igh voltage V IN + V IN - O ver current detection Level shifter E xt supply Low voltage S D OC V SS R PO Figure 9: Over current block diagram 12 www.irf.com IR2277S/IR2177S(PbF) 1.4 Analog Output (OUT) The analog output is internally buffered and capable of driving capacitive loads ranging up to 50nF. VRH and VRL set the dynamic range and gain of OUT pin. Additional circuitry to protect A/D converter input against excessive voltage is not required. Hereafter follow some definitions (see Figure 10 and following). • • Vin=Vinp-Vinm Input referred analog offset (Vaos): It is the input that gives an output that equals V RH + V RL (referred to VSS). 2 ∆OUT Gain: It is defined by the ratio Ga= . ∆Vin OUT VRH VRH+VRL 2 VRL Vin VSS Vaos OUT = • • Linearity: It is defined by the maximum difference between the ideal OUT/Vin curve and the measured curve depurated of the offset voltage and the gain error. Figure 10: Input offset definition OUT VRH OUT The analog output is also defined by some dynamic characteristics (see figure 8): • • • • Slew Rate (SLOUT). The maximum slope of OUT measured in V/µs Settling time (tsettl). Time needed by the analog output (OUT) to reach 90% of final value. Measure delay (MD). It is defined by the time interval between the actual SYNC edge and PO rising edge. Step response (SR). Is the time needed by Output to reach the final value after a step of the input. Is always within the following range: (Vpos if PO is measured instead of OUT) Ga Gid VRL Vin Vin VSS Figure 11: Gain definition OUT VRH Linearity Error 1 1 + MD + t settl ≤ SROUT ≤ + MD + t settl 2 ⋅ f SYNC f SYNC Ga Gid VRL Vin VSS Figure 12: Linearity error definition 13 www.irf.com IR2277S/IR2177S(PbF) 1.5 DC transfer functions Eq. 3 The working principle of the device can be easily explained by Figure 13, in which the main signals are represented. Triangular reference OUT = 2 ⋅ (VRH − VRL ) ⋅ Vin + The same equation can be referred to VRL, as follows in Eq. 4: Eq. 4 OUT − VRL = 2 ⋅ (VRH − VRL ) ⋅ Vin + SYNC VRH + VRL 2 OUT Vin VRH − VRL 2 VRH PO VRH OUT (VRH+VRL)/2 VRL Figure 13: Main current sensor signals and outputs Eq. 2 Dn = 20% − 40 200mV 100mV 0mV -100mV -200mV 250mV Vin VRL -250mV PWM out (PO pin) gives a duty cycle which is inversely proportional to the input signal while the OUT pin gives the analog converted output. Eq. 2 gives the resulting Dn of the PWM output (PO pin): Figure 15: ideal OUT/Vin transfer function % ⋅ Vin V where Vin = Vinp-Vinm PO duty cycle 30% 25% 20% 15% 10% Vin Figure 14: PO Duty Cycle (Dn) The Voltage-to-Time conversion (Vin to PO) must be reconstructed (see Functional Block Diagram) to give an analog voltage output at OUT pin. OUT pin swings from VRL to VRH, so the analog output (referred to VSS) follows Eq. 3: 14 www.irf.com IR2277S/IR2177S(PbF) Filter AC characteristic IR2177/2277 signal path can be considered as composed by three stages in series (see Figure 17). The first two stages perform the filtering action. Stage 1 (input filter) implements the filtering action originating the transfer function shown in Figure 18. The input filter is a self-adaptive reset integrator which performs an accurate ripple cancellation. This stage extracts automatically the PWM frequency from Sync signal and puts transmission zeros at even harmonics, rejecting the unwanted PWM noise. The following timing diagram shows the principle by which even harmonics are rejected (Figure 16). As can be seen from Figure 18, the odd harmonics are rejected as a first order low pass filter with a single pole placed in fPWM. The input filter group delay in the pass-band is very low (see GD on AC electrical characteristics) due to the beneficial action of the zeroes. The second stage samples the result of the first stage at double Sync frequency. This action can be used to fully remove the odd harmonics from the input signal. To perform this cancellation it is necessary a shift of 90 degrees of the SYNC signal with respect to the triangular carrier edges (SYNC2). The following timing diagrams show the principle of odd harmonics cancellation (Figure 19), in which SYNC2 allows the sampling of stage 1 output during odd harmonic zero crossings. Odd harmonic cancellation using SYNC2 (i.e. 90 degree shifted SYNC signal) signal will introduce Tsync/4 additional propagation delay. Anther way to obtain the same result (odd harmonics cancellation) can be achieved by controller computing the average of two consecutive PO results using SYNC1 (SYNC is in this case aligned to triangular edges, i.e. 0 degree shift). This method is suitable for most symmetric (center aligned) PWM schemes. For this particular PWM scheme another suitable solution is driving the IR2x77 with a half frequency SYNC signal (fsync=fPWM/2). In this case the cut frequency of the input filter is reduced by half allowing zeroes to be put at fPWM multiples (i.e. even and odd harmonics cancellation, no more computational effort needed by the controller). Figure 16: Even harmonic cancellation principle Figure 17: Simplified block diagram 15 www.irf.com IR2277S/IR2177S(PbF) Figure 18: Input filter transfer function (10 kHz PWM) 16 www.irf.com IR2277S/IR2177S(PbF) Switching level Triangular Phase voltage Phase current Current Mean Fundamental harmonic Third harmonic Stage 1 input: Input signal components (1st and 2nd harmonic only) Fundamental harmonic Third harmonic SYNC 1 Error SYNC 2 Stage 1 output Sampling instant Sampling instant Figure 19: Even harmonic cancellation principle G0 and G1 pins are used to change the time constant of the integrators of the high side input filter. To avoid internal saturation of the input filter, G0 and G1 must be connect according to SYNC frequency as shown in Table 1. A too small time constant may saturate the internal integrator, while a large time constant may reduce accuracy. G0 and G1 do not affect the overall current sensor gain. f PWM G0 G1 > 16 kHz * VB VB 16 / 10 kHz VS VB 10 / 6 kHz VB VS < 6 kHz VS VS *Æ 40 kHz Table 1: G0, G1 gain settings 2 Sizing tips 2.1 Bootstrap supply The VBS1,2,3 voltage provides the supply to the high side drivers circuitry of the IR2277S/IR2177S. VBS supply sit on top of the VS voltage and so it must be floating. The bootstrap method to generate VBS supply can be used with IR2277S/IR2177S current sensors. The bootstrap supply is formed by a diode and a capacitor connected as in Figure 20. IR2277S or IR2177S 1.6 Input filter gain setting Figure 20: bootstrap supply schematic 17 www.irf.com IR2277S/IR2177S(PbF) This method has the advantage of being simple and low cost but may force some limitations on dutycycle and on-time since they are limited by the requirement to refresh the charge in the bootstrap capacitor. Proper capacitor choice can reduce drastically these limitations. Bootstrap capacitor sizing Given the maximum admitted voltage drop for VBS, namely ∆VBS, the influencing factors contributing to VBS decrease are: − − − − Floating section quiescent current (IQBS); Floating section leakage current (ILK) Bootstrap diode leakage current (ILK_DIODE); Charge required by the internal level shifters (QLS); typical 20nC − Bootstrap capacitor leakage current (ILK_CAP); − High side on time (THON). ILK_CAP is only relevant when using an electrolytic capacitor and can be ignored if other types of capacitors are used. It is strongly recommend using at least one low ESR ceramic capacitor (paralleling electrolytic and low ESR ceramic may result in an efficient solution). Then we have: QTOT = QLS + ( I QBS + + I LK + I LK _ DIODE + I LK _ CAP ) ⋅ THON The minimum size of bootstrap capacitor is then: C BOOT min = QTOT ∆V BS Some important considerations a) Voltage ripple There are three different cases making the bootstrap circuit get conductive (see Figure 20) ILOAD < 0; the load current flows in the low side IGBT displaying relevant VCEon VBS = VCC − VF − VCEon In this case we have the lowest value for VBS. This represents the worst case for the bootstrap capacitor sizing. When the IGBT is turned off the Vs node is pushed up by the load current until the 18 high side freewheeling diode get forwarded biased ILOAD = 0; the IGBT is not loaded while being on and VCE can be neglected VBS = VCC − VF ILOAD > 0; the load current flows through the freewheeling diode V BS = VCC − VF + VFP In this case we have the highest value for VBS. Turning on the high side IGBT, ILOAD flows into it and VS is pulled up. b) Bootstrap Resistor A resistor (Rboot) is placed in series with the bootstrap diode (see Figure 20) to limit the current when the bootstrap capacitor is initially charged. We suggest not exceeding some Ohms (typically 5, maximum 10 Ohms) to avoid increasing the VBS time-constant. The minimum on time for charging the bootstrap capacitor or for refreshing its charge must be verified against this time-constant. c) Bootstrap Capacitor For high THON designs where an electrolytic tank capacitor is used, its ESR must be considered. This parasitic resistance develops a voltage divider with Rboot generating a voltage step on VBS at the first charge of bootstrap capacitor. The voltage step and the related speed (dVBS/dt) should be limited. As a general rule, ESR should meet the following constraint: ESR ⋅ VCC ≤ 3V ESR + RBOOT Parallel combination of small ceramic and large electrolytic capacitors is normally the best compromise, the first acting as fast charge tank for the gate charge only and limiting the dVBS/dt by reducing the equivalent resistance while the second keeps the VBS voltage drop inside the desired ∆VBS. d) Bootstrap Diode The diode must have a BV> 600V (or 1200V depending on application) and a fast recovery time (trr < 100 ns) to minimize the amount of charge fed back from the bootstrap capacitor to VCC supply. www.irf.com IR2277S/IR2177S(PbF) 3 PCB LAYOUT TIPS 3.1 Distance from H to L voltage The IR2277S/IR2177S package (wide body) maximizes the distance between floating (from DCto DC+) and low voltage pins (VSS). It is strongly recommended to place components tied to floating voltage in the respective high voltage portions of the device (VB, VS) side. 3.3 Antenna loops and inputs connection Current loops behave like antennas able to receive EM noise. In order to reduce EM coupling loops must be reduced as much as possible. Figure 21 shows the high side shunt loops. Moreover it is strongly suggested to use Kelvin connections for Vin+ and Vin- to shunt paths and starconnect VS to Vin- close to the shunt resistor as explained in Fig. 22. 3.2 Ground plane Ground plane must NOT be placed under or nearby the high voltage floating side to minimize noise coupling. VB VS VB V in V in + VS Vin- Antenna Loop Vin+ Figure 22: Recommended shunt connection Figure 21: antenna loops 3.4 Supply capacitors The supply capacitors must be placed as close as possible to the device pins (VCC and VSS for the ground tied supply, VB and VS for the floating supply) in order to minimize parasitic traces inductance/resistance 19 www.irf.com IR2277S/IR2177S(PbF) Case Outline WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 This part has been qualified for the Industrial Market Data and specifications subject to change without notice. 8/18/2005 20 www.irf.com