IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A 1M x 36 and 2M x 18 36Mb, FLOW THROUGH 'NO WAIT' STATE BUS SRAM JUNE 2008 FEATURES DESCRIPTION • 100 percent bus utilization The 36 Meg 'NLF/NVF' product family feature high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, 'no wait' state, device for networking and communications applications. They are organized as 1M words by 36 bits and 2M words by 18 bits, fabricated with ISSI's advanced CMOS technology. • No wait cycles between Read and Write • Internal self-timed write cycle • Individual Byte Write Control • Single Read/Write control pin • Clock controlled, registered address, data and control • Interleaved or linear burst sequence control using MODE input • Three chip enables for simple depth expansion and address pipelining • Power Down mode • Common data inputs and data outputs • CKE pin to enable clock and suspend operation • JEDEC 100-pin TQFP and 165-ball packages • Power supply: NVF: Vdd 2.5V (± 5%), Vddq 2.5V (± 5%) NLF: Vdd 3.3V (± 5%), Vddq 3.3V/2.5V (± 5%) • JTAG Boundary Scan for PBGA packages • Industrial temperature available Incorporating a 'no wait' state feature, wait cycles are eliminated when the bus switches from read to write, or write to read. This device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers are controlled by a positive-edge-triggered single clock input. Operations may be suspended and all synchronous inputs ignored when Clock Enable, CKE is HIGH. In this state the internal device will hold their previous values. All Read, Write and Deselect cycles are initiated by the ADV input. When the ADV is HIGH the internal burst counter is incremented. New external addresses can be loaded when ADV is LOW. Write cycles are internally self-timed and are initiated by the rising edge of the clock inputs and when WE is LOW. Separate byte enables allow individual bytes to be written. A burst mode pin (MODE) defines the order of the burst sequence.When tied HIGH, the interleaved burst sequence is selected. When tied LOW, the linear burst sequence is selected. • Lead-free available FAST ACCESS TIME Symbol tkq tkc Parameter Clock Access Time Cycle Time Frequency 6.5 6.5 7.5 133 7.5 7.5 8.5 117 Units ns ns MHz Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 1 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A BLOCK DIAGRAM x 36: A [0:19] or x 18: A [0:20] ADDRESS REGISTER A2-A19 or A2-A20 MODE A0-A1 CLK CONTROL LOGIC CKE BURST ADDRESS COUNTER 1Mx36; 2Mx18 MEMORY ARRAY A'0-A'1 DATA-IN REGISTER WRITE ADDRESS REGISTER CE CE2 CE2 ADV WE BWŸX } CONTROL REGISTER CONTROL LOGIC (X=a-d, or a,b) BUFFER OE ZZ 36 or 18 DQx/DQPx 2 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A Bottom View 165-Ball, 13 mm x 15mm BGA Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 3 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A Pin Configuration — 1M x 36, 165-Ball PBGA (Top View) 1 2 3 4 5 6 7 8 9 10 11 A NC A CE BWc BWb CE2 CKE ADV A A NC B NC A CE2 BWd BWa CLK WE OE A A NC C DQPc NC Vddq VSS VSS VSS VSS VSS Vddq NC DQPb D DQc DQc Vddq Vdd VSS VSS VSS Vdd Vddq DQb DQb E DQc DQc Vddq Vdd VSS VSS VSS Vdd Vddq DQb DQb F DQc DQc Vddq Vdd VSS VSS VSS Vdd Vddq DQb DQb G DQc DQc Vddq Vdd VSS VSS VSS Vdd Vddq DQb DQb H NC VDD NC Vdd VSS VSS VSS Vdd NC NC ZZ J DQd DQd Vddq Vdd VSS VSS VSS Vdd Vddq DQa DQa K DQd DQd Vddq Vdd VSS VSS VSS Vdd Vddq DQa DQa L DQd DQd Vddq Vdd VSS VSS VSS Vdd Vddq DQa DQa M DQd DQd Vddq Vdd VSS VSS VSS Vdd Vddq DQa DQa N DQPd NC Vddq VSS NC NC NC VSS Vddq NC DQPa P NC NC A A TDI A1* TDO A A A NC R MODE A A A TMS A0* TCK A A A A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV WE CLK CKE CE CE2 CE2 BWx (x=a-d) 4 Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load Synchronous Read/Write Control Input Synchronous Clock Clock Enable Synchronous Chip Select Synchronous Chip Select Synchronous Chip Select Synchronous Byte Write Inputs Symbol OE ZZ Pin Name Output Enable Power Sleep Mode MODE TCK, TDI TDO, TMS VDD NC DQx DQPx VDDQ Burst Sequence Selection JTAG Pins Vss 3.3V/2.5V Power Supply No Connect Data Inputs/Outputs Parity Data I/O Isolated output Power Supply 3.3V/2.5V Ground Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A 165-PIN PBGA PACKAGE CONFIGURATION 2M x 18 (TOP VIEW) 1 2 3 4 5 6 7 8 9 10 11 A NC A BWb NC CE2 CKE ADV A NC A NC NC VDDQ BWa Vss CLK Vss WE Vss VDDQ NC NC DQPa D NC DQb VDDQ VDD Vss Vss Vss OE Vss VDD A C NC Vss A A A B CE CE2 VDDQ NC DQa E NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa F NC DQb VDDQ VDD Vss Vss Vss VDD VDDQ NC DQa G NC DQb VDDQ Vss NC NC NC ZZ J DQb NC VDDQ VDD Vss Vss VDD VDD DQa VDD Vss Vss NC NC Vss Vss VDDQ H VDD VDD Vss Vss VDD VDDQ DQa NC K DQb NC VDDQ VDD Vss Vss Vss VDD VDDQ DQa L DQb NC VDDQ VDD Vss Vss VDD VDDQ DQa M DQb NC VDDQ VDD Vss Vss Vss NC NC Vss VDD VDDQ DQa NC N DQPb NC Vss NC TDO A A NC R MODE A A A TMS A1* A0* VDDQ A NC NC NC TDI NC NC Vss A NC P VDDQ A TCK A A A A Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired. PIN DESCRIPTIONS Symbol A A0, A1 ADV WE CLK CKE CE CE2 CE2 BWx (x=a,b) OE ZZ Pin Name Address Inputs Synchronous Burst Address Inputs Synchronous Burst Address Advance/ Load Synchronous Read/Write Control Input Synchronous Clock Clock Enable Synchronous Chip Select Synchronous Chip Select Synchronous Chip Select Synchronous Byte Write Inputs Output Enable Power Sleep Mode MODE TCK, TDI TDO, TMS VDD NC DQx DQPx VDDQ Vss Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 Burst Sequence Selection JTAG Pins 3.3V/2.5V Power Supply No Connect Data Inputs/Outputs Parity Data I/O Isolated output Power Supply 3.3V/2.5V Ground 5 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A PIN CONFIGURATION VDDQ VDDQ DQb DQb DQb Vss NC VDD ZZ DQb Vss VDD DQa DQb DQa DQb VDDQ VDDQ NC Vss DQa Vss DQb DQa DQb DQa DQa Vss DQPb NC VDDQ VDDQ DQa DQa DQPa NC NC NC Vss Vss A A A ADV A OE CKE CLK WE CE2 VDD Vss BWa NC BWb NC CE2 CE 1M x 36 A NC NC VDDQ Vss NC DQPa DQa DQa Vss VDDQ DQa DQa Vss NC VDD ZZ DQa DQa VDDQ Vss DQa DQa NC NC Vss VDDQ NC NC NC A A Vss Vss A DQb A DQb A DQb DQb A NC NC NC A A DQb DQb VDD Vss Vss Vss A A A ADV A OE CKE CLK WE CE2 VDD Vss BWa BWc BWb BWd CE2 CE A A VDDQ NC NC MODE DQd DQd DQPd VDDQ A1 A0 VDDQ NC A DQd DQd Vss DQb A DQd NC A Vss DQd DQb 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A VDDQ NC MODE DQd DQPb A A DQd A NC Vss A DQc Vss VDD A DQc A VDDQ NC A A Vss VDD DQc Vss DQc NC NC DQc DQc A1 A0 Vss A VDDQ A DQc A DQc 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 10 71 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 30 51 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 A DQPc A A 100-Pin TQFP 2M x 18 PIN DESCRIPTIONS A0, A1 A CLK ADV BWa-BWd WE CKE Vss NC 6 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Burst Address Advance Synchronous Byte Write Enable Write Enable Clock Enable Ground for Core Not Connected CE, CE2, CE2 OE DQa-DQd DQPa-DQPd MODE Vdd Vss Vddq ZZ Synchronous Chip Enable Output Enable Synchronous Data Input/Output Parity Data I/O Burst Sequence Selection +3.3V/2.5V Power Supply Ground for output Buffer Isolated Output Buffer Supply: +3.3V/2.5V Snooze Enable Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A STATE DIAGRAM READ READ READ BURST WRITE BEGIN READ DS DS READ WRITE DESELECT BURST BURST READ BEGIN WRITE BURST DS BURST DS DS WRITE READ BURST WRITE WRITE WRITE BURST SYNCHRONOUS TRUTH TABLE(1) Operation Not Selected Not Selected Not Selected Not Selected Continue Begin Burst Read Continue Burst Read NOP/Dummy Read Dummy Read Begin Burst Write Continue Burst Write NOP/Write Abort Write Abort Ignore Clock Notes: Address Used N/A N/A N/A N/A External Address Next Address External Address Next Address External Address Next Address N/A Next Address Current Address CE H X X X L X L X L X L X X CE2 X L X X H X H X H X H X X CE2 X X H X L X L X L X L X X ADV L L L H L H L H L H L H X WE X X X X H X H X L X L X X BWx X X X X X X X X L L H H X OE X X X X L L H H X X X X X CKE L L L L L L L L L L L L H CLK ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ ↑ 1. "X" means don't care. 2. The rising edge of clock is symbolized by ↑ 3. A continue deselect cycle can only be entered if a deselect cycle is executed first. 4. WE = L means Write operation in Write Truth Table. WE = H means Read operation in Write Truth Table. 5. Operation finally depends on status of asynchronous pins (ZZ and OE). Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 7 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A ASYNCHRONOUS TRUTH TABLE(1) Operation Sleep Mode Read Write Deselected Notes: ZZ H L L L L I/O STATUS High-Z DQ High-Z Din, High-Z High-Z OE X L H X X 1. X means "Don't Care". 2. For write cycles following read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur. 3. Sleep Mode means power Sleep Mode where stand-by current does not depend on cycle time. 4. Deselected means power Sleep Mode where stand-by current depends on cycle time. WRITE TRUTH TABLE (x18) Operation READ WRITE BYTE a WRITE BYTE b WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE H L L L L BWa X L H L H BWb X H L L H 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. WRITE TRUTH TABLE (x36) Operation READ WRITE BYTE a WRITE BYTE b WRITE BYTE c WRITE BYTE d WRITE ALL BYTEs WRITE ABORT/NOP Notes: WE H L L L L L L BWa X L H H H L H BWb X H L H H L H BWc X H H L H L H BWd X H H H L L H 1. X means "Don't Care". 2. All inputs in this table must beet setup and hold time around the rising edge of CLK. INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or NC) External Address A1 A0 00 01 10 11 8 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A LINEAR BURST ADDRESS TABLE (MODE = Vss) 0,0 A1', A0' = 1,1 0,1 1,0 ABSOLUTE MAXIMUM RATINGS(1) Symbol Tstg Pd Iout Vin, Vout Vin Parameter Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to Vss for I/O Pins Voltage Relative to Vss for for Address and Control Inputs Value –65 to +150 1.6 100 –0.5 to Vddq + 0.3 –0.3 to 4.6 Unit °C W mA V V Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 9 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A OPERATING RANGE (IS61NLFx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C Vdd 3.3V ± 5% 3.3V ± 5% Vddq 3.3V / 2.5V ± 5% 3.3V / 2.5V ± 5% Vdd 2.5V ± 5% 2.5V ± 5% Vddq 2.5V ± 5% 2.5V ± 5% OPERATING RANGE (IS61NVFx) Range Commercial Industrial Ambient Temperature 0°C to +70°C -40°C to +85°C DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Voh Output HIGH Voltage Vol Output LOW Voltage Vih Input HIGH Voltage Vil Input LOW Voltage Ili Input Leakage Current Ilo Output Leakage Current 3.3V Test Conditions Min. Ioh = –4.0 mA (3.3V) 2.4 Ioh = –1.0 mA (2.5V) Iol = 8.0 mA (3.3V) — Iol = 1.0 mA (2.5V) 2.0 –0.3 Vss ≤ Vin ≤ Vdd(1) –5 Vss ≤ Vout ≤ Vddq, OE = Vih –5 2.5V Max. — Min. 2.0 Max. — Unit V 0.4 — 0.4 V Vdd + 0.3 0.8 5 5 1.7 –0.3 –5 –5 Vdd + 0.3 0.7 5 5 V V µA µA POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Icc AC Operating Supply Current Isb Standby Current TTL Input Isbi Standby Current CMOS Input Test Conditions Temp. range Device Selected, Com. OE = Vih, ZZ ≤ Vil, Ind. All Inputs ≤ 0.2V or ≥ Vdd – 0.2V, typ.(2) Cycle Time ≥ tkc min. Device Deselected, Com. Vdd = Max., Ind. All Inputs ≤ Vil or ≥ Vih, ZZ ≤ Vil, f = Max. Device Deselected, Com. Vdd = Max., Ind. Vin ≤ Vss + 0.2V or ≥ Vdd – 0.2V f = 0 typ(2) 6.5 MAX x18 400 425 x36 400 425 7.5 MAX x18 375 400 x36 375 400 Unit mA 390 200 200 210 210 190 200 190 200 mA 100 105 100 105 100 105 mA 100 105 40 340 40 Note: 1. MODE pin has an internal pullup and should be tied to Vdd or Vss. It exhibits ±100 µA maximum leakage current when tied to ≤ Vss + 0.2V or ≥ Vdd – 0.2V. 2. Typical values are measured at Vcc = 3.3V, TA = 25oC and not 100% tested. 10 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A CAPACITANCE(1,2) Symbol Cin Cout Parameter Input Capacitance Input/Output Capacitance Conditions Vin = 0V Vout = 0V Max. 6 8 Unit pF pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V. 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V See Figures 1 and 2 3.3V I/O OUTPUT LOAD EQUIVALENT 317 Ω +3.3V Zo=50Ω OUTPUT OUTPUT 50Ω 5 pF Including jig and scope 351 Ω 1.5V Figure 1 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 Figure 2 11 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 2.5V 1.5 ns 1.25V See Figures 3 and 4 2.5V I/O OUTPUT LOAD EQUIVALENT 1,667 Ω +2.5V ZO = 50Ω OUTPUT OUTPUT 50Ω 5 pF Including jig and scope 1,538 Ω 1.25V Figure 3 12 Figure 4 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A READ/WRITE CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) Parameter Clock Frequency Cycle Time Clock High Time Clock Low Time Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Clock High to Output High-Z Output Enable to Output Valid Output Enable to Output Low-Z 6.5 Min. Max. — 133 7.5 — 2.2 — 2.2 — — 6.5 2.5 — 2.5 — — 3.8 — 3.2 0 — 7.5 Min. Max. — 117 8.5 — 2.5 — 2.5 — — 7.5 2.5 — 2.5 — — 4.0 — 3.4 0 — Unit MHz ns ns ns ns ns ns ns ns ns Output Disable to Output High-Z Address Setup Time Read/Write Setup Time Chip Enable Setup Time Clock Enable Setup Time Address Advance Setup Time Data Setup Time Address Hold Time Clock Enable Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time Data Hold Time ZZ High to Power Down ZZ Low to Power Down — 1.5 1.5 1.5 1.5 1.5 1.5 0.65 0.5 0.5 0.5 0.5 0.5 — — — 3.5 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 1.5 — 0.65 — 0.5 — 0.5 — 0.5 — 0.5 — 0.5 — — 2 — 2 ns ns ns ns ns ns ns ns ns ns ns ns ns cyc cyc Symbol fmax tkc tkh tkl tkq tkqx(2) tkqlz(2,3) tkqhz(2,3) toeq toelz(2,3) toehz(2,3) tas tws tces tse tadvs tds tah the twh tceh tadvh tdh tpds tpus Notes: 3.5 — — — — — — — — — — — — 2 2 1. Configuration signal MODE is static and must not change during normal operation. 2. Guaranteed but not 100% tested. This parameter is periodically sampled. 3. Tested with load in Figure 2. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 13 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A SLEEP MODE ELECTRICAL CHARACTERISTICS Symbol Isb2 tpds tpus tzzi trzzi Parameter Conditions Min. Max. Current during SLEEP MODE ZZ ≥ Vih 80 ZZ active to input ignored 2 ZZ inactive to input sampled 2 ZZ active to SLEEP current 2 ZZ inactive to exit SLEEP current 0 Unit mA cycle cycle cycle ns SLEEP MODE TIMING CLK tPDS ZZ setup cycle tPUS ZZ recovery cycle ZZ tZZI Isupply ISB2 tRZZI All Inputs (exceptZZ) DeselectorReadOnly DeselectorReadOnly Normal operation cycle Outputs (Q) High-Z Don'tCare 14 Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A READ CYCLE TIMING tKH tKL CLK tKC tADVS tADVH ADV tAS tAH Address A1 A3 A2 tWS tWH WRITE tSE tHE CKE tCES tCEH CE OE tOEQ tOEHZ Data Out Q1-1 tOEHZ tKQX Q2-1 tKQ Q2-2 tKQHZ Q2-3 NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 Q2-4 Q3-1 Q3-2 Q3-3 Q3-4 Don't Care Undefined 15 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A WRITE CYCLE TIMING tKH tKL CLK tKC ADV Address A1 A3 A2 WRITE tSE tHE CKE CE OE tDS Data In D1-1 D2-1 D2-2 D2-3 D2-4 D3-1 tDH D3-2 D3-3 D3-4 tOEHZ Data Out Q0-4 NOTES: WRITE = L means WE = L and BWx = L WE = L and BWX = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L 16 Don't Care Undefined Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A SINGLE READ/WRITE CYCLE TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 A6 A7 A8 A9 WRITE CE ADV OE tOEQ Data Out tOELZ Q1 Q3 Q4 Q6 Q7 tDS tDH Data In D2 D5 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 Don't Care Undefined 17 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A CKE OPERATION TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 A6 WRITE CE ADV OE tKQ Data Out tKQLZ tKQHZ Q1 Q3 Q4 tDS tDH Data In D2 NOTES: WRITE=LmeansWE=LandBWx=L CE=LmeansCE1=L,CE2=HandCE2=L CE=HmeansCE1=H,orCE1=LandCE2=H,orCE1=LandCE2=L 18 D5 Don'tCare Undefined Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A CE OPERATION TIMING tKH tKL CLK tSE tHE tKC CKE Address A1 A2 A3 A4 A5 WRITE CE ADV OE tOEQ Data Out tOELZ tKQHZ Q1 tKQ tKQLZ Q2 Q4 tDS tDH Data In D3 NOTES: WRITE = L means WE = L and BWx = L CE = L means CE1 = L, CE2 = H and CE2 = L CE = H means CE1 = H, or CE1 = L and CE2 = H, or CE1 = L and CE2 = L Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 D5 Don't Care Undefined 19 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A ORDERING INFORMATION (Vdd = 3.3V/Vddq = 2.5V- 3.3V) Commercial Range: 0°C to +70°C Access Time 6.5 7.5 6.5 7.5 Order Part Number 1Mx36 IS61NLF102436A-6.5TQ IS61NLF102436A-6.5B3 IS61NLF102436A-7.5TQ IS61NLF102436A-7.5B3 2Mx18 IS61NLF204818A-6.5TQ IS61NLF204818A-6.5B3 IS61NLF204818A-7.5TQ IS61NLF204818A-7.5B3 Package 100 TQFP 165 PBGA 100 TQFP 165 PBGA 100 TQFP 165 PBGA 100 TQFP 165 PBGA Industrial Range: -40°C to +85°C Access Time Order Part Number 1Mx36 6.5 IS61NLF102436A-6.5TQI IS61NLF102436A-6.5B3I 7.5 IS61NLF102436A-7.5TQI IS61NLF102436A-7.5TQLI IS61NLF102436A-7.5B3I 2Mx18 6.5 IS61NLF204818A-6.5TQI IS61NLF204818A-6.5B3I 7.5 IS61NLF204818A-7.5TQI IS61NLF204818A-7.5B3I 20 Package 100 TQFP 165 PBGA 100 TQFP 100 TQFP, Lead-free 165 PBGA 100 TQFP 165 PBGA 100 TQFP 165 PBGA Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 IS61NLF102436A/IS61NVF102436A IS61NLF204818A/IS61NVF204818A ORDERING INFORMATION (Vdd = 2.5V /Vddq = 2.5V) Commercial Range: 0°C to +70°C Access Time 6.5 7.5 6.5 7.5 Order Part Number 1Mx36 IS61NVF102436A-6.5TQ IS61NVF102436A-6.5B3 IS61NVF102436A-7.5TQ IS61NVF102436A-7.5B3 2Mx18 IS61NVF204818A-6.5TQ IS61NVF204818A-6.5B3 IS61NVF204818A-7.5TQ IS61NVF204818A-7.5B3 Package 100 TQFP 165 PBGA 100 TQFP 165 PBGA 100 TQFP 165 PBGA 100 TQFP 165 PBGA Industrial Range: -40°C to +85°C Access Time 6.5 7.5 6.5 7.5 Order Part Number 1Mx36 IS61NVF102436A-6.5TQI IS61NVF102436A-6.5B3I IS61NVF102436A-7.5TQI IS61NVF102436A-7.5B3I 2Mx18 IS61NVF204818A-6.5TQI IS61NVF204818A-6.5B3I IS61NVF204818A-7.5TQI IS61NVF204818A-7.5B3I Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. B 06/09/08 Package 100 TQFP 165 PBGA 100 TQFP 165 PBGA 100 TQFP 165 PBGA 100 TQFP 165 PBGA 21 PACKAGING INFORMATION Ball Grid Array Package Code: B (165-pin) BOTTOM VIEW TOP VIEW A1 CORNER 1 2 3 4 A1 CORNER φ b (165X) 5 6 7 8 9 10 11 10 11 9 8 7 6 5 4 3 2 1 A A B B C C D D E E e F F G G D D1 H H J J K K L L M M N N P P R R E1 E A2 e A A1 BGA - 13mm x 15mm MILLIMETERS Sym. Min. N0. Leads Nom. Max. Notes: 1. Controlling dimensions are in millimeters. INCHES Min. 165 Nom. Max. 165 A — — 1.20 — A1 0.25 0.33 0.40 0.010 — 0.047 0.013 0.016 A2 — 0.79 — — 0.031 — D 14.90 15.00 15.10 0.587 0.591 0.594 D1 13.90 14.00 14.10 0.547 0.551 0.555 E 12.90 13.00 13.10 0.508 0.512 0.516 E1 9.90 10.00 10.10 0.390 0.394 0.398 e — 1.00 — — 0.039 — b 0.40 0.45 0.50 0.016 0.018 0.020 Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774 Rev. A 06/11/03 PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code: TQ D D1 E E1 N L1 L C 1 e SEATING PLANE A2 A b A1 Millimeters Min Max Thin Quad Flat Pack (TQ) Inches Millimeters Min Max Min Max Symbol Ref. Std. No. Leads (N) 100 A — 1.60 — 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.45 0.053 0.057 b 0.22 0.38 0.009 0.015 D 21.90 22.10 0.862 0.870 D1 19.90 20.10 0.783 0.791 E 15.90 16.10 0.626 0.634 E1 13.90 14.10 0.547 0.555 e 0.65 BSC 0.026 BSC L 0.45 0.75 0.018 0.030 L1 1.00 REF. 0.039 REF. o o C 0 7 0o 7o 128 — 1.60 0.05 0.15 1.35 1.45 0.17 0.27 21.80 22.20 19.90 20.10 15.80 16.20 13.90 14.10 0.50 BSC 0.45 0.75 1.00 REF. 0o 7o Integrated Silicon Solution, Inc. — 1-800-379-4774 PK13197LQ Rev. D 05/08/03 Inches Min Max — 0.063 0.002 0.006 0.053 0.057 0.007 0.011 0.858 0.874 0.783 0.791 0.622 0.638 0.547 0.555 0.020 BSC 0.018 0.030 0.039 REF. 0o 7o Notes: 1. All dimensioning and tolerancing conforms to ANSI Y14.5M-1982. 2. Dimensions D1 and E1 do not include mold protrusions. Allowable protrusion is 0.25 mm per side. D1 and E1 do include mold mismatch and are determined at datum plane -H-. 3. Controlling dimension: millimeters.