IW4049UB HEX BUFFER/CONVERTER High-Voltage Silicon-Gate CMOS The IW4049UB is inverting hex buffers and feature logic-level conversion using only one supply (voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logic-level conversions. These devices are intended for use as CMOS to DTL/TTL converters. • Operating Voltage Range: 3.0 to 18 V • Maximum input current of 1 µA at 18 V over full packagetemperature range; 100 nA at 18 V and 25°C • Noise margin (over full package temperature range): 0.5 V min @ 5.0 V supply 1.0 V min @ 10.0 V supply 1.0 V min @ 15.0 V supply • High-to-low level conversion ORDERING INFORMATION IW4049UBN Plastic IW4049UBD SOIC TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN ASSIGNMENT NC = NO CONNECTION FUNCTION TABLE Inputs Output A Y H L L H PINS 13, 16 = NO CONNECTION PIN 1 =VCC PIN 8 = GND 1 IW4049UB MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +20 V ** VIN DC Input Voltage (Referenced to GND) VCC to +18 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin mA ±10 PD Power Dissipation in Still Air, Plastic DIP+ 750 mW SOIC Package+ 500 PD r Dissipation per Output Transistor 100 mW Tstg Storage Temperature -65 to +150 °C 260 TL Lead Temperature, 1 mm from Case for 10 °C Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C SOIC Package: : - 7 mW/°C from 65° to 125°C ** The IW4049UB has high-to-low level voltage conversion capability but not low-to-high level; therefore it is recommended that VIN ≥ VCC RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min VCC DC Supply Voltage (Referenced to GND) 3.0 VIN DC Input Voltage (Referenced to GND) VCC** VOUT DC Output Voltage (Referenced to GND) 0 TA Operating Temperature, All Package Types -55 ** The IW4049UB has high-to-low level voltage conversion capability but therefore it is recommended that VIN ≥ VCC Max Unit 18 V 18 V VCC V +125 °C not low-to-high level; This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 IW4049UB DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) Guaranteed Limit VCC Symbol Parameter Test Conditions V ≥-55°C 25°C ≤125 Unit °C V 4 4 4 VOUT= 0.5V 5.0 VIH Minimum High8 8 8 10 Level Input VOUT= 1.0 V 12.5 12.5 12.5 15 Voltage VOUT= 1.5V V 1 1 1 VOUT= VCC - 0.5V 5.0 VIL Maximum Low 2 2 2 10 Level Input VOUT= VCC - 1.0 V 2.5 2.5 2.5 15 Voltage VOUT= VCC - 1.5V V 4.95 4.95 VIN=GND 4.95 VOH Minimum High5.0 9.95 9.95 9.95 Level Output 10 Voltage 15 14.95 14.95 14.95 V 0.05 0.05 VIN= VCC 0.05 VOL Maximum Low5.0 0.05 0.05 0.05 Level Output 10 0.05 0.05 0.05 Voltage 15 IIN Maximum Input VIN= GND or VCC 18 ±0.1 ±0.1 ±1.0 µA Leakage Current 30 1 VIN= GND or VCC 1 ICC Maximum 5.0 µA 60 2 2 Quiescent Supply 10 120 4 4 Current 15 600 20 20 (per Package) 20 mA VIN= GND or VCC IOL Minimum Output 1.8 2.6 3.3 4.5 Low (Sink) UOL=0.4 V 2.4 3.2 4 5 Current UOL=0.4 V 5.6 8 10 10 UOL=0.5 V 18 24 26 15 UOL=1.5 V mA VIN= GND or VCC IOH Minimum Output -2.1 -1.55 -2.6 5.0 High (Source) UOH=2.5 V 5.0 -0.81 -0.65 -0.48 Current UOH=4.6 V -1.65 -1.18 -2.0 10 UOH=9.5 V -3.1 -4.3 -5.2 15 UOH=13.5 V 3 IW4049UB AC ELECTRICAL CHARACTERISTICS(CL=50pF, RL=200kΩ, Input tr=tf=20 ns) Guaranteed Limit VIN VCC Symbol Parameter V V ≥-55°C 25°C ≤125°C 240 120 120 5 tPLH Maximum Propagation Delay, 5 130 65 65 Input A to Output Y (Figure 1) 10 10 180 90 90 5 10 100 50 50 15 15 180 90 90 5 15 130 65 65 5 tPHL Maximum Propagation Delay, 5 80 40 40 Input A to Output Y (Figure 1) 10 10 60 30 30 5 10 60 30 30 15 15 40 20 20 5 15 320 160 160 5 tTLH Maximum Output Transition Time, 5 160 80 80 Any Output (Figure 1) 10 10 120 60 60 15 15 120 60 60 5 tTHL Maximum Output Transition Time, 5 80 40 40 Any Output (Figure 1) 10 10 60 30 30 15 15 CIN Maximum Input Capacitance 22.5 Figure 1. Switching Waveforms EXPANDED LOGIC DIAGRAM (1/6 of the Device) 4 Unit ns ns ns ns pF