STMICROELECTRONICS L6926D

L6926D
HIGH EFFICIENCY MONOLITHIC SYNCHRONOUS
STEP DOWN REGULATOR
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2V TO 5.5V BATTERY INPUT RANGE
HIGH EFFICIENCY: UP TO 95%
INTERNAL SYNCHRONOUS SWITCH
NO EXTERNAL SCHOTTKY REQUIRED
EXTREMELY LOW QUIESCENT CURRENT
1µA MAX SHUTDOWN SUPPLY CURRENT
800mA MAX OUTPUT CURRENT
ADJUSTABLE OUTPUT VOLTAGE FROM 0.6V
LOW DROP-OUT OPERATION: UP TO100%
DUTY CYCLE
SELECTABLE LOW NOISE/LOW
CONSUMPTION MODE AT LIGHT LOAD
POWER GOOD SIGNAL
±1% OUTPUT VOLTAGE ACCURACY
CURRENT-MODE CONTROL
600kHz SWITCHING FREQUENCY
EXTERNALLY SYNCHRONIZABLE FROM
500kHz TO 1.4MHz
OVP
SHORT CIRCUIT PROTECTION
MSOP8
ORDERING NUMBERS: L6926D
L6926D013TR (Tape & Reel)
■
GPS
DESCRIPTION
The device is dc-dc monolithic regulator specifically
designed to provide extremely high efficiency.
L6926D supply voltage can be as low as 2V allowing
its use in single Li-ion cell supplied applications. Output voltage can be selected by an external divider
down to 0.6V. Duty Cycle can saturate to 100% allowing low drop-out operation. The device is based
on a 600kHz fixed-frequency, current mode-architecture. Low Consumption Mode operation can be selected at light load conditions, allowing switching
losses to be reduced. L6926D is externally synchronizable with a clock which makes it useful in noisesensitive applications. Other features like Powergood, Overvoltage protection, Shortcircuit protection
and Thermal Shutdown (150°C) are also present.
APPLICATIONS
■ BATTERY-POWERED EQUIPMENTS
■ PORTABLE INSTRUMENTS
■ CELLULAR PHONES
■ PDAs AND HAND HELD TERMINALS
■ DSC
APPLICATION TEST CIRCUIT
L 6.8µH
VIN=2V to 5.5V
C1
10µF
6.3V
SYNC
VCC
RUN
5
7
6
May 2003
R2
200K
C4
10µF
6.3V
PGOOD
2
D01IN1305
R3
500K
VOUT=1.8V
8
1
COMP
LX
4
C2
220pF
3
VFB
GND
R1
100K
1/8
L6926D
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
V6
Input voltage
Value
Unit
-0.3 to 6
V
V5
Output switching voltage
-1 to VCC
V
V1
Shutdown
-0.3 to VCC
V
V3
Feedback voltage
-0.3 to VCC
V
V2
Analog input voltage
-0.3 to VCC
V
Ptot
Power dissipation at Tamb=70°C
0.45
W
Junction operating temperature range
-40 to 150
°C
Storage temperature range
-65 to 150
°C
±1000
V
±2000
V
Tj
Tstg
LX Pin
Other pins
Maximum Withstanding Voltage Range Test Condition: CDFAEC-Q100-002- “Human Body Model” Acceptance Criteria:
“Normal Performance’
PIN CONNECTION
RUN
1
8
PGOOD
COMP
2
7
SYNC
VFB
3
6
VCC
GND
4
5
LX
D01IN1239AMOD
THERMAL DATA
Symbol
Rth j-amb
Parameter
Thermal Resistance Junction to Ambient
Value
Unit
180
°C/W
PIN FUNCTIONS
2/8
N
Name
1
RUN
Description
2
COMP
3
VFB
Error amplifier inverting input. The output voltage can be adjusted from 0.6V up to the input
voltage by connecting this pin to an external resistor divider.
4
GND
Ground.
5
LX
6
VCC
7
SYNC
8
PGOOD
Shutdown input. When connected to a low level (lower than 0.4V) the device stops working.
When high (higher than 1.3V) the device is enabled.
Error amplifier output. A compensation network has to be connected to this pin. Usually a
220pF capacitor is enough to guarantee the loop stability.
Switch output node. This pin is internally connected to the drain of the internal switches.
Input voltage. The start up input voltage is 2.2V (typ) while the operating input voltage range is
from 2V to 5.5V. An internal UVLO circuit realizes a 100mV (typ.) hysteresis.
Operating mode selector input. When high (higher than 1.3V) the Low Consumption Mode is
selected. When low (lower than 0.5V) the Low Noise Mode is selected. If connected with an
appropriate external synchronization signal (from 500KHz up to 1.4MHz) the internal
synchronization circuit is activated and the device works at the same switching frequency.
Power good comparator output. It is an open drain output. A pull-up resistor should be
connected between PGOOD and VOUT (or VCC depending on the requirements). The pin is
forced low when the output voltage is lower than 90% of the regulated output voltage and goes
high when the output voltage is greater than 90% of the regulated output voltage. If not used the
pin can be left floating.
L6926D
ELECTRICAL CHARACTERISTICS (Tj = 25°C, VCC = 3.6V unless otherwise specified)
Symbol
Vcc
Parameter
Operating input voltage
Vcc ON
Turn On threshold
Vcc OFF
Turn Off threshold
Vcc hys
Hysteresis
Test Condition
After Turn on
Min
Typ
2
Max
Unit
5.5
V
2.2
V
2
V
100
mV
Rp
High side Ron
Vcc = 3.6V, Ilx =100mA
240
mΩ
Rn
Low side Ron
Vcc = 3.6V, Ilx =100mA
215
mΩ
Ilim
Peak current limit
Vcc = 3.6V
1.2
A
Valley current limit
Vcc = 3.6V
1.4
A
Vout
Output voltage range
fosc
Oscillator frequency
fsync
Sync mode clock (*)
Vfb
Vcc
V
1400
KHz
600
500
KHz
DC CHARACTERISTICS
Quiescent current (low noise
mode)
Vsync = 0V, no load, VFB >
0.6V
230
µA
Quiescent current (low
cunsumption mode)
Vsync = Vcc, no load, VFB
> 0.6V
25
µA
Ish
Shutdown current
RUN to GND, Vcc = 5.5V
0.2
µA
Ilx
LX leakage current (*)
RUN to GND, VLX = 5.5V,
Vcc = 5.5V
1
µA
RUN to GND, VLX = 0V,
Vcc = 5.5V
1
µA
Iq
ERROR AMPLIFIER CHARACTERISTICS
Vfb
Voltage feedback
Ifb
Feedback input current (*)
0.593
VFB = 0.6V
0.6
0.607
25
V
nA
RUN
Vrun_H
RUN threshold high
Vrun_L
RUN threshold low
Irun
1.3
0.4
RUN input current (*)
V
V
25
nA
SYNC/MODE FUNCTION
Vsync_H
Sync mode threshold high
Vsync_L
Sync mode threshold low
1.3
0.5
V
V
PGOOD SECTION
VPGOOD
Power Good Threshold
VOUT = Vfb
90
%Vout
∆VPGOOD
Power Good Hysteresis
VOUT = Vfb
4
%Vout
VPgood(low)
Power Good Low Voltage
Run to GND
ILK-PGOOD
Power Good Leakage Current
(*)
VPGOOD = 3.6V
50
nA
VOUT = Vfb
10
%Vout
0.4
V
PROTECTIONS
HOVP
Hard overvoltage threshold
(*) Guaranteed by design
3/8
L6926D
OPERATION DESCRIPTION
The main loop uses slope compensated PWM current mode architecture. Each cycle the high side MOSFET
is turned on, triggered by the oscillator, so that the current flowing through it (the same as the inductor current)
increases. When this current reaches the threshold (set by the output of the error amplifier E/A), the peak current
limit comparator PEAK_CL turns off the high side MOSFET and turns on the low side one until the next clock
cycle begins or the current flowing through it goes down to zero (ZERO CROSSING comparator). The peak inductor current required to trigger PEAK_CL depends on the slope compensation signal and on the output of the
error amplifier.
In particular, the error amplifier output depends on the VFB pin voltage. When the output current increases, the
output capacitor is discharged and so the VFB pin decreases. This produces increase of the error amplifier output, so allowing a higher value for the peak inductor current. For the same reason, when due to a load transient
the output current decreases, the error amplifier output goes low, so reducing the peak inductor current to meet
the new load requirements.
The slope compensation signal allows the loop stability also in high duty cycle conditions (see related section)
Figure 1. Device Block Diagram
RUN
SYNC
VCC
OSCILLATOR
COM P
GND
LOW
NOISE/
CONSUM PTION
SLOP E
GND
LOOP
CONTROL
E/A
FB
POWER
PMOS
SENSE
PMOS
PEAK
CL
VREF
LX
DRIVER
0.6V
OVP
P GOOD
VREF
0.9V
ZERO
CROSSING
Vcc
SENSE
NMOS
Vcc
POWER
NMOS
GND
PGOOD
VALLEY
CL
GND
Modes of Operation
Depending on the SYNC pin value the device can operate in low consumption or low noise mode. If the SYNC
pin is high (higher than 1.3V) the low consumption mode is selected while the low noise mode is selected if the
SYNC pin is low (lower than 0.5V).
Low Consumption Mode
In this mode of operation, at light load, the device operates discontinuously based on the COMP pin voltage, in
order to keep the efficiency very high also in these conditions. While the device is not switching the load discharges the output capacitor and the output voltage goes down. When the feedback voltage goes lower than
the internal reference, the COMP pin voltage increases and when an internal threshold is reached, the device
starts to switch. In these conditions the peak current limit is set approximately in the range of 200mA-400mA,
depending on the slope compensation (see related section).
Once the device starts to switch the output capacitor is recharged. The feedback pin increases and, when it
reaches a value slightly higher than the reference voltage, the output of the error amplifier goes down until a
clamp is activated. At this point, the device stops to switch. In this phase, most of the internal circuitries are off,
so reducing the device consumption down to a typical value of 25µA.
4/8
L6926D
Low Noise Mode
If for noise reasons, the very low frequencies of the low consumption mode are undesirable, the low noise mode
can be selected. In low noise mode, the efficiency is a little bit lower compared with the low consumption mode
in very light load conditions but for medium-high load currents the efficiency values are very similar.
Basically, the device switches with its internal free running frequency of 600KHz. Obviously, in very light load
conditions, the device could skip some cycles in order to keep the output voltage in regulation.
Synchronization
The device can also be synchronized with an external signal from 500KHz up to 1.4MHz.
In this case the low noise mode is automatically selected. The device will eventually skip some cycles in very
light load conditions.
The internal synchronization circuit is inhibited in shortcircuit and overvoltage conditions in order to keep the
protections effective (see relative sections).
Short Circuit Protection
During the device operation, the inductor current increases during the high side turn on phase and decrease
during the high side turn off phase based on the following equations:
( VIN – V OUT )
∆ ION = ----------------------------------- ⋅ TON
L
( V O UT )
∆I O F F = ------------------⋅ T O FF
L
In strong overcurrent or shortcircuit conditions the VOUT can be very close to zero. In this case ∆ION increases
and ∆IOFF decreases. When the inductor peak current reaches the current limit, the high side mosfet turns off
and so the TON is reduced down to the minimum value (250ns typ.) in order to reduce as much as possible ∆ION.
Anyway, if VOUT is low enough it can be that the inductor peak current further increases because during the
TOFF the current decays very slowly.
Due to this reason a second protection that fixes the maximum inductor valley current has been introduced. This
protection doesn't allow the high side MOSFET to turn on if the current flowing through the inductor is higher
that a specified threshold (valley current limit). Basically the TOFF is increased as much as required to bring the
inductor current down to this threshold.
So, the maximum peak current in worst case conditions will be:
VIN
I P EAK = IVAL LEY + --------- ⋅ T ON_MIN
L
Where IPEAK is the valley current limit (1.4A typ.) and TON_MIN is the minimum TON of the high side MOSFET.
Slope Compensation
In current mode architectures, when the duty cycle of the application is higher than approximately 50%, a pulseby-pulse instability (the so called sub harmonic oscillation) can occur.
To allow loop stability also in these conditions a slope compensation is present. This is realized by reducing the
current flowing through the inductor necessary to trigger the COMP comparator (with a fixed value for the COMP
pin voltage).
With a given duty cycle higher than 50%, the stability problem is particularly present with an higher input voltage
(due to the increased current ripple across the inductor), so the slope compensation effect increases as the input
voltage increases.
5/8
L6926D
From an application point of view, the final effect is that the peak current limit depends both on the duty cycle (if
higher than approximately 40%) and on the input voltage.
Loop Stability
Since the device is realized with a current mode architecture, the loop stability is usually not a big issue. For
most of the application a 220pF connected between the COMP pin and ground is enough to guarantee the stability. In case very low ESR capacitors are used for the output filter, such as multilayer ceramic capacitors, the
zero introduced by the capacitor itself can shift at very high frequency and the transient loop response could be
affected. Adding a series resistor to the 220pF capacitor can solve this problem.
The right value for the resistor (in the range of 50K) can be determined by checking the load transient response
of the device. Basically, the output voltage has to be checked at the scope after the load steps required by the
application. In case of stability problems, the output voltage could oscillates before to reach the regulated value
after a load step.
ADDITIONAL FEATURES AND PROTECTIONS
DROPOUT Operation
The Li-Ion battery voltage ranges from approximately 3V and 4.1V-4.2V (depending on the anode material). In
case the regulated output voltage is from 2.5V and 3.3V, it can be that, close to the end of the battery life, the
battery voltage goes down to the regulated one. In this case the device stops to switch, working at 100% of duty
cycle, so minimizing the dropout voltage and the device losses.
PGOOD (Power Good Output)
A power good output signal is available. The VFB pin is internally connected to a comparator with a threshold
set at 90% of the of reference voltage (0.6V). Since the output voltage is connected to the VFB pin by a resistor
divider, when the output voltage goes lower than the regulated value, the VFB pin voltage goes lower than 90%
of the internal reference value. The internal comparator is triggered and the PGOOD pin is pulled down.
The pin is an open drain output and so, a pull up resistor should be connected to him.
If the feature is not required, the pin can be left floating.
ADJUSTABLE OUTPUT VOLTAGE
The output voltage can be adjusted by an external resistor divider from a minimum value of 0.6V up to the input
voltage. The output voltage value is given by:
R
VOUT = 0.6 ⋅  1 + ------2-
R1
OVP (Overvoltage Protection)
The device has an internal overvoltage protection circuit to protect the load.
If the voltage at the feedback pin goes higher than an internal threshold set 10% (typ) higher than the reference
voltage, the low side power mosfet is turned on until the feedback voltage goes lower than the reference one.
During the overvoltage circuit intervention, the zero crossing comparator is disabled so that the device is also
able to sink current.
THERMAL SHUTDOWN
The device has also a thermal shutdown protection activated when the junction temperature reaches 150 C. In
this case both the high side MOSFET and the low side one are turned off. Once the junction temperature goes
back lower than 95 C, the device restarts the normal operation.
6/8
L6926D
mm
inch
DIM.
MIN.
TYP.
A
MAX.
MIN.
TYP.
1.10
A1
0.050
A2
0.750
b
MAX.
0.043
0.150
0.002
0.950
0.03
0.250
0.400
0.010
0.016
c
0.130
0.230
0.005
0.009
D (1)
2.900
3.000
3.100
0.114
0.118
0.122
E
4.650
4.900
5.150
0.183
0.193
0.20
E1 (1)
2.900
3.000
3.100
0.114
0.118
0.122
e
L
L1
k
aaa
Note:
0.850
0.650
0.400
0.550
OUTLINE AND
MECHANICAL DATA
0.006
0.033
0.037
0.026
0.700
0.016
0.950
0.022
0.028
0.037
0˚ (min.) 6˚ (max.)
0.100
0.004
1. D and F does not include mold flash or protrusions.
Mold flash or potrusions shall not exceed 0.15mm
(.006inch) per side.
MSOP8
(Body 3mm)
7/8
L6926D
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of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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