Ordering number : ENN*6700 CMOS IC LC866548/40/32/28/24A 8-Bit Single Chip Microcontroller Preliminary Overview - CPU : Operable at a minimum bus cycle time of 0.5µs (microsecond) - On-chip ROM maximum capacity : 48K bytes - On-chip RAM capacity : 1152 bytes (LC866548A/40A/32A) : 896 bytes (LC866528A/24A) - VFD automatic display controller/driver - 16-bit timer/counter (or two 8-bit timers) - 16-bit timer/ PWM (or two 8-bit timers) - 8-channels × 8 bit AD Converter - Two 8-bit synchronous serial-interface circuits (1-channel × 16 bit, 1-channel × 8 bit) - 14-source 10-vectored interrupt system All of the above functions are fabricated on a single chip. Features (1) Read Only Memory (ROM) Ver.1.05 71896 : LC866548A : LC866540A : LC866532A : LC866528A : LC866524A 49152 × 8 bits 40960 × 8 bits 32768 × 8 bits 28672 × 8 bits 24576 × 8 bits 91400 RM (IM) SK No.6700-1/21 LC866548/40/32/28/24A (2) Random Access Memory (RAM) : LC866548A/40A/32A LC866528A/24A 1152 × 8 bits 896 × 8 bits (3) Bus Cycle Time / Instruction Cycle Time The bus cycle time indicates the speed to read ROM. Bus cycle time Cycle time Clock divider System clock oscillation Oscillation Frequency Voltage 0.5µs 2µs 7.5µs 183µs 1µs 4µs 15µs 366µs 1/1 1/2 1/2 1/2 Ceramic resonator oscillation Ceramic resonator oscillation RC resonator oscillation Crystal oscillation 6MHz 3MHz 800MHz 32.768kHZ 4.5 - 6.0V 4.5 - 6.0V 4.5 - 6.0V 4.5 - 6.0V Note : External resisters (Rf, Rd) are required when X’tal oscillation is used. (4) Ports - Input/output ports : 3 ports (16 terminals : port 1, 7, 8) Input/output port programmable in a bit - 15V withstand Input/output ports : 2 ports (16 terminals) Input/output port programmable nibble unit : 1 port (8 terminals : port 0) (When the N-channel open drain output is selected, the data in a bit can be inputted.) Input/output port programmable in a bit : 1 port (8 terminals : port 3) - Input port : 2 ports (6 terminals : port 7, 8) - VFD output port : 52 terminals Large current output for digit : 16 terminals Pull-down resistor option available - Other function Input/output port : 2 ports (12 terminals : port F, G) Input port : 3 ports (24 terminals : port C, D, E) (5) VFD automatic display controller - Segment/digit output pattern programmable Any segment/digit combination available VFD parallel-drive available - 16-step dimmer function available (6) AD converter - 8-channels × 8-bit AD converter (7) Serial interface - 1-channel × 16-bit serial interface circuits - 1-channel × 8-bit serial interface circuits - LSB first/MSB first function available - Internal 8-bit baud-rate generator in common with two serial interface circuits - SIO automatic transmission available (2-32 byte data can be transmitted with program automatically and continuously.) No.6700-2/21 LC866548/40/32/28/24A (8) Timers - Timer 0 : 16-bit timer/counter with 2-bit prescaler + 8-bit programmable prescaler Mode 0 : Two 8-bit timers with programmable prescaler Mode 1 : 8-bit timer with a programmable prescaler + 8-bit counter Mode 2 : 16-bit timer with a programmable prescaler Mode 3 : 16-bit counter The resolution of Timer is tCYC. (tCYC : cycle time) - Timer 1 : 16-bit timer/PWM with Mode 0 : Two 8-bit timers Mode 1 : 8-bit timer + 8-bit PWM Mode 2 : 16-bit timer Mode 3 : Variable-bit PWM (9-16 bits) In Mode 0 and Mode 1, the resolution of Timer and PWM is tCYC. In Mode 2 and Mode 3, the resolution of Timer and PWM selectable : tCYC or 1/2tCYC by program - Base timer Every 500ms overflow system for a clock application (using 32.768kHz crystal oscillation for Base timer clock) Every 976µs, 3.9ms, 15.6ms, 62.5ms overflow system (using 32.768kHz crystal oscillation for Base timer clock) The Base timer clock selectable ; 32.768kHz crystal oscillation, System clock, and programmable prescaler output of Timer 0 (9) Buzzer output - The Buzzer sound frequency selectable ; 4kHz, 2kHz (using 32.768kHz crystal oscillation for Base timer clock) (10) Remote control receiver circuit (connected to the P73/INT3/T0IN terminal) - Noise rejection function (the time constant of noise rejection filter : 1tCYC/16tCYC/64tCYC) (tCYC : instruction cycle time) - Polarity switching (11) Watchdog timer - The watchdog timer is taken on RC outside - Watchdog timer operation selectable : interrupt system, system reset (12) Interrupt system - 14-source 10-vectored interrupts : 1. External Interrupt INT0 (include watchdog timer) 2. External Interrupt INT1 3. External Interrupt INT2, Timer/counter T0L (Lower 8 bits) 4. External Interrupt INT3, base timer 5. Timer/counter T0H (Upper 8 bits) 6. Timer T1H / T1L 7. Serial interface SIO0 8. Serial interface SIO1 9. AD converter 10. VFD automatic display controller, Port 0 - Built-in Interrupt priority control register Microcontroller allows 3 levels of interrupt ; low level, high level, and highest level of multiplex interrupt. It can specify a low level or a high level interrupt priority from INT2/T0L through port 0 (i. e. the above interrupt number from three through ten). It can also specify a low level or the highest level interrupt priority to INT0 and INT1. (13) Subroutine stack levels - 128 levels (Max.) : Stack area included in RAM area No.6700-3/21 LC866548/40/32/28/24A (14) Multiplication and division - 16 bit × 8 bit (7 instruction cycle times) - 16 bit ÷ 8 bit (7 instruction cycle times) (15) Three oscillation circuits - On-chip RC oscillation circuit used for the system clock - On-chip CF oscillation circuit used for the system clock - On-chip Crystal oscillation circuit used for the system clock and for time-base clock Note : External resisters (Rf, Rd) are required (16) Standby function - HALT mode function The HALT mode is used to reduce the power dissipation. In this operation mode, the program execution is stopped. This operation mode can be released by the interrupt request signals or the initial system reset request signal. - HOLD mode function The HOLD mode is used to stop all the oscillations ; RC (internal), CF and Crystal oscillations. This mode can be released by the following operations. • Reset terminal ( RES ) set to low level. • Input a assigned level to P70/INT0/T0IN or P71/INT1/T0IN terminal. • Input a Port0 interrupt condition. (17) Factory shipment QFP100E delivery form (18) Development Tools - Evaluation chip - EPROM version - One time version - Emulator : LC866094 : LC86E6548 : LC86P6548 : EVA86000 + ECB866500 (Evaluation chip board) + POD866500 (Pod) • Notes for use Follow the under table. Frequency range of the system clock 15kHz to 3MHz 30kHz to 6MHz Internal RC oscillation Voltage range Clock Divider Note 4.5V to 6.0V 1/1 1/1, 1/2 1/1, 1/2 Can not use 1/2 divider No.6700-4/21 P16/BUZZ P17/PWM0 P30 P31 P32 P33 P34 P35 P36 P37 P70/INT0 RES XT1/P74 XT2/P75 VSS1 CF1 CF2 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P71/INT1 P72/INT2/T0IN P72/INT3/T0IN S0/T0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 S47/PF7 S46/PF6 S45/PF5 S44/PF4 S43/PF3 S42/PF2 S41/PF1 S40/PF0 VDD4 S39/PE7 S38/PE6 S37/PE5 S36/PE4 S35/PE3 S34/PE2 S33/PE1 S32/PE0 S31/PD7 S30/PD6 S29/PD5 S28/PD4 S27/PD3 S26/PD2 S25/PD1 S24/PD0 S23/PC7 S22/PC6 S21/PC5 S20/PC4 VP LC866548/40/32/28/24A Pin Assignment QIP100E S48/PG0 S49/PG1 S50/PG2 S51/PG3 P00 P01 P02 P03 VSS2 VDD2 P04 P05 P06 P07 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 S19/PC3 S18/PC2 S17/PC1 S16/PC0 VDD3 S15/T15 S14/T14 S13/T13 S12/T12 S11/T11 S10/T10 S9/T9 S8/T8 S7/T7 S6/T6 S5/T5 S4/T4 S3/T3 S2/T2 S1/T1 Package Dimension (unit : mm) 3151 SANYO : QIP-100E No.6700-5/21 LC866548/40/32/28/24A System Block Diagram Interrupt Control IR Standby Control PLA ROM RC Clock Generator CF PC X’tal Base Timer Bus Interface ACC SIO0 Port 1 B Register SIO1 Port 3 C Register Timer 0 Port 7 ALU Timer 1 Port 8 ADC PSW INT0 to 3 Noise Filtter RAR SI0 Automatic transmission RAM RAM 128 bytes Stack Pointer VFD Controller Port 0 High Voltage Output Watch dog Timer No.6700-6/21 LC866548/40/32/28/24A LC866548A/40A/32A/28A/24A Pin Description Pin Name VSS1, 2 VDD1,2,3,4 VP Port 0 P00 - P07 I/O I/O Function Description Option Power pin (-) *1 Power pin (+) *1 Power pin (+) for the VFD output pull-down resist •8-bit input/output port Input/output in nibble units •Input for port 0 interrupt •Input for HOLD release •15V withstand at N-channel open drain output •Pull-up resistor : Provided/Not provided (each nibble) •Output form : CMOS/N-channel open drain (each bit) Port 1 P10 - P17 I/O •8-bit Input/output port Input/output can be specified in bit unit. •Other pin functions P10 SIO0 data output P11 SIO0 data input/bus input/output P12 SIO0 clock input/output P13 SIO1 data output P14 SIO1 data input/bus input/output P15 SIO1 clock input/output P16 Buzzer output P17 Timer1 output (PWM0 output) •Output form : CMOS/N-channel open drain (each bit) Port 3 P30 - P37 I/O •8-bit input/output port Input/output in bit unit •15V withstand at N-channel open drain output •Output form : CMOS/N-channel open drain (each bit) Port 7 P70 - P73 P74 - P75 Port 8 P80 - P83 P84 - P87 S0/T0 to S6/T6 I/O I I I/O O •4-bit input/output port Input/output in bit unit •2-bit input port •Other pin function P70 INT0 input/HOLD release /Nch-Tr. output for watchdog timer P71 INT1 input/HOLD release input P72 INT2 input/timer 0 event input P73 INT3 input with noise filter/timer 0 event input P74 Input pin XT1 for 32.768kHz crystal resonator oscillation P75 Output pin XT2 for 32.768kHz crystal resonator oscillation •Interrupt received form, vector address rising falling rising/ H level falling INT0 enable enable disable enable INT1 enable enable disable enable INT2 enable enable enable disable INT3 enable enable enable disable •4-bit input/output port Input/output in bit unit •4-bit input port •Other function AD input port (8 port pins) Output for VFD display controller segment/timing in common L level Vector enable enable disable disable 03H 0BH 13H 1BH Pull-down resistor : Provided/Not provided (each bit) (continue) No.6700-7/21 LC866548/40/32/28/24A Pin Name S7/T7 to S15/T15 S16 to S31 I/O O I/O Function Description Option •Output for VFD display controller segment/timing with internal pull-down resistor in common •Internal pull-down resistor output •Output for VFD display controller segment •Other function S16 : High voltage input port PC0 S17 : High voltage input port PC1 S18 : High voltage input port PC2 S19 : High voltage input port PC3 S20 : High voltage input port PC4 S21 : High voltage input port PC5 S22 : High voltage input port PC6 S23 : High voltage input port PC7 Pull-down resistor : Provided/Not provided (each bit) S24 : High voltage input port PD0 S25 : High voltage input port PD1 S26 : High voltage input port PD2 S27 : High voltage input port PD3 S28 : High voltage input port PD4 S29 : High voltage input port PD5 S30 : High voltage input port PD6 S31 : High voltage input port PD7 S32 to S47 I/O •Output for VFD display controller segment •Other function S32 : High voltage input port PE0 S33 : High voltage input port PE1 S34 : High voltage input port PE2 S35 : High voltage input port PE3 S36 : High voltage input port PE4 S37 : High voltage input port PE5 S38 : High voltage input port PE6 S39 : High voltage input port PE7 Pull-down resistor : Provided/Not provided (each bit) S40 : High voltage I/O port PF0 S41 : High voltage I/O port PF1 S42 : High voltage I/O port PF2 S43 : High voltage I/O port PF3 S44 : High voltage I/O port PF4 S45 : High voltage I/O port PF5 S46 : High voltage I/O port PF6 S47 : High voltage I/O port PF7 S48 to S51 I/O •Output for VFD display controller segment •Other function S48 : High voltage I/O port PG0 S49 : High voltage I/O port PG1 S50 : High voltage I/O port PG2 S51 : High voltage I/O port PG3 RES XT1/ P74 I I Reset pin •Input pin for 32.768kHz crystal oscillation •Other function P74 for input port In case of non use, connect to VDD1. (continue) No.6700-8/21 LC866548/40/32/28/24A Pin Name I/O XT2/P75 O CF1 CF2 I O Function Description Option •Output pin for 32.768kHz crystal oscillation •Other function P75 for input port •In case of non use, At using as oscillator, should be left opened. At using as a port, connect to VDD1. Input pin for ceramic resonator oscillation Output pin for ceramic resonator oscillation * All of port options (except pull-up resistor of port 0) can be specified in bit unit. * A state of pins at reset Pin name Input/output mode Port 0 Ports 1, 3 Input Input A state of pull-up resistor specified at pull-up option Fixed pull-up resistor OFF Programmable pull-up resistor OFF S0/T0 to S15/T15 P channel Transistor OFF S16 to S51 P channel Transistor OFF *1 Connect like the following figure to reduce noise into a VDD1 terminal. • Shorted the VSS1 terminal to the VSS2 terminal and to make the back-up time long. LSI VDD1 Power Supply Back-up capacitor VDD2 VDD3 VFD powers VDD4 VSS1 VSS2 No.6700-9/21 LC866548/40/32/28/24A 1. Absolute Maximum Ratings at VSS1=VSS2=0V and Ta=25°C Parameter Symbol Pins Supply voltage VDD MAX VDD1, VDD2 VDD3, VDD4 Input voltage VI(1) VI(2) VO VIO(1) Output voltage Input/output voltage VIO(2) High level output current Peak output current Total output current Low level output current Peak output current Total output current Power dissipation (max.) Operating temperature range Storage temperature range VIO(3) IOPH(1) IOPH(2) IOPH(3) ΣIOAH(1) ΣIOAH(2) ΣIOAH(3) ΣIOAH(4) ΣIOAH(5) ΣIOAH(6) IOPL(1) IOPL(2) ΣIOAL(1) ΣIOAL(2) ΣIOAL(3) Pdmax Conditions min. typ. max. -0.3 +7.0 •Ports 74,75 •Ports 80,81,82, 83 •Port 8 • RES -0.3 VDD+0.3 VP S0/T0-S15/T15 •Port 1 •Ports 70,71,72, 73 •Ports 84,85,86, 87 •Ports 0, 3 at CMOS output option Ports 0, 3 at N-ch open drain output option S16 - S51 Ports 0, 1, 3 VDD-45 VDD+0.3 VDD-45 VDD+0.3 -0.3 VDD+0.3 -0.3 15 VDD-45 VDD+0.3 S0/T0-S15/T15 S16 - S51 Port 0 Ports 1, 3 S0/T0-S15/T15 S16 - S27 S28 - S39 S40 - S51 Ports 0, 1, 3 •Ports 70,71,72, 73 •Ports 84,85,86, 87 Port 0 Ports 1, 3, 70 •Ports 71,72, 73 •Ports 84,85,86, 87 QFP100E VDD1=VDD2 =VDD3=VDD4 Ratings VDD[V] •CMOS output •For each pin. For each pin. For each pin. The total of all pins. -10 unit V mA -30 -15 -30 -30 -55 -60 -60 -60 For each pin. 20 15 The total of all pins. 60 50 20 Ta=-30 to+70°C 500 mW °C Topr -30 70 Tstg -55 125 No.6700-10/21 LC866548/40/32/28/24A 2. Recommended Operating Range at Ta=-30°C to +70°C, VSS1=VSS2=0V Parameter Symbol Pins Conditions Ratings VDD[V] min. typ. max. Operating supply voltage range Hold voltage VDD(1) VDD1=VDD2 =VDD3=VDD4 0.98µs ≤ tCYC tCYC ≤ 400µs 4.5 6.0 VHD VDD1=VDD2 RAMs and the Registers hold voltage at HOLD mode. 2.0 6.0 Pull-down voltage Input high voltage VP VP -35 VDD VIH(1) Port 0 at CMOS output option Port 0 at N-ch open drain output •Port 1 •Ports 72, 73 •Port 3 at CMOS output option Port 3 at N-ch open drain output •Port 70 port input /interrupt •Port 71 • RES Port 70 Watchdog timer •Port 8 •Ports 74 , 75 S16 - S51 VIH(2) VIH(3) VIH(4) VIH(5) VIH(6) VIH(7) VIH(8) Input low voltage VIL(1) VIL(2) VIL(3) VIL(4) VIL(5) VIL(6) VIL(7) Operation cycle time Port 0 at CMOS output option Port 0 at N-ch open drain output •Ports 1, 3 •Ports 72, 73 •Port 70 port input /interrupt •Port 71 • RES Port 70 Watchdog timer •Port 8 •Ports 74 , 75 S16 - S51 4.5 - 6.0 Output disable 4.5 - 6.0 0.33VDD unit V VDD +1.0 Output disable 4.5 - 6.0 0.75VDD 13.5 Output disable 4.5 - 6.0 0.75VDD VDD Output disable Tr. OFF Output disable 4.5 - 6.0 0.75VDD 13.5 4.5 - 6.0 0.75VDD VDD Output disable 4.5 - 6.0 0.9VDD VDD Output disable 4.5 - 6.0 0.75VDD VDD Output P-channel Tr. OFF Output disable 4.5 - 6.0 0.33VDD VDD 4.5 - 6.0 VSS 0.2VDD Output disable 4.5 - 6.0 VSS 0.25VDD Output disable 4.5 - 6.0 VSS 0.25VDD Output disable 4.5 - 6.0 VSS 0.25VDD Output disable 4.5 - 6.0 VSS 0.8VDD -1.0 Output disable 4.5 - 6.0 VSS 0.25VDD Output P-channel Tr. OFF 4.5 - 6.0 VP 0.2VDD 4.5 - 6.0 0.98 400 tCYC +1.0 µs (continue) No.6700-11/21 LC866548/40/32/28/24A Parameter Symbol Oscillation frequency range (Note 1) FmCF(1) CF1, CF2 FmCF(2) CF1, CF2 FmRC FsX’tal XT1, XT2 tmsCF(1) CF1, CF2 tmsCF(2) CF1, CF2 tssX’tal XT1, XT2 Oscillation stable time period (Note 1) Pins Conditions •6MHz (ceramic resonator oscillation) •Refer to figure 1 •3MHz (ceramic resonator oscillation) •Refer to figure 1 RC oscillation •32.768kHz (crystal oscillation) •Refer to figure 2 •6MHz (ceramic resonator oscillation) •Refer to figure 3 •3MHz (ceramic resonator oscillation) •Refer to figure 3 •32.768kHz (crystal oscillation) •Refer to figure 3 Ratings VDD[V] min. typ. 4.5 - 6.0 6 4.5 - 6.0 3 4.5 - 6.0 4.5 - 6.0 0.3 max. unit MHz 0.8 32.768 3.0 4.5 - 6.0 0.1 3.0 4.5 - 6.0 0.1 3.0 4.5 - 6.0 0.7 1.0 kHz ms s (Note 1) The oscillation constant is shown on table 1. No.6700-12/21 LC866548/40/32/28/24A 3. Electrical Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V Parameter Input high current Input low current Output high voltage Symbol Pins Conditions IIH(1) Ports 0, 3 of open drain output IIH(2) •Port 0 without pull-up MOS Tr. •Ports 1, 3 IIH(3) •Ports70,71,72,73 •Port 8 IIH(4) IIH(5) IIH(6) RES Ports 74 , 75 S16 to S51 without pull-down resistor (Ports C, D, E, F,G) •Ports 1, 3 •Port 0 without pull-up MOS Tr. •Output disable •VIN=13.5V (including off-leak current of the output Tr.) •Output disable •Pull-up MOS Tr. OFF •VIN=VDD (including off-leak current of the output Tr.) •Output disable •VIN=VDD (including off-leak current of the output Tr.) VIN=VDD VIN=VDD •Output P-channel Tr. OFF •VIN=VDD IIL(1) IIL(2) •Ports70,71,72,73 •Port 8 IIL(3) IIL(4) VOH(1) VOH(2) VOH(3) VOH(4) RES Ports 74 , 75 Ports 0, 1, 3 of CMOS output VOH(5) VOH(6) S16 to S51 S0/T0 to S15/T15 •Output disable •Pull-up MOS Tr. OFF •VIN=VSS (including off-leak current of the output Tr.) •Output disable •VIN=VSS (including off-leak current of the output Tr.) VIN=VSS VIN=VSS IOH=-1.0mA IOH=-0.1mA IOH=-20mA •IOH=-1mA •The current of any unmeasurement pin is not over 1mA. IOH=-5mA The current of any unmeasurement pin is not over 1mA. Ratings VDD[V] min. typ. max. 4.5 - 6.0 5 4.5 - 6.0 1 4.5 - 6.0 1 4.5 - 6.0 4.5 - 6.0 4.5 - 6.0 1 1 1 4.5 - 6.0 -1 4.5 - 6.0 -1 4.5 - 6.0 -1 4.5 - 6.0 -1 4.5 - 6.0 VDD-1 4.5 - 6.0 VDD-0.5 4.5 - 6.0 VDD-1.8 4.5 - 6.0 VDD-1 unit µA µA V 4.5 - 6.0 VDD-1.8 4.5 - 6.0 VDD-1 (continue) No.6700-13/21 LC866548/40/32/28/24A Parameter Output low voltage Pull-up MOS Tr. resistor Output offleak current Symbol VOL(1) VOL(2) VOL(3) VOL(4) Rpu IOFF(1) Pins Ports 0, 1, 3 Port 70 •Ports 71, 72, 73 •Ports84,85,86,87 Ports 0, 1, 3 IOFF(2) S0/T0 to S6/T6, S16 to S51 without pull-down resistor Resistance of the low level hold Tr. Rinpd S16 to S51 High voltage pull-down resistor Rpd S0/T0 to S15/T15, S16 to S51 with pull-down resistor VP pull-down resistor Hysteresis voltage Rvppd Vp VHIS Pin capacitance CP •Port 1 •Ports 70, 71, 72, 73, 75 • RES All pins Conditions Ratings VDD[V] min. IOL=10mA IOL=1.6mA IOL=1mA IOL=1.6mA 4.5 - 6.0 4.5 - 6.0 4.5 - 6.0 4.5 - 6.0 VOH=0.9VDD 4.5 - 6.0 15 •Output P-ch Tr. OFF •VOUT=VSS •Output P-ch Tr. OFF •VOUT=VDD-40V •Output P-ch Tr. OFF •Using as input ports •Output P-ch Tr. OFF •VOUT=3V •Vp=-30V •VSS=GND •Vp=-30V Output disable 4.5 - 6.0 -1 4.5 - 6.0 -30 •f=1MHz •Unmeasurement terminals for the input are set to VSS level. •Ta=25°C 4.5 - 6.0 typ. 40 max. unit 1.5 0.4 0.4 0.4 V 70 KΩ µA kΩ 200 5.0 60 100 200 5.0 60 100 200 4.5 - 6.0 0.1 VDD V 4.5 - 6.0 10 pF No.6700-14/21 LC866548/40/32/28/24A Serial output Serial input Cycle tCKCY(1) Low Level pulse width High Level pulse width Cycle tCKL(1) 1 tCKH(1) 1 Input clock Symbol tCKCY(2) Low Level pulse width High Level pulse width Data set up time tCKL(2) Data hold time tCKI Output delay time (Serial clock is external clock) Output delay time (Serial clock is internal clock) tCKO(1) Pins •SCK0 •SCK1 •SCK0 •SCK1 tCKH(2) SI0 SI1 SB0 SB1 tICK SO0 SO1 SB0 SB1 tCKO(2) Conditions Ratings Parameter Output clock Serial clock 4. Serial Input/Output Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V Refer to figure 5. VDD[V] min. 4.5 - 6.0 2 •Use pull-up resistor (1kΩ) when open drain output. •Refer to figure 5. 4.5 - 6.0 •Data set-up to SCK0, 1. •Data hold from SCK0, 1. •Refer to figure 5. 4.5 - 6.0 •Use pull-up resistor (1kΩ) when open drain output. •Data hold from SCK0, 1 •Refer to figure 5. 4.5 - 6.0 typ. max. unit tCYC 2 1/2tCKCY 1/2tCKCY µs 0.1 0.1 7/12tCYC +0.2 1/3tCYC +0.2 5. Pulse Input Conditions at Ta=-30°C to +70°C, VSS1=VSS2=0V Parameter Symbol High/low level pulse width tPIH(1) tPIL(1) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) Pins •INT0, INT1 •INT2/T0IN INT3/T0IN (The noise rejection clock is select to 1/1.) INT3/T0IN (The noise rejection clock is select to 1/16.) INT3/T0IN (The noise rejection clock is select to 1/64.) RES Conditions Ratings VDD[V] min. •Interrupt acceptable •Timer0-countable •Interrupt acceptable •Timer0-countable 4.5 - 6.0 1 4.5 - 6.0 2 •Interrupt acceptable •Timer0-countable 4.5 - 6.0 32 •Interrupt acceptable •Timer0-countable 4.5 - 6.0 128 Reset acceptable 4.5 - 6.0 200 typ. max. unit tCYC µs No.6700-15/21 LC866548/40/32/28/24A 6. AD Converter Characteristics at Ta=-30°C to + 70°C, VSS1=VSS2=0V Parameter Resolution Absolute precision (Note2) Conversion time Analog input voltage range Analog port input current Symbol Pins Conditions N ET min. typ. 4.5 - 6.0 4.5 - 6.0 tCAD VAIN Ratings VDD[V] AD conversion time =16 × tCYC (ADCR2=0) *Note3 AD conversion time =32 × tCYC (ADCR2=1) *Note3 AN0 - AN7 IAINH IAINL VAIN=VDD VAIN=VSS 4.5 - 6.0 8 ±1.5 4.5 - 6.0 15.68 (tCYC =0.98µs) 31.36 (tCYC =0.98µs) VSS 4.5 - 6.0 4.5 - 6.0 -1 4.5 - 6.0 max. unit bit LSB 65.28 (tCYC =4.08µs) 130.56 (tCYC =4.08µs) VDD µs 1 µA V (Note 2) Absolute precision excepts quantizing error (±1/2 LSB). (Note 3) The conversion time means the time from executing the AD conversion instruction to setting the complete digital conversion value to the register. 7. Current Dissipation Characteristics at Ta=-30°C to +70°C, VSS1=VSS2=0V Parameter Current dissipation during basic operation (Note 4) Symbol IDDOP(1) IDDOP(2) IDDOP(3) IDDOP(4) Pins Conditions •FmCF=6MHz Ceramic resonator oscillation •Internal RC oscillation stops. •FsXtal=32.768kHz Crystal oscillation •System clock : CF oscillation •1/1 divided •FmCF=3MHz Ceramic resonator oscillation •Internal RC oscillation stops. •FsXtal=32.768kHz Crystal oscillation •System clock : CF oscillation •1/2 divided •FmCF=0Hz (when oscillation stops) •FsXtal=32.768kHz Crystal oscillation •System clock : RC oscillation •1/2 divided •FmCF=0Hz (when oscillation stops) •FsXtal=32.768kHz Crystal oscillation •System clock : Crystal oscillation •Internal RC oscillation stops. •1/2 divided Ratings VDD[V] min. typ. max. 4.5 - 6.0 10 25 4.5 - 6.0 3 9 4.5 - 6.0 0.7 3.4 4.5 - 6.0 35 130 unit mA µA No.6700-16/21 LC866548/40/32/28/24A Parameter Symbol Pins Current dissipation HALT mode (Note 4) IDDHALT(1) IDDHALT(2) IDDHALT(3) IDDHALT(4) Current dissipation HOLD mode (Note 4) IDDHOLD(1) Ratings Conditions VDD[V] •HALT mode •FmCF=6MHz Ceramic resonator oscillation •FsXtal=32.768kHz Crystal oscillation •Internal RC oscillation stops. •System clock : CF oscillation •1/1 divided •HALT mode •FmCF=3MHz Ceramic resonator oscillation •FsXtal=32.768kHz Crystal oscillation •Internal RC oscillation stops. •System clock : CF oscillation •1/2 divided •HALT mode •FmCF=0Hz (when oscillation stops) •FsXtal=32.768kHz Crystal oscillation •System clock : RC oscilaltion •1/2 divided •HALT mode •FmCF=0Hz (when oscillation stops) •FsXtal=32.768kHz Crystal oscillation •System clock : Crystal oscilaltion •Internal RC oscillation stops. •1/2 divided HOLD mode min. typ. max. 4.5 - 6.0 5 14 4.5 - 6.0 2.2 7 4.5 - 6.0 400 1600 4.5 - 6.0 25 100 4.5 - 6.0 0.05 30 unit mA µA µA (Note 4) The currents of the output transistors and the pull-up MOS transistors are ignored. Table 1. Ceramic resonator oscillation guaranteed constant (main clock) Oscillation type Maker Oscillator C1 C2 6MHz ceramic resonator oscillation Murata CSA6.00MG CST6.00MGW KBR-6.0MSB PBRC6.00A (chip type) KBR-6.0MKC PBRC6.00B (chip type) CSA3.00MG CST3.00MGW KBR-3.0MS 33pF 33pF Kyocera 3MHz ceramic resonator oscillation Murata Kyocera on chip 33pF 33pF 33pF 33pF on chip 33pF 33pF on chip 33pF 33pF * Both C1 and C2 must be a K rank (±10%) and SL characteristics. No.6700-17/21 LC866548/40/32/28/24A Table 2. Crystal oscillation guaranteed constant (sub clock) Oscillation type Maker Oscillator C1 C2 Rf Rd 32.768kHz crystal oscillation EPSON CITIZEN C-002RX CFS-308 CFS-206 18pF 18pF 18pF 18pF 10MΩ 10MΩ 680kΩ 330kΩ * Both C3 and C4 must use J rank (±5%) and CH characteristics. (It is about the application which is not in need of high precision. Use K rank (±10%) and SL characteristics.) (Notes) •Since the circuit pattern affects the oscillation frequency, place the oscillation-related parts as close to the oscillation pins as possible with the shortest possible pattern length. •If you use other oscillators herein, we provide no guarantee for the characteristics. CF1 CF2 XT1 XT2 Rf Rd CF C1 Figure 1 C2 Ceramic oscillation circuit C3 Figure 2 X’tal C4 Crystal oscillation circuit No.6700-18/21 LC866548/40/32/28/24A VDD VDD limit 0V Power supply Reset time RES Internal RC resonator oscillation tmsCF CF1, CF2 tssXtal XT1, XT2 Operation mode Unfixed Reset Instruction execution mode OCR6=1 Instruction execution mode < Reset time and oscillation stabilizing time. > HOLD release signal Valid Internal RC resonator oscillation tmsCF CF1, CF2 tssXtal XT1, XT2 Operation mode HOLD Instruction execution mode < HOLD release signal and oscillation stabilizing time. > Figure 3 Oscillation stable time VDD RRES (Note) RES CRES Figure 4 Fix the value of CRES, RRES that is sure to reset until 200µs, after Power supply has been over inferior limit of supply voltage. Reset circuit No.6700-19/21 LC866548/40/32/28/24A 0.5VDD <AC timing point> tCKCY tCKL VDD tCKH SCK0 SCK1 1kΩ tICK tCKI SI0 SI1 tCKO 50pF SO0, SO1 SB0, SB1 <Timing> Figure 5 Serial input / output test condition tPIL Figure 6 <Test load> tPIH Pulse input timing condition No.6700-20/21 LC866548/40/32/28/24A PS No.6700-21/21