Ordering number : EN* 5192B CMOS LSI LC895195 ATA-PI (IDE) CD-ROM Decoder LSI Preliminary Overview Package Dimensions The LC895195 is a CD-ROM decoder LSI that includes both an on-chip IDE interface that was developed jointly with Western Digital and an on-chip subcode ECC function. unit: mm 3214-SQFP144 [LC895195] Features • ATA-PI (IDE) interface • Supports 16× playback (with IORDY) - Using ×16 70 ns DRAMs • 16.6 MB/s transfer rate: Using ×16 70 ns DRAMs • 8.33 MB/s transfer rate: Using ×8 70 ns DRAMs • Supports the use of from 1 M to 32 M of buffer RAM. (DRAM) • Allows the user to arbitrarily set the CD main channel, C2 flag and subcode areas in buffer RAM. • Batch transfer function (function for transferring the CD main channel, C2 flag and subcode data in one operation) • Multi-transfer function (function for sending multiple blocks in one operation) SANYO: SQFP144 Specifications Absolute Maximum Ratings at VSS = 0 V Parameter Symbol Maximum supply voltage I/O voltages Allowable power dissipation Conditions Ratings Unit VDD max Ta = 25°C –0.3 to +7.0 V VI, VO max Ta = 25°C –0.3 to VDD + 0.3 V Pd max Ta ≤ 70°C 550 mW Operating temperature Topr –30 to +75 °C Storage temperature Tstg –55 to +125 °C Soldering heat resistances (pins only) 10 seconds I/O current II, IO max 235 °C ±20* mA Unit Note: * Per cell for basic I/O cells Allowable Operating Ranges at Ta = –30 to +75°C, VSS = 0 V min typ max Supply voltage Parameter Symbol VDD Conditions 4.5 5.0 5.5 V Input voltage range VIN 0 VDD V SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN N3097HA (OT)/22896HA (OT) No. 5192-1/8 LC895195 DC Characteristics at VSS = 0 V, VDD = 4.5 to 5.5 V, Ta = –30 to +75°C Parameter Symbol Applicable Pins* (See below) max Unit 0.8 V 0.8 V 0.8 V 0.4 V 0.4 V 0.4 V IOL = 24 mA: (8) 0.4 V IOL = 2 mA: (4) 0.4 V +10 µA Input high level voltage VIH1 Input low level voltage VIL1 Input high level voltage VIH2 Input low level voltage VIL2 Input high level voltage VIH3 Input low level voltage VIL3 Output high level voltage VOH1 IOH = –2 mA Output low level voltage VOL1 IOL = 2 mA Output high level voltage VOH2 IOH = –8 mA Output low level voltage VOL2 IOL = 8 mA Output high level voltage VOH3 IOH = –4 mA Output low level voltage VOL3 IOL = 24 mA Output high level voltage VOL5 Output high level voltage VOL4 Input leakage current min typ 2.2 TTL compatible: (1) TTL compatible, with pull-up resistor: (9) TTL compatible, Schmitt: (2), and (10) (5), (7), and (9) (3) (6), and (10) V 2.2 V 2.2 V VDD – 2.1 V VDD – 2.1 V VDD – 2.1 IIL VI = VSS, VDD: (1), (2),and (10) –10 Output leakage current IOZ For high-impedance outputs: (6), and (10) –10 Pull-up resistance RUP (9) 40 V 80 +10 µA 160 kΩ Note: * The entries in the “Applicable Pins” column specify the following pin sets. [Input] 1: CSCTRL, SUA0 to SUA6, TEST0 to TEST4 2: SBSO, SCOR, WFCK, ZCS, ZDIOR, ZDIOW, ZDMACK, ZHRST, ZRESET, ZRD, ZWR, BCK, C2PO, LRCK, SDATA, DA0 to DA2, ZCS1FX, ZCS3FX [Output] 3: MCK, MCK2 4: ZRSTCPU, ZRSTIC, ZINT1 5: ZINT, ZSWAIT 6: DMARQ, HINTRQ 7: RA0 to RA9, ZCAS0, ZCAS1, ZLWE, ZOE, ZRAS0, ZRAS1, ZUWE, EXCK 8: IORDY, ZIOCS16 [I/O] 9: D0 to D7, IO0 to IO15 10: DD0 to DD15, ZDASP, ZPDIAG Note: XTAL, XTALCK The above pins are not included in the DC characteristics. Sample Recommended Oscillator Circuit R1 = 120 kΩ R2 = 47 kΩ C1 = 30 pF For a crystal oscillator frequency of 16.9344 MHz. Alternatively: R1 = 3.3 kΩ R2 = None C1 = 5 pF For a crystal oscillator frequency of 33.8688 MHz. For an oscillator frequency of 33.8688, the third harmonic is used. This means that precise component values will be influenced by the printed circuit board. Consult the manufacturer of the crystal to determine the circuit constants for this frequency. No. 5192-2/8 LC895195 Pin Functions Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Pin No. Symbol Type 1 VSS0 P 2 ZRAS0 O Buffer DRAM RAS signal output 0 (This pin is used normally.) 3 ZRAS1 O Buffer DRAM RAS signal output 1 4 VSS0 P 5 ZCAS0 O Buffer DRAM CAS signal output 0 (This pin is used normally.) 6 ZCAS1 O Buffer DRAM CAS signal output 1 7 VSS0 P 8 ZOE O Buffer RAM output enable 9 ZUWE O Buffer RAM upper write enable 10 ZLWE O Buffer RAM lower write enable 11 RA0 O 12 RA1 O 13 RA2 O 14 RA3 O 15 RA4 O 16 RA5 O 17 RA6 O 18 VDD P 19 VSS0 P 20 RA7 O 21 RA8 O 22 RA9 O 23 VSS0 P 24 TEST0 NC TEST1 NC 25 26 Function RA0 to RA6 are the data buffer DRAM address signal output. RA7 to RA9 are the data buffer DRAM address signal output. NC 27 TEST2 NC 28 TEST3 NC 29 NC 30 IO0 B 31 IO1 B 32 IO2 B 33 IO3 B 34 IO4 B 35 IO5 B 36 VSS0 P 37 VDD P 38 IO6 B 39 IO7 B 40 IO8 B 41 IO9 B Data buffer DRAM data I/O 42 IO10 B These pins have built-in pull-up resistors. 43 IO11 B 44 IO12 B 45 IO13 B 46 IO14 B 47 IO15 B 48 EXCK O 49 WFCK I 50 SBSO I Data buffer DRAM data I/O These pins have built-in pull-up resistors. SUB-CODE I/O Note: 1. NC (no connection) pins must be left open. 2. Pin names (signal names) that begin with a Z have negative (inverted) logic. 3. VSS0 is the logic system ground and VSS1 is the IDE interface driver ground. No. 5192-3/8 LC895195 Continued from preceding page. Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Pin No. Symbol Type 51 SCOR I 52 VSS0 P 53 VSS0 P 54 TEST4 I 55 VSS0 P 56 VSS0 P 57 ZINT1 O 58 VSS0 P 59 VSS0 P 60 VSS0 61 Function SUB-CODE input pin Test input. This must be tied low. Interrupt request signal output to the microcontroller from the IDE block. P NC 62 NC 63 VSS0 P 64 SDATA I 65 BCK I 66 LRCK I CD-DSP interface 67 C2PO I 68 MCK2 O 69 VSS0 P 70 XTALCK I Xtal oscillator input 71 XTAL O Xtal oscillator output 72 VSS0 P XTALCK 1/1, 1/2, 1/512, and stop output 73 VDD P 74 MCK O 75 VSS0 P 76 ZRSTIC I Reset signal to drive reset IC 77 CSCTRL I Selects active high or active low for the microcontroller CS line. 78 ZRESET I LSI reset 79 ZRD I Microcontroller data read signal input 80 ZWR I Microcontroller data write signal input 81 ZCS I Input for the register chip select signal from the microcontroller 82 VSS0 P 83 SUA0 I 84 SUA1 I 85 SUA2 I 86 SUA3 I 87 SUA4 I 88 SUA5 I 89 SUA6 I 90 VDD P 91 VSS0 P 92 D0 B 93 D1 B 94 D2 B 95 D3 B 96 D4 B 97 D5 B 98 D6 B 99 D7 B 100 ZINT O XTALCK 1/1, 1/2, and stop output Microcontroller register select signals Microcontroller data signals These pins have built-in pull-up resistors. Interrupt request signal output to the microcontroller Note: 1. NC (no connection) pins must be left open. 2. Pin names (signal names) that begin with a Z have negative (inverted) logic. 3. VSS0 is the logic system ground and VSS1 is the IDE interface driver ground. Continued on next page. No. 5192-4/8 LC895195 Continued from preceding page. Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, NC: No connection pin Pin No. Symbol Type 101 ZRSTCPU O 102 ZWAIT O 103 ZHRST I 104 ZDASP B 105 ZCS3FX I 106 ZCS1FX I 107 DA2 I 108 VSS0 P 109 VDD P 110 DA0 I 111 ZPDIAG B 112 DA1 I 113 ZIOCS16 O 114 HINTRQ O 115 ZDMACK I 116 VSS1 P 117 IORDY O 118 ZDIOR I 119 ZDIOW I 120 DMARQ O 121 DD15 B 122 VSS1 P 123 DD0 B 124 DD14 B 125 DD1 B 126 DD13 B 127 VSS1 P 128 VDD P 129 DD2 B 130 DD12 B 131 DD3 B 132 VSS1 P 133 DD11 B 134 DD4 B 135 DD10 B 136 VSS1 P 137 VDD P 138 DD5 B 139 DD9 B 140 DD6 B 141 VSS1 P 142 DD8 B 143 DD7 B 144 VDD P Function ATAPI control signals ATAPI control signals ATAPI control signals ATAPI data bus ATAPI data bus ATAPI data bus ATAPI data bus ATAPI data bus ATAPI data bus Note: 1. NC (no connection) pins must be left open. 2. Pin names (signal names) that begin with a Z have negative (inverted) logic. 3. VSS0 is the logic system ground and VSS1 is the IDE interface driver ground. No. 5192-5/8 LC895195 Pin Functions 1. ATA-PI Pins • ZCS1FX (input) Chip select signal for selecting the command block register. • ZCS3FX (input) Chip select signal for selecting the control block register. • DA0 to DA2 (input) Address for accessing the ATAPI registers. • ZDASP (I/O) Drive 1 is output and drive 0 is input. Signal used to indicate to drive 0 that drive 1 exists. An external pull-up resistor must be connected to this pin. • DD0 to DD15 (I/O) 16-bit data bus. Can be used for either 8-bit or 16-bit data transfers. • ZDIOR (input) Read strobe signal from the host. • ZDIOW (input) Write strobe signal from the host. • ZDMACK (input) Acknowledge signal from the host in response to the drive DMARQ request signal during DMA transfers. The pin circuit does not include a pull-up resistor. • DMARQ (output) Drive request signal during DMA transfers • HINTRQ (output) Drive interrupt signal to the host • ZIOCS16 (output) Signal asserted by the drive when the drive supports 16-bit transfers. This signal is not asserted during DMA transfers. • IORDY (output) Signal that indicates that the drive has completed response preparations during data transfers. This signal is low when the drive is not ready. • ZPDIAG (I/O) Signal asserted by drive 1 to inform drive 0 that diagnostics have completed. An external pull-up resistor must be connected to this pin. • ZHRST (input) Reset signal from the host. The pin circuit does not include a pull-up resistor. 2. MC (microcontroller) Interface Pins • ZCS (input) Microcontroller chip select signal • CSCTRL (input) Microcontroller chip select logic selection signal High - ZCS functions as an active low signal. Low - ZCS functions as an active high signal. • ZRD, ZWR, SUA0 to SUA6 (input) Microcontroller interface control signals. The SUA0 to SUA6 pins are address lines. No. 5192-6/8 LC895195 • ZSWAIT (output) When the microcontroller is accessing RAM, the sub-CPU must wait if this pin is low. • D7 to D0 (I/O) Microcontroller data bus. Pull-up resistors are built in. • ZINT (output) Interrupt request signal output to the microcontroller. A pull-up resistor is built in. • ZINT1 (output) Interrupt request signal output from the IDE block to the microcontroller. An external pull-up resistor must be connected to this pin. 3. Buffer RAM Pins • IO0 to IO15 (I/O) Buffer DRAM data bus. A pull-up resistor is built in. • RA0 to RA9 (output) Buffer RAM address lines. • ZRAS0, ZRAS1 (output) Buffer DRAM RAS outputs. Normally, ZRAS0 is used, but if two 1-Mb (64k × 16 bits) chips are used, then both ZRAS0 and ZRAS1 are used, one for each of the chips. • ZCAS0, ZCAS1 (output) Buffer DRAM CAS outputs. Normally, ZCAS0 is used, but if two 1-Mb (64k × 16 bits) chips are used, then both ZCAS0 and ZCAS1 are used, one for each of the chips. When using a two-CAS type DRAM, connect ZCAS0 to UCAS, and ZCAS1 to LCAS. • ZOE (output) Buffer DRAM read output signal. • ZUWE, ZLWE (output) Buffer DRAM write output signals. Connected the corresponding DRAM pins. 4. Subcode Interface Pins • EXCK, WFCK, SBSO, SCOR (input or output) These are the subcode interface connections. The LC895195 acquires subcode data by connection with the CDDSP and sends that data to the host. 5. CD-DSP Data Pins • BCK, SDATA, LRCK, C2PO (input) The LC895195 reads in the CD-ROM data by connecting to the CD-DSP. The C2PO pin is used for the C2 flags. 6. Other Pins • ZRESET (input) This is the LC895195 reset pin. The LC895195 is reset by a low level on this pin. This pin must be held low for at least 1 µs when power is first applied. • XTALCK, XTAL These pins can drive a 16.9344-MHz or 33.8688-MHz oscillator. Alternatively, an external clock can be input to the XTALCK pin. • MCK (output) This pin outputs either the XTALCK frequency or that frequency divided by 2. This output can be turned off. • MCK2 (output) This pin outputs either the XTALCK frequency or that frequency divided by 512. This output can be turned off. • ZRSTIC (output) This pin can be set to output a low level either by writing to the microcontroller write register R46 bit 7 (ZSYSRTS) or by setting the ZHRST pin (pin 103) low. This pin goes to the high-impedance state when both ZSYSRST and ZHRST are high. Since this pin has an open-drain circuit, an external pull-up resistor must be used. No. 5192-7/8 LC895195 • ZRSTCPU (output) When an ATAPI soft reset command (08h) has been received, this pin generates a low-going pulse with a duration of about 1 ms (when the XTALCK frequency is 34 MHz). (This pulse will have a duration of about 2 ms when the XTALCK frequency is 16 MHz.) At this time a microcontroller interrupt will be generated. When the ZRESET pin (pin 78) becomes active (low), the ZRESET signal will be output without change to the ZRSTCPU pin. Since this pin has an open-drain circuit, an external pull-up resistor must be used. ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1997. Specifications and information herein are subject to change without notice. No. 5192-8/8