Ordering number : EN*5824 CMOS IC LC895994 CD-R Encoder/Decoder LSI with Built-in ATAPI (IDE) Interface Preliminary Overview Package Dimensions The LC895994 is a CD-R LSI that provides a wide range of functions including CD-ROM decoding (including ECC) and encoding, subcode Q encoding (CRC addition) and decoding, CD encoding, ATIP decoding and CLV servo, and an IDE interface that includes the register block. unit: mm 3153A-QFP160E [LC895994] Features • ECC and EDC correction/addition for the CD-ROM data (during decoding and encoding) • ATIP decoding and CRC checking for both encoding and decoding • CLV servo control using ATIP data during encoding • CIRC code insertion and EFM modulation during encoding • Support for PCA random EFM output during encoding • Support for CD-ReWritable (CD-RW) Write Strategy signal output • Access to buffer RAM from microcontroller via LC895994 • Built-in ATAPI (IDE) interface • Speeds of 12× for decoding and 4× for encoding — Frequencies Decoding: 17.2872 MHz Encoding: 17.2872 MHz without Write Strategy support 69.1488 MHz with Write Strategy support • IDE Transfer rate: 13.3 MB/s when using 16-bit data path 80-ns DRAM chips • Buffer RAM sizes between 1 and 32 megabits (using 16bit DRAMs) • User control over sizes of CD main channel, C2 flag areas in buffer RAM • Built-in batch transfer function for transferring entire CD main channel, C2 flag, or subcode area in a single operation • Built-in multiblock transfer function for transferring multiple blocks in a single operation SANYO: QIP160E SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN 42098RM (OT) No. 5824-1/7 LC895994 Specifications Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Maximum supply voltage I/O voltage Symbol Conditions Ratings VDD max VI, VO Allowable power dissipation Pd max Unit –0.3 to +7.0 V –0.3 to VDD + 0.3 Ta ≤ 70°C V 600 mW Operating temperature Topr –30 to +70 Storage temperature Tstg –55 to +125 °C 260 °C Solder resistance (Pins only) 10 seconds °C Allowable Operating Range at Ta = –30 to +70°C, VSS = 0 V Parameter Symbol Conditions Ratings min typ Supply voltage VDD 4.5 Input voltage range VIN 0 5.0 Unit max 5.5 V VDD V DC Characteristics at Ta = –30 to +70°C, VSS = 0 V, VDD = 4.5 to 5.5 V Parameter Symbol Input high-level voltage VIH Input low-level voltage VIL Input high-level voltage VIH Input low-level voltage VIL Input high-level voltage VIH Conditions TTL levels, for pin types 1 and 7 Ratings min typ Unit max 2.2 V 0.8 TTL levels, for pin types 8 and 9, with pull-up resistors 2.2 TTL levels, for pin types 2 and 10, with Schmitt inputs 2.5 V V 0.8 V V 0.6 V Input low-level voltage VIL Output high-level voltage VOH IOH = –2 mA, for pin type 6 Output low-level voltage VOL IOL = 2 mA, for pin type 6 Output high-level voltage VOH IOH = –24 mA, for pin type 3 Output low-level voltage VOL IOL = 24 mA, for pin type 3 Output high-level voltage VOH IOH = –2 mA, for pin types 4, 7, and 8 Output low-level voltage VOL IOL = 2 mA, for pin types 4, 7, and 8 Output high-level voltage VOH IOH = –24 mA, for pin types 5 and 10 Output low-level voltage VOL IOL = 24 mA, for pin types 5 and 10 0.4 Output low-level voltage VOL IOL = 2 mA, for pin type 9. 0.4 V +10 µA Input leakage current IIL Output leakage current Pull-up resistance RUP VDD — 2.1 0.4 VDD — 2.1 0.4 0.4 When set to high-impedance output: For pin types 4, 5, 7, and 10. –10 40 V V VDD — 2.1 –10 V V VDD — 2.1 VI = VSS, VDD, for pin types 1, 2, 7, and 10 For pin types 8 and 9 V V V 80 V +10 µA 160 kΩ The pin types above refer to the following groups. Input (1) SUA0 to SUA7, TEST0 to TEST6, RESET (2) BCK, BICLKIN, BIDATAI, C2PO, DA0 to DA2, LOCKIN, LRCK, PLLOUTIN, ROUGH, SBSO, SCOR, SDATA, WFCK, CS, CS1FX, CS3FX, DIOR, DIOW, DMACK, HRST, RD, WR Output (3) EFM (4) CLVMDP, CLVMDS, FSW (5) DMARQ, HINTRQ, IORDY, IOCS16 (6) DATACKO, EFMG, EFMGATE0 to EFMGATE3, EXCK, LOCK, MCK, MON, PSUBSYNC, RA0 to RA9, SUBSYNC, CAS0, CAS1, ERROR, EXTACK, FRCK, LWE, OE, RAS0, RAS1, UWE Input (7) ATIPSYNC, Reserve0 to Reserve5 (8) D0 to D7, IO0 to IO15 (9) INT0 to INT1, SWAIT (10) DD0 to DD15, DASP, PDIAG No. 5824-2/7 LC895994 Block Diagram *2 *3 *4 *5 *6 *7 *8 *9 *10 *11 *12 **1 BCK, SDATA, LRCK, C2PO DD0 to DD15, DASP, PDIAG CS1FX, CS3FX, DA0 to DA2, DIOR, DIOW, DMACK DMARQ, HINTRQ, IOCS16, IORDY RD, WR, SUA0 to SUA6, CS D0 to D7 IO0 to IO15 RA0 to RA9, RAS0, RAS1, CAS0, CAS1, OE, UWE, LWE PLLOUTIN, ROUGH, LOCKIN, BICLKIN, BIDATAIN ERROR, LOCK, CLV+ (MDP), CLV– (MDS), MON, FSW SUBSYNC, PSUBSYNC, FRCK, EFM, EFMG, EFMGATE3 to EFMGATE0, EXTACK, DATACKO HISIDE (WD25C32) is made by WESTERN DIGITAL. No. 5824-3/7 LC895994 Pin Descriptions Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, N: No connection pin Pin No. Pin Name Type 1 VSS P Description 2 Reserve0 O Reserved for future expansion (Must be left open if unused.) 3 Reserve1 I Reserved for future expansion (Must be tied to ground if unused.) 4 Reserve2 I Reserved for future expansion (Must be tied to ground if unused.) 5 TEST1 I Test pin (connect to VSS) 6 XTALCK I Crystal oscillator circuit input pin (17.2872 to 69.1488 MHz) 7 XTAL O Crystal oscillator circuit output pin 8 TEST2 I Test pin (connect to VSS) 9 MCK O Master Clock output pin 10 TEST3 I Test pin (connect to VSS) 11 PSUBSYNC O Pseudo-subcode synchronization output 12 EXTACK O ATIP synchronization acknowledge signal output 13 TEST4 I Test pin (connect to VSS) 14 VDD P 15 VSS P 16 CLV+ (MDP) O 17 CLV– (MDS) O 18 MON O 19 FSW O 20 VDD P 21 VSS P 22 PLLOUTIN I Wobble signal carrier clock input pin 23 ROUGH I Rough CLV servo wobble signal input pin 24 LOCKIN I CD decoder lock signal input pin 25 LOCK O CLV servo lock monitor pin 26 ERROR O ATIP parity error detection pin 27 ATIPSYNC B ATIP synchronization signal I/O pin 28 BIDATAI I Biphase data input pin 29 BICLKIN I Biphase data transfer clock input pin 30 DATACKO O 4.3218 MHz (normal speed) oscillator output 31 IO0 B 32 IO1 B 33 IO2 B 34 IO3 B 35 IO4 B 36 IO5 B 37 IO6 B 38 IO7 B 39 IO8 B 40 VDD P 41 VSS P CLV servo signal output pins Data signal pins for ROM encoder/decoder buffer RAM, with pull-up resistors Continued on next page. No. 5824-4/7 LC895994 Continued from preceding page. Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power supply pin, N: No connection pin Pin No. Pin Name Type 42 IO9 B 43 IO10 B 44 IO11 B 45 IO12 B 46 IO13 B 47 IO14 B 48 IO15 B 49 VSS P 50 RA0 O 51 RA1 O 52 RA2 O 53 RA3 O 54 RA4 O 55 RA5 O 56 RA6 O 57 RA7 O 58 RA8 O 59 RA9 O 60 VDD P 61 VSS P 62 RAS0 O 63 RAS1 O 64 CAS0 O 65 CAS1 O Description Data signal pins for ROM encoder/decoder DRAM, with pull-up resistors Address signal pins for ROM encoder/decoder DRAM DRAM RAS signal output pins DRAM CAS signal output pins 66 OE O DRAM output enable signal output pin 67 UWE O DRAM upper write enable signal output pin 68 LWE O DRAM lower write enable signal output pin 69 TEST0 I Test pin (connect to VSS) 70 VDD P 71 EXCK O 72 WFCK I Subcode frame synchronization input pin 73 SBSO I Subcode serial data input pin 74 SCOR I Subcode block synchronization input pin 75 VSS P Subcode data read shift clock output pin 76 BCK I Serial data input clock input pin 77 SDATA I Serial data input pin 78 LRCK I 44.1-kHz strobe signal input pin 79 C2PO I C2 pointer input pin 80 VDD P 81 VSS P 82 HRST I 83 DASP B 84 CS3FX I 85 CS1FX I 86 VDD P I 87 DA2 88 DA0 I 89 PDIAG B IDE pins IDE pins Continued on next page. No. 5824-5/7 LC895994 Continued from preceding page. Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power Supply pin, N: No connection pin Pin No. Pin Name Type 90 DA1 I 91 IOCS16 O 92 INTRQ O P 93 VSS 94 DMACK I 95 IORDY O 96 DIOR I 97 DIOW I 98 DMARQ O 99 DD15 B 100 VDD P 101 VSS P 102 DD0 B 103 DD14 B 104 DD1 B 105 DD13 B 106 DD2 B 107 VSS P 108 DD12 B 109 DD3 B 110 DD11 B 111 VSS P 112 DD4 B 113 DD10 B 114 DD5 B 115 VSS P 116 DD9 B 117 DD6 B 118 DD8 B Description IDE pins IDE pins IDE pins IDE pins IDE pins IDE pins 119 DD7 B 120 VDD P 121 VSS P 122 SUBSYNC O Subcode synchronization signal output pin 123 FRCK O EFM frame synchronization signal output pin 124 EFMG O EFM output gate signal output pin 125 EFM O EFM signal output pin 126 EFMGATE0 O 127 EFMGATE1 O 128 EFMGATE2 O 129 EFMGATE3 O 130 TEST5 I 131 VSS P 132 TEST6 I EFM pulse width detection gate signals Test pin (connect to VSS) Test pin (connect to VSS) Continued on next page. No. 5824-6/7 LC895994 Continued from preceding page. Type: I: Input pin, O: Output pin, B: Bidirectional pin, P: Power Supply pin, N: No connection pin Pin No. Pin Name Type 133 SUA0 I 134 SUA1 I 135 SUA2 I 136 SUA3 I 137 SUA4 I Description Command register selection address input pins 138 SUA5 I 139 SUA6 I 140 VDD P 141 VSS P 142 D0 B 143 D1 B 144 D2 B 145 D3 B 146 D4 B 147 D5 B 148 D6 B 149 D7 B 150 RESET I Reset pin 151 CS I Chip select signal from microcontroller 152 RD I Data read signal from microcontroller 153 WR I Data write signal from microcontroller 154 SWAIT O Wait signal to microcontroller 155 INT0 O 156 INT1 O 157 Reserve3 O 158 Reserve4 O 159 Reserve5 O 160 VDD P Microcontroller data signal pins, with pull-up resistors Interrupt request signals to microcontroller. Open drain outputs with built-in pull-up resistors. Reserved for future expansion (Must be left open if unused.) ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of April, 1998. Specifications and information herein are subject to change without notice. PS No. 5824-7/7