Ordering number : EN*4909A CMOS LSI LC8220 JPEG Still Color Image Compression/Decompression LSI Preliminaly Overview Package Dimensions The LC8220 JPEG LSI implements digital still image compression and decompression conforming to the JPEG (Joint Photographic Expert Group) standard. The LC8220 includes the baseline system of the ISO 10918 (JPEG) standard, and requires no external components to construct an application that performs JPEG compliant compression/decompression. unit: mm 3153A-QFP160 [LC8220] Features • Conforms to the ISO 10918-1 baseline system • Four quantization tables and four Huffman tables (two for AC and two for DC) are built in. • Hardware support for JPEG marker codes • Built-in bidirectional YUV - RGB converter • Many color component sampling ratios are supported. (e.g., YUV 4:1:1 and YMCK 1:1:1:1, etc.) • Level shift function that can be defined for each component • Built-in dual buffers for reduced data transfer load • Bus sizing function that allows direct connection to 8-, 16-, and 32-bit busses • Endian control function • Three independent data buses SANYO: QFP160 SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 32896HA (OT)/D1694TH (OT) No. 4909-1/13 LC8220 Block Diagram The LC8220 has three independent buses. Pin Assignment No. 4909-2/13 LC8220 Pin Functions Pin No. Symbol I/O Function 1 VSS 2 CTLCS I Control bus chip select*2 3 CTLRD I Control bus read request*3 4 CTLWR I Control bus write request*4 5 CTLRDY O Control bus ready for read/write requests*5 6 CTLERR O Error interrupt request 7 CTLINT O Control bus interrupt request 8 CPUCTL I Connected CPU type setting for the control bus*1 9 CTLSIZE I 10 VDD — +5 V power supply 11 VSS — Ground 12 CTLA7 I 13 CTLA6 I 14 CTLA5 I 15 CTLA4 I 16 CTLA3 I 17 CTLA2 I 18 CTLA1 I 19 CTLA0 20 VDD — +5 V power supply 21 VSS — Ground 22 CTLD15 I/O — Ground Bus width selection for the control bus (0: 8 bits, 1: 16 bits) Control address bus I 23 CTLD14 I/O 24 CTLD13 I/O 25 CTLD12 I/O 26 CTLD11 I/O 27 CTLD10 I/O 28 CTLD9 I/O Control data bus (D15 to D8 are unused if an 8-bit CPU is used.*7) 29 CTLD8 I/O 30 VDD — +5 V power supply 31 VSS — Ground 32 CTLD7 I/O 33 CTLD6 I/O 34 CTLD5 I/O 35 CTLD4 I/O 36 CTLD3 I/O 37 CTLD2 I/O 38 CTLD1 I/O Control data bus 39 CTLD0 I/O 40 VDD — +5 V power supply 41 VSS — Ground 42 CLK I System clock 43 CLKSEL I Clock divisor selection (0: no divisor, 1: divisor used)*6 44 RESET I System reset 45 TEST I Test mode selection (0: normal operation, 1: test mode)*6 46 TESTOUT O Test result output*8 47 MDD10 I/O 48 MDD9 I/O 49 MDD8 I/O 50 VDD — +5 V power supply 51 VSS — Ground 52 MDD7 I/O 53 MDD6 I/O 54 MDD5 I/O Test mode data bus*7 Test mode data bus*7 Continued on next page. No. 4909-3/13 LC8220 Continued from preceding page. Pin No. 55 Symbol MDD4 I/O Function I/O 56 MDD3 I/O 57 MDD2 I/O 58 MDD1 I/O Test mode data bus*7 59 MDD0 I/O 60 VDD — +5 V power supply 61 VSS — Ground 62 TESTI1 I 63 TESTI2 I 64 TESTI3 I 65 TESTI4 I 66 TESTI5 I 67 TESTO1 O 68 TESTO2 O 69 TESTI6 I Test mode input pin*9 70 TESTO3 O Test mode output pin*8 71 CPUPX I Connected CPU type setting for the pixel bus*1 72 PXCS I Pixel bus chip select*2 73 PXRD I Pixel bus read request*3 74 PXWR I Pixel bus write request*4 75 PXRDY O Pixel bus ready for read/write requests*5 76 PXINT O Pixel bus interrupt request 77 PXRLS I Pixel bus interrupt release 78 PXEND O Pixel bus last data output indicator 79 (NC) — Test mode input pins*9 Test mode output pins*8 80 VDD — +5 V power supply 81 VSS — Ground 82 PXD31 I/O 83 PXD30 I/O 84 PXD29 I/O 85 PXD28 I/O 86 PXD27 I/O 87 PXD26 I/O 88 PXD25 I/O Pixel data bus (D31 to D16 are unused if a 16-bit CPU is used and D31 to D8 are unused if an 8-bit CPU is used.*7) 89 PXD24 I/O 90 VDD — +5 V power supply 91 VSS — Ground 92 PXD23 I/O 93 PXD22 I/O 94 PXD21 I/O 95 PXD20 I/O 96 PXD19 I/O 97 PXD18 I/O 98 PXD17 I/O Pixel data bus (D31 to D16 are unused if a 16-bit CPU is used and D31 to D8 are unused if an 8-bit CPU is used.*7) 99 PXD16 I/O 100 VDD — +5 V power supply 101 VSS — Ground 102 PXD15 I/O 103 PXD14 I/O 104 PXD13 I/O 105 PXD12 I/O 106 PXD11 I/O 107 PXD10 I/O 108 PXD9 I/O 109 PXD8 I/O Pixel data bus (D31 to D16 are unused if a 16-bit CPU is used and D31 to D8 are unused if an 8-bit CPU is used.*7) Continued on next page. No. 4909-4/13 LC8220 Continued from preceding page. Pin No. Symbol I/O Function — +5 V power supply VSS — Ground PXD7 I/O 113 PXD6 I/O 114 PXD5 I/O 115 PXD4 I/O 116 PXD3 I/O 117 PXD2 I/O 118 PXD1 I/O 119 PXD0 I/O 120 VDD — +5 V power supply 121 VSS — Ground 122 PXSIZE0 I Bus width selection for the pixel bus 123 PXSIZE1 I (PXSIZE [1,0] = 00: 8 bits, 01: 16 bits, 1*: 32 bits) 124 (NC) 110 VDD 111 112 Pixel data bus — 125 CDCS I Code bus chip select*2 126 CDRD I Code bus read request*3 127 CDWR I Code bus write request*4 128 CDRDY O Code bus ready for read/write requests*5 129 CDINT O Code bus interrupt request 130 CDRLS I Code bus interrupt release 131 CDEND O Code bus last data output 132 CDFLSH I Code bus forcible buffer flush 133 (NC) — 134 (NC) — 135 (NC) — 136 (NC) — 137 (NC) — 138 CPUCD I Connected CPU type setting for the code bus*1 139 CDSIZE I Bus width setting for the code bus (0: 8 bits, 1: 16 bits) 140 VDD — +5 V power supply 141 VSS — Ground 142 CDD15 I/O 143 CDD14 I/O 144 CDD13 I/O 145 CDD12 I/O 146 CDD11 I/O 147 CDD10 I/O 148 CDD9 I/O 149 CDD8 I/O 150 VDD — +5 V power supply 151 VSS — Ground 152 CDD7 I/O 153 CDD6 I/O 154 CDD5 I/O 155 CDD4 I/O 156 CDD3 I/O 157 CDD2 I/O 158 CDD1 I/O 159 CDD0 I/O 160 VDD — Note 1, 2, 3, 4, 5: 6: 7: 8: 9: Code data bus (D15 to D8 are unused if an 8-bit CPU is used.*7) Code data bus +5 V power supply These items are related to the CPU type. Connect to VSS (ground). Must be pulled up. These are NC pins. Connect to VDD. Z**CS2 Z**RD3 8086 family CPU (CPU = 1) CS RD Z**WR4 Z**RDY5 WR RDY 68000 family CPU (CPU = 0) AS R/W DS ACK No. 4909-5/13 LC8220 Specifications Absolute Maximum Ratings at Ta = 25°C, GND = 0 V Parameter Symbol Maximum supply voltage Conditions Ratings VDD max I/O voltages VI, VO Unit –0.3 to +7.0 V –0.3 to VDD + 0.3 V Operating temperature Topr –30 to +70 °C Storage temperature Tstg –55 to +125 °C Hand soldering: 3 seconds 350 °C Reflow soldering: 10 seconds 235 °C Soldering temperature Allowable Operating Ranges at Ta = –30 to +70°C, GND = 0 V Parameter Symbol Conditions min typ max Unit Supply voltage VDD 4.5 5.5 V Input voltage VIN 0 VDD V max Unit DC Characteristics at Ta = –30 to +70°C, VDD = 4.5 to 5.5 V, GND = 0 V Parameter Symbol Conditions Input high level voltage VIH TTL compatible: CTLCS, CTLRD, CTLWR, CPUCTL, CTLSIZE, CTLA7 to CTLA0, CLKSEL, RESET, TEST, CTLD15 to CTLD0 Input low level voltage VIL TTL compatible: CPUPX, PXCS, PXRD, PXWR, PXD31 to PXD0, PXRLS, PXSIZE0 Input leakage current IL PXSIZE1, CDCS, CDRD, CDWR, CDRLS, CDFLSH, CPUCD, CDSIZE, CDD15 to CDD0 VOH IOH = –3 mA, TTL compatible: CTLRDY, CTLERR, CTLINT, TESTOUT, CTLD15 to CTLD0, PXRDY, PXINT, PXEND, PXD31 to PXD0, CDRDY, CDINT, CDEND, CDD15 to CDD0 Output low level voltage VOL IOH = –3 mA, TTL compatible: CTLRDY, CTLERR, CTLINT, TESTOUT, CTLD15 to CTLD0, PXRDY, PXINT, PXEND, PXD31 to PXD0, CDRDY, CDINT, CDEND, CDD15 to CDD0 Output leakage current IOZ For high impedance outputs: CTLD15 to CTLD0, PXD31 to PXD0, CDD15 to CDD0 Output high level voltage Oscillator frequency fOSC CLK Current drain IDD VDD = 5.0 V min typ 2.2 V –10 0.8 V +10 µA VDD – 2.1 V –10 0.4 V +10 µA 16.67 145 MHz mA No. 4909-6/13 LC8220 AC Characteristics Code Bus Interface Timing Code Bus Read Cycle Code Bus Read Cycle (type 1) Code Bus Read Cycle (type 2) Item Minimum Maximum Unit t1 Read signal assert setup time (referenced to CLK) 8 ns t2 Read signal assert hold time (referenced to CLK) 15 ns t3 Chip select stabilization time (referenced to the read signal) 0 ns t4 Chip select hold time (referenced to the read signal) 0 t5 Ready signal response delay time (referenced to the read signal) t6 Ready signal release delay time (referenced to the read signal) t7 Read signal negate setup time (referenced to CLK) 8 t8 Read signal negate hold time (referenced to CLK) 15 t9 Data output delay time (referenced to the ready signal) t10 Data output hold time (referenced to the read signal) T Clock period 60 ns T + t1 + 20 ns t7 + 27 ns ns ns 15 ns t7 + 15 ns ns No. 4909-7/13 LC8220 Code Bus Write Cycle Code Bus Write Cycle (type 1) Code Bus Write Cycle (type 2) Item Minimum Maximum Unit t1 Write signal assert setup time (referenced to CLK) 8 ns t2 Write signal assert hold time (referenced to CLK) 15 ns t3 Chip select stabilization time (referenced to the write signal) 0 ns t4 Chip select hold time (referenced to the write signal) 0 ns t5 Write cycle selection signal stabilization time (referenced to the write signal) 0 ns t6 Write cycle selection signal hold time (referenced to the write signal) 0 t7 Ready signal response delay time (referenced to the write signal) t8 Ready signal release delay time (referenced to the write signal) ns T + t1 + 20 ns t9 + 27 ns t9 Write signal negate setup time (referenced to CLK) 8 ns t10 Write signal negate hold time (referenced to CLK) 15 ns t11 Data setup time (referenced to the ready signal) 45 ns t12 Data hold time (referenced to the ready signal) 15 ns Clock period 60 ns T No. 4909-8/13 LC8220 Pixel Bus Interface Timing Pixel Bus Read Cycle Pixel Bus Read Cycle (type 1) Pixel Bus Read Cycle (type 2) Item Minimum Maximum Unit t1 Read signal assert setup time (referenced to CLK) 8 ns t2 Read signal assert hold time (referenced to CLK) 15 ns t3 Chip select stabilization time (referenced to the read signal) 5 ns t4 Chip select hold time (referenced to the read signal) 5 t5 Ready signal response delay time (referenced to the read signal) t6 Ready signal release delay time (referenced to the read signal) t7 Read signal negate setup time (referenced to CLK) 8 t8 Read signal negate hold time (referenced to CLK) 15 t9 Data output delay time (referenced to the ready signal) t10 Data output hold time (referenced to the read signal) T Clock period 60 ns T + t1 + 20 ns t7 + 28 ns ns ns 15 ns t7 + 18 ns ns No. 4909-9/13 LC8220 Pixel Bus Write Cycle Pixel Bus Write Cycle (type 1) Pixel Bus Write Cycle (type 2) Item Minimum Maximum Unit t1 Write signal assert setup time (referenced to CLK) 8 ns t2 Write signal assert hold time (referenced to CLK) 15 ns t3 Chip select stabilization time (referenced to the write signal) 5 ns t4 Chip select hold time (referenced to the write signal) 5 ns t5 Write cycle selection signal stabilization time (referenced to the write signal) 5 ns t6 Write cycle selection signal hold time (referenced to the write signal) 5 t7 Ready signal response delay time (referenced to the write signal) t8 Ready signal release delay time (referenced to the write signal) ns T + t1 + 20 ns t9 + 28 ns t9 Write signal negate setup time (referenced to CLK) 8 ns t10 Write signal negate hold time (referenced to CLK) 15 ns t11 Data setup time (referenced to the ready signal) 60 ns t12 Data hold time (referenced to the ready signal) 20 ns Clock period 60 ns T No. 4909-10/13 LC8220 Control Bus Interface Timing Control Bus Read Cycle Control Bus Register Read Cycle (type 1) Control Bus Register Read Cycle (type 2) Item Minimum Maximum Unit t1 Read signal assert setup time (referenced to CLK) 10 ns t2 Read signal assert hold time (referenced to CLK) 15 ns t3 Chip select stabilization time (referenced to the read signal) 10 ns t4 Chip select hold time (referenced to the read signal) 15 ns t5 Address stabilization time (referenced to the read signal) 0 ns t6 Address hold time (referenced to the read signal) 5 t7 Ready signal response delay time (referenced to the read signal) t8 Ready signal release delay time (referenced to the read signal) ns T + t1 + 24 ns t9 + 30 ns t9 Read signal negate setup time (referenced to CLK) 12 ns t10 Read signal negate hold time (referenced to CLK) 15 ns t11 Data output delay time (referenced to the ready signal) t12 Data output hold time (referenced to the read signal) T Clock period 60 0 ns t9 + 30 ns ns No. 4909-11/13 LC8220 Control Bus Write Cycle Control Bus Register Write Cycle (type 1) Control Bus Register Write Cycle (type 2) Item Minimum Maximum Unit t1 Write signal assert setup time (referenced to CLK) 12 ns t2 Write signal assert hold time (referenced to CLK) 15 ns t3 Chip select stabilization time (referenced to the write signal) 10 ns t4 Chip select hold time (referenced to the write signal) 15 ns t5 Write cycle selection signal stabilization time (referenced to the write signal) 10 ns t6 Write cycle selection signal hold time (referenced to the write signal) 10 ns t7 Address stabilization time (referenced to the write signal) 0 ns t8 Address hold time (referenced to the write signal) 5 t9 Ready signal response delay time (referenced to the write signal) t10 Ready signal release delay time (referenced to the write signal) t11 Write signal negate setup time (referenced to CLK) 5 ns t12 Write signal negate hold time (referenced to CLK) 15 ns ns T + t1 + 24 ns t11 + 32 ns t13 Data setup time (referenced to the ready signal) 60 ns t14 Data hold time (referenced to the ready signal) 20 ns Clock period 60 ns T No. 4909-12/13 LC8220 Hardware Reset Timing Hardware Reset Timing Item Minimum Maximum Unit t1 Reset signal pulse width 2T ns t2 LSI access disabled time 5T ns T Clock period 60 ns ■ No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. ■ Anyone purchasing any products described or contained herein for an above-mentioned use shall: ➀ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: ➁ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. ■ Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of December, 1997. Specifications and information herein are subject to change without notice. No. 4909-13/13