LMH0303 www.ti.com SNLS285G – APRIL 2008 – REVISED APRIL 2013 3 Gbps HD/SD SDI Cable Driver with Cable Detect Check for Samples: LMH0303 FEATURES DESCRIPTION • The LMH0303 3 Gbps HD/SD SDI Cable Driver with Cable Detect is designed for use in SMPTE 424M, SMPTE 292M, SMPTE 344M, and SMPTE 259M serial digital video applications. The LMH0303 drives 75Ω transmission lines (Belden 1694A, Belden 8281, or equivalent) at data rates up to 2.97 Gbps. 1 2 • • • • • • • • • • • • • • SMPTE 424M, SMPTE 292M, SMPTE 344M, and SMPTE 259M Compliant Data Rates to 2.97 Gbps Supports DVB-ASI at 270 Mbps Cable Detect on Output Loss of Signal Detect at Input Output Driver Power Down Control Typical Power Consumption: 130 mW in SD Mode and 155 mW in HD Mode Power Save Mode Typical Power Consumption: 4 mW Single 3.3V Supply Operation Differential Input 75Ω Differential Output Selectable Slew Rate Industrial Temperature Range: −40°C to +85°C 16-pin WQFN Package Footprint Compatible With the LMH0302 APPLICATIONS • • • The LMH0303 includes intelligent sensing capabilities to improve system diagnostics. The cable detect feature senses near-end termination to determine if a cable is correctly attached to the output BNC. Input loss of signal (LOS) detects the presence of a valid signal at the input of the cable driver. These sensing features may be used to alert the user of a system fault and activate a deep power save mode, reducing the cable driver's power consumption to 4 mW. These features are accessible via an SMBus interface. The LMH0303 provides two selectable slew rates for SMPTE 259M and SMPTE 424M / 292M compliance. The output amplitude is adjustable ±10% in 5 mV steps via the SMBus. The LMH0303 is powered from a single 3.3V supply. Power consumption is typically 130 mW in SD mode and 155 mW in HD mode. The LMH0303 is available in a 16-pin WQFN package. SMPTE 424M, SMPTE 292M, SMPTE 344M, and SMPTE 259M Serial Digital Interfaces Digital Video Routers and Switches Distribution Amplifiers Typical Application SDI In SD/HD LMH0356 3G/HD/SD SDI Reclocker ENABLE SDI Clock or Second Data Output SDI Out LMH0303 3G/HD/SD SDI Cable Driver FAULT SDA SCL SMBus Data SMBus Clock Microcontroller or FPGA 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2013, Texas Instruments Incorporated LMH0303 SNLS285G – APRIL 2008 – REVISED APRIL 2013 www.ti.com VEE 3 RREF 4 NC NC FAULT 13 LMH0303 (top view) 5 6 7 8 SCL 2 14 SDA SDI 15 ENABLE 1 16 RSTI SDI RSTO Connection Diagram 12 SDO 11 SDO 10 SD/HD 9 VCC The exposed die attach pad is a negative electrical terminal for this device. It should be connected to the negative power supply voltage. Figure 1. 16-Pin WQFN Package Number RUM PIN DESCRIPTIONS Pin Description 1 SDI Serial data true input. 2 SDI Serial data complement input. 3 VEE Negative power supply (ground). 4 RREF Bias resistor. Connect a 750Ω resistor to VCC. 5 RSTI Reset input. RSTI has an internal pullup. H = Normal operation. L = Device reset. The device operates with default register settings. Forcing RSTI low also forces RSTO low. 6 ENABLE Output driver enable. ENABLE has an internal pullup. H = Normal operation. L = Output driver powered off. 7 SDA SMBus bidirectional data pin. When functioning as an output, it is open drain. This pin requires an external pullup. 8 SCL SMBus clock input. SCL is input only. This pin requires an external pullup. 9 VCC Positive power supply (+3.3V). 10 SD/HD Output slew rate control. SD/HD has an internal pulldown. H = Output rise/fall time complies with SMPTE 259M. L = Output rise/fall time complies with SMPTE 424M / 292M. 11 SDO Serial data complement output. 12 SDO Serial data true output. 13 FAULT Fault open drain output flag. Requires external pullup resistor and may be wire ORed with multiple cable drivers. H = Normal operation. L = Loss of signal or termination fault for any output. 14 NC No connect. Not bonded internally. 15 NC No connect. Not bonded internally. 16 RSTO Reset output. RSTO is automatically set to 1 when register 0 is written. It can be reset back to zero by forcing RSTI to zero to reset the device. Used to daisy chain multiple cable drivers on the same SMBus. VEE Connect exposed DAP to negative power supply (ground). DAP 2 Name Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0303 LMH0303 www.ti.com SNLS285G – APRIL 2008 – REVISED APRIL 2013 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) −0.5V to 3.6V Supply Voltage −0.3V to VCC+0.3V Input Voltage (all inputs) Output Current 28 mA −65°C to +150°C Storage Temperature Range Junction Temperature +125°C Lead Temperature (Soldering 4 Sec) +260°C Package Thermal Resistance ESD Rating θJA 16-pin WQFN +43°C/W θJC 16-pin WQFN +7°C/W HBM 8 kV MM 400V CDM (1) 2 kV Absolute Maximum Ratings are those parameter values beyond which the life and operation of the device cannot be ensured. The stating herein of these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of Electrical Characteristics specifies acceptable device operating conditions. Recommended Operating Conditions Supply Voltage (VCC – VEE) 3.3V ±5% −40°C to +85°C Operating Free Air Temperature (TA) Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0303 3 LMH0303 SNLS285G – APRIL 2008 – REVISED APRIL 2013 www.ti.com DC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1) (2). Symbol Parameter VCMIN Input Common Mode Voltage VSDI Input Voltage Swing VCMOUT Output Common Mode Voltage VSDO Output Voltage Swing VIH Input Voltage High Level VIL InputVoltage Low Level ICC Supply Current Conditions Reference SDI, SDI Differential Min Typ 1.6 + VSDI/2 100 SDO, SDO Single-ended, 75Ω load, RREF = 750Ω 1% Units VCC – VSDI/2 V 2200 mVP−P VCC – VSDO 720 SD/HD, ENABLE Max 800 V 880 mVP-P 2.0 V 0.8 V 47 57 mA SD/HD = 1, SDO/SDO enabled 40 47 mA SDO/SDO disabled 1.3 2.5 mA 0.8 V VSDD V SD/HD = 0, SDO/SDO enabled SMBus DC Specifications VSIL Data, Clock Input Low Voltage VSIH Data, Clock Input High Voltage ISPULLUP Current through pullup resistor or current source VSDD Nominal Bus Voltage ISLEAKB Input Leakage per bus segment ISLEAKP Input Leakage per pin CSI Capacitance for SDA and SCL (1) (2) (3) (4) 4 2.1 VOL = 0.4 V (3) (3) (4) 4 mA 3.0 3.6 V −200 200 µA −10 10 µA 10 pF Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to VEE = 0 Volts. Typical values are stated for VCC = +3.3V and TA = +25°C. Recommended value — Parameter not tested. Recommended maximum capacitive load per bus segment is 400 pF. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0303 LMH0303 www.ti.com SNLS285G – APRIL 2008 – REVISED APRIL 2013 AC Electrical Characteristics Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (1). Symbol Parameter DRSDI Input Data Rate tjit Additive Jitter tr,tf Conditions Reference Min SDI, SDI 2.97 Gbps Output Rise Time, Fall Time SDO, SDO Mismatch in Rise/Fall Time Duty Cycle Distortion RLSDO Output Return Loss Units 2970 Mbps psP-P 1.485 Gbps 18 psP-P 270 Mbps 15 psP-P SD/HD = 0, 20% – 80%, 130 ps 800 ps SD/HD = 0 30 ps SD/HD = 1 50 ps SD/HD = 0, 2.97 Gbps (2) 27 ps SD/HD = 0, 1.485 Gbps (2) 30 ps SD/HD = 1 Output Overshoot Max 20 90 SD/HD = 1, 20% – 80% tOS Typ 400 (2) 100 ps SD/HD = 0 (2) 10 % SD/HD = 1 (2) 8 % 5 MHz - 1.5 GHz (3) 15 dB 1.5 GHz - 3.0 GHz (3) 10 dB SMBus AC Specifications fSMB Bus Operating Frequency 10 100 kHz tBUF Bus free time between Stop and Start Condition 4.7 µs tHD:STA Hold time after (repeated) Start Condition. After this period, the first clock is generated. 4.0 µs 4.7 µs At ISPULLUP = MAX tSU:STA Repeated Start Condition setup time tSU:STO Stop Condition setup time 4.0 µs tHD:DAT Data hold time 300 ns tSU:DAT Data setup time 250 ns tLOW Clock low period 4.7 µs tHIGH Clock high period 4.0 50 µs tF Clock/Data Fall Time 300 ns tR Clock/Data Rise Time 1000 ns tPOR Time in which device must be operational after power on 500 ms (1) (2) (3) Typical values are stated for VCC = +3.3V and TA = +25°C. Specification is ensured by characterization. Output return loss is dependent on board design. The LMH0303 meets this specification on the SD303 evaluation board. TIMING DIAGRAM tLOW tR tHIGH SCL tHD:STA tBUF tHD:DAT tF tSU:STA tSU:DAT tSU:STO SDA SP ST ST SP Figure 2. SMBus Timing Parameters Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0303 5 LMH0303 SNLS285G – APRIL 2008 – REVISED APRIL 2013 www.ti.com DEVICE OPERATION INPUT INTERFACING The LMH0303 accepts either differential or single-ended input. For single-ended operation, the unused input must be properly terminated. OUTPUT INTERFACING The LMH0303 uses current mode outputs. Single-ended output levels are 800 mVP-P into 75Ω AC-coupled coaxial cable with an RREF resistor of 750Ω. The RREF resistor is connected between the RREF pin and VCC. The only resistor value that should be used for RREF is 750Ω. The RREF resistor should be placed as close as possible to the RREF pin. In addition, the copper in the plane layers below the RREF network should be removed to minimize parasitic capacitance. OUTPUT SLEW RATE CONTROL The LMH0303 output rise and fall times are selectable for either SMPTE 259M or SMPTE 424M / 292M compliance via the SD/HD pin. For slower rise and fall times, or SMPTE 259M compliance, SD/HD is set high. For faster rise and fall times, or SMPTE 424M and SMPTE 292M compliance, SD/HD is set low. SD/HD may also be controlled using the SMBus, provided the SD/HD pin is held low. SD/HD has an internal pulldown. OUTPUT ENABLE The SDO/SDO output driver can be enabled or disabled with the ENABLE pin. When set low, the output driver is powered off and the LMH0303 enters a deep power save mode. ENABLE has an internal pullup. INPUT LOS OF SIGNAL DETECTION (LOS) The LMH0303 detects when the input signal does not have a video-like pattern. Self oscillation and low levels of noise are rejected. This loss of signal detect allows a very sensitive input stage that is robust against coupled noise without any degradation of jitter performance. Via the SMBus, the loss of signal detect can either add an input offset or mute the outputs. An offset is added by default. Additionally, the loss of signal detect can be linked to the ENABLE functionality so that when the LOS goes low, ENABLE will also go low. OUTPUT CABLE DETECTION The LMH0303 detects when an output is locally terminated. When a video signal (or AC test signal) is present on SDI, the device senses the SDO and SDO amplitudes. If the output is not properly terminated (via a terminated cable or local termination), the amplitude will be higher than expected, and the Termination Fault signal is asserted. The Termination Fault signal is de-asserted when the proper termination is applied. This feature allows the system designer the flexibility to react to cable attachment and removal. Note that a long length of cable will look like a proper termination at the device output. The cable driver must be enabled for the termination detection to operate. If the Termination Fault will be used to power down the LMH0303, then periodic polling (enabling) is recommended to monitor the output termination. For example, when a Fault condition is triggered, ENABLE can be driven low to power down the device. The LMH0303 should be re-enabled periodically to check the status of the output termination. The LMH0303 needs to be powered on for roughly 4 ms for Termination Fault detection to work. SMBus Interface The System Management Bus (SMBus) is a two-wire interface designed for the communication between various system component chips. By accessing the control functions of the circuit via the SMBus, pincount is kept to a minimum while allowing a maximum amount of versatility. The LMH0303 has several internal configuration registers which may be accessed via the SMBus. The 7-bit default address for the LMH0303 is 17h. The LSB is set to 0b for a WRITE and 1b for a READ, so the 8-bit default address for a WRITE is 2Eh and the 8-bit default address for a READ is 2Fh. The SMBus address may be dynamically changed. 6 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0303 LMH0303 www.ti.com SNLS285G – APRIL 2008 – REVISED APRIL 2013 In applications where there might be several LMH0303s, the SDA, SCL, and FAULT pins can be shared. The SCL, SDA, and FAULT pins are open drain and require external pullup resistors. Multiple LMH0303s may have the FAULT pin wire ORed. This signal becomes active when either loss of signal is detected or any termination faults are detected. The registers may be read in order to determine the cause. Additionally, each signal can be masked from the FAULT pin. TRANSFER OF DATA VIA THE SMBus During normal operation the data on SDA must be stable during the time when SCL is High. There are three unique states for the SMBus: START: A High-to-Low transition on SDA while SCL is High indicates a message START condition. STOP: A Low-to-High transition on SDA while SCL is High indicates a message STOP condition. IDLE: If SCL and SDA are both High for a time exceeding tBUF from the last detected STOP condition or if they are High for a total exceeding the maximum specification for tHIGH then the bus will transfer to the IDLE state. SMBus TRANSACTIONS The device supports WRITE and READ transactions. See Table 1 for register address, type (Read/Write, Read Only), default value and function information. WRITING A REGISTER To 1. 2. 3. 4. 5. 6. 7. write a register, the following protocol is used (see SMBus 2.0 specification). The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE. The Device (Slave) drives the ACK bit (“0”). The Host drives the 8-bit Register Address. The Device drives an ACK bit (“0”). The Host drives the 8-bit data byte. The Device drives an ACK bit (“0”). The Host drives a STOP condition. The WRITE transaction is completed, the bus goes IDLE and communication with other SMBus devices may now occur. READING A REGISTER To read a register, the following protocol is used (see SMBus 2.0 specification). 1. The Host drives a START condition, the 7-bit SMBus address, and a “0” indicating a WRITE. 2. The Device (Slave) drives the ACK bit (“0”). 3. The Host drives the 8-bit Register Address. 4. The Device drives an ACK bit (“0”). 5. The Host drives a START condition. 6. The Host drives the 7-bit SMBus Address, and a “1” indicating a READ. 7. The Device drives an ACK bit “0”. 8. The Device drives the 8-bit data value (register contents). 9. The Host drives a NACK bit “1”indicating end of the READ transfer. 10. The Host drives a STOP condition. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0303 7 LMH0303 SNLS285G – APRIL 2008 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION Figure 3 shows the application circuit for the LMH0303. VCC VCC 10 k: FAULT 75: 0.1 PF 75: RSTO 13 FAULT 14 15 SD/HD 4.7 PF Coaxial Cable 75: 4.7 PF Coaxial Cable 12 11 10 75: 75: 6.8 nH 9 DAP RSTI 5 VCC SCL RREF VCC 75: 8 4 LMH0303 VEE SDA 3 SDO 7 0.1 PF SDI ENABLE 2 SDO SDI 6 1 49.9: Differential Input NC RSTO 49.9: NC 16 6.8 nH 750: RSTI VCC ENABLE SDA SCL VCC 0.1 PF 10 k: 10 k: SD/HD Figure 3. Application Circuit COMMUNICATING WITH MULTIPLE LMH0303 CABLE DRIVERS VIA THE SMBus A common application for the LMH0303 will utilize multiple cable driver devices. Even though the LMH0303 devices all have the same default SMBus device ID (address), it is still possible for them share the SMBus signals as shown in Figure 4. A third signal is required from the host to the first device. This signal acts as a “Enable / Reset” signal. Additional LMH0303s are controlled from the upstream device. In this control scheme, multiple LMH0303s may be controlled via the two-wire SMBus and the use of one GPO (General Purpose Output) signal. Other SMBus devices may also be connected to the two wires, assuming they have their own unique SMBus addresses. 8 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0303 LMH0303 www.ti.com SNLS285G – APRIL 2008 – REVISED APRIL 2013 3.3V RSTO RSTI RSTO SDA RSTI LMH0303 #N SCL RSTO SCL GPO SCL LVCMOS GPIO SMBus Interface RSTI SDA Host (e.g. FPGA) LMH0303 #2 SDA LMH0303 #1 SCL SDA Figure 4. SMBus Configuration for Multiple LMH0303 Cable Drivers The RSTI pin of the first device is controlled by the system with a GPO pin from the host. The first LMH0303 RSTO pin is then daisy chained to the next device's RSTI pin. That device’s RSTO pin is connected to the next device and so on. The procedure at initialization is to: 1. Hold the host GPO pin Low in RESET, to the first device. RSTO output default is also Low which holds the next device in RESET in the chain. 2. Raise the host GPO signal to LMH0303 #1 RSTI input pin. 3. Write to Address 8’h2E (7’h17) Register 0 with the new address value (e.g. 8’h2C (7’h16). 4. Upon writing Register 0 in LMH0303 #1, its RSTO signal will switch High. Its new address is 8’h2C (7’h16), and the next LMH0303 in the chain will now respond to the default address of 8’h2E (7’h17). 5. The process is repeated until all LMH0303 devices have a unique address loaded. 6. Direct SMBus writes and reads may now take place between the host and any addressed device. The 7-bit address field allows for 128 unique addresses. The above procedure allows for the reprogramming of the LMH0303 devices such that multiple devices may share the two-wire SMBus. Make sure all devices on the bus have unique device IDs. If power is toggled to the system, the SMBus address routine needs to be repeated. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0303 9 LMH0303 SNLS285G – APRIL 2008 – REVISED APRIL 2013 www.ti.com SMBUS REGISTERS Table 1. SMBus Registers Address R/W Name Bits Field Default Description 00h R/W ID 7:1 DEVID 0010111 Device ID. Writing this register will force the RSTO pin high. Further accesses to the device must use this 7-bit address. 0 RSVD 0 01h R STATUS 7:3 RSVD 00000 02h 10 R/W MASK Reserved as 0. Always write 0 to this bit. Reserved. 2 TFN 0 Termination Fault for SDI. 0: No Termination Fault Detected. 1: Termination Fault Detected. 1 TFP 0 Termination Fault for SDI. 0: No Termination Fault Detected. 1: Termination Fault Detected. 0 LOS 0 Loss Of Signal (LOS) detect at input. 0: No Signal Detected. 1: Signal Detected. 7 SD 0 SD Rate select bit. If the SD/HD pin is set to VCC, it overrides this bit. With the SD/HD pin set to ground, this bit selects the output edge rate as follows: 0: HD edge rate. 1: SD edge rate. 6 RSVD 0 Reserved as 0. Always write 0 to this bit. 5 PD 0 Power Down for SDO output stage. If the ENABLE pin is set to ground, it overrides this bit. With the ENABLE pin set to VCC, PD functions as follows: 0: SDO active. 1: SDO powered down. 4:3 RSVD 00 Reserved as 00. Always write 00 to these bits. 2 MTFN 0 Mask TFN from affecting FAULT pin. 0: TFN=1 will cause FAULT to be 0. 1: TFN=1 will not affect FAULT; the condition is masked off. 1 MTFP 0 Mask TFP from affecting FAULT pin. 0: TFP=1 will cause FAULT to be 0. 1: TFP=1 will not affect FAULT; the condition is masked off. 0 MLOS 0 Mask LOS from affecting FAULT pin. 0: LOS=0 will cause FAULT to be 0. 1: LOS=0 will not affect FAULT; the condition is masked off. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0303 LMH0303 www.ti.com SNLS285G – APRIL 2008 – REVISED APRIL 2013 Table 1. SMBus Registers (continued) Address R/W Name 03h R/W DIRECTION 04h R/W OUTPUT Bits Field Default Description 7 HDTFThreshLSB 1 Least Significant Bit for HDTFThresh detection threshold. Combines with HDTFThresh bits in register 04h. 6 SDTFThreshLSB 1 Least Significant Bit for SDTFThresh detection threshold. Combines with SDTFThresh bits in register 05h. 5:3 RSVD 000 2 DTFN 0 Direction of TFN that affects FAULT pin (when not masked). 0: TFN=1 will cause FAULT to be 0 (when the condition is not masked off). 1: TFN=0 will cause FAULT to be 0 (when the condition is not masked off). 1 DTFP 0 Direction of TFP that affects FAULT pin (when not masked). 0: TFP=1 will cause FAULT to be 0 (when the condition is not masked off). 1: TFP=0 will cause FAULT to be 0 (when the condition is not masked off). 0 DLOS 0 Direction of LOS that affects FAULT pin (when not masked). 0: LOS=0 will cause FAULT to be 0 (when the condition is not masked off). 1: LOS=1 will cause FAULT to be 0 (when the condition is not masked off). 100 Sets the Termination Fault threshold for SDO, when SD is set to HD rates (0). Combines with HDTFThreshLSB in register 03h (default for combined value is 1001). 10000 SDO output amplitude in roughly 5 mV steps. 7:5 HDTFThresh 4:0 AMP Reserved as 000. Always write 000 to these bits. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0303 11 LMH0303 SNLS285G – APRIL 2008 – REVISED APRIL 2013 www.ti.com Table 1. SMBus Registers (continued) 12 Address R/W Name 05h R/W OUTPUTCTRL Bits Field Default 7 RSVD 0 Reserved as 0. Always write 0 to this bit. 6 FLOSOF 0 Force LOS to always OFF in regard to its effect on the output signal. This forces the device into either the mute or “add offset” state. The LOS bit in register 01h still reflects the correct state of LOS. 0: LOS operates normally, muting or adding offset as specified by the MUTE bit. 1: Muting or adding offset is always in place as specified by the MUTE bit. 5 FLOSON 0 Force LOS to always ON in regard to its effect on the output signal. This prevents the device from muting or adding offset. The LOS bit in register 01h still reflects the correct state of LOS. 0: LOS operates normally, muting or adding offset as specified in the MUTE bit. 1: Muting or adding offset never occurs. 4 LOSEN 0 Configures LOS to be combined with the ENABLE functionality. 0: Only the PD bit and ENABLE pin affect the power down state of the output drivers. 1: If the ENABLE pin is set to ground, it powers down the output drivers regardless of the state of LOS or the PD bit. With the ENABLE pin set to VCC, LOS=0 will power down the output drivers, and LOS=1 will leave the power down state dependent on the PD bit. 3 MUTE 0 Selects whether the device will MUTE when loss of signal is detected or add an offset to prevent self oscillation. When an input signal is detected (LOS=1), the device will operate normally. 0: Loss of signal will force a small offset to prevent self oscillation. 1: Loss of signal will force the channel to MUTE. 010 Sets the Termination Fault threshold for SDO, when SD is set to SD rates (1). Combines with SDTFThreshLSB in register 03h (default for combined value is 0101). 2:0 SDTFThresh Description 06h R/W RSVD 7:0 RSVD 00000000 Reserved as 00000000. Always write 00000000 to these bits. 07h R/W RSVD 7:0 RSVD 00000000 Reserved as 00000000. Always write 00000000 to these bits. 08h R/W TEST 7:5 CMPCMD 4:0 RSVD 000 00000 Submit Documentation Feedback Compare command. Determines whether the peak value or the current value of the Termination Fault counters is read in registers 0Ah and 0Bh. 000: Resets compare value to 00; registers 0Ah and 0Bh show current counter values. Sets detection to look for MAX peak values. 001: Capture counter 0. Register 0Ah shows peak value. 010: Capture counter 1. Register 0Bh shows peak value. 011, 100: Reserved. 101: Resets compare value to 1Fh. Sets detection to look for MIN peak values. 110, 111: Reserved. Reserved as 00000. Always write 00000 to these bits. Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0303 LMH0303 www.ti.com SNLS285G – APRIL 2008 – REVISED APRIL 2013 Table 1. SMBus Registers (continued) Address R/W 09h R 0Ah 0Bh R R Name Bits Field Default REV 7:5 RSVD 000 Reserved. 4:3 DIREV 10 Die Revision. 2:0 PARTID 011 Part Identifier. Note that single output devices (LMH0303) have the LSB=1. Dual output devices (LMH0307) have the LSB=0. 7:5 RSVD 000 Reserved. 4:0 TFPCOUNT 7:5 RSVD 4:0 TFNCOUNT TFPCOUNT TFNCOUNT 00000 000 00000 Description This is either the current value of TFP Counter, or the peak value of the counter, depending on CMPCMD in register 08h. Reserved. This is either the current value of TFN Counter, or the peak value of the counter, depending on CMPCMD in register 08h. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0303 13 LMH0303 SNLS285G – APRIL 2008 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision F (April 2013) to Revision G • 14 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 13 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH0303 PACKAGE OPTION ADDENDUM www.ti.com 15-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LMH0303SQ/NOPB ACTIVE WQFN RUM 16 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 L0303 LMH0303SQE/NOPB ACTIVE WQFN RUM 16 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 L0303 LMH0303SQX/NOPB ACTIVE WQFN RUM 16 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 L0303 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMH0303SQ/NOPB WQFN RUM 16 LMH0303SQE/NOPB WQFN RUM LMH0303SQX/NOPB WQFN RUM SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 16 250 178.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 16 4500 330.0 12.4 4.3 4.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 24-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH0303SQ/NOPB WQFN RUM 16 1000 213.0 191.0 55.0 LMH0303SQE/NOPB WQFN RUM 16 250 213.0 191.0 55.0 LMH0303SQX/NOPB WQFN RUM 16 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA RUM0016A SQB16A (Rev A) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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