LT3070 5A, Low Noise, Programmable Output, 85mV Dropout Linear Regulator Features n n n n n n n n n n n n n n n n Description Output Current: 5A Dropout Voltage: 85mV Typical Digitally Programmable VOUT : 0.8V to 1.8V Digital Output Margining: ±1%, ±3% or ±5% Low Output Noise: 25µVRMS (10Hz to 100kHz) Parallel Multiple Devices for 10A or More Precision Current Limit: ±20% ±1% Accuracy Over Line, Load and Temperature Stable with Low ESR Ceramic Output Capacitors (15µF Minimum) High Frequency PSRR: 30dB at 1MHz Enable Function Turns Output On/Off VIOC Pin Controls Buck Converter to Maintain Low Power Dissipation and Optimize Efficiency PWRGD/UVLO/Thermal Shutdown Flag Current Limit with Foldback Protection Thermal Shutdown 28-Lead (4mm × 5mm × 0.75mm) QFN Package Applications n n n n FPGA and DSP Supplies ASIC and Microprocessor Supplies Servers and Storage Devices Post Buck Regulation and Supply Isolation The LT®3070 is a low voltage, UltraFast™ transient response linear regulator. The device supplies up to 5A of output current with a typical dropout voltage of 85mV. A 0.01µF reference bypass capacitor decreases output voltage noise to 25µVRMS. The LT3070’s high bandwidth permits the use of low ESR ceramic capacitors, saving bulk capacitance and cost. The LT3070’s features make it ideal for high performance FPGAs, microprocessors or sensitive communication supply applications. Output voltage is digitally selectable in 50mV increments over a 0.8V to 1.8V range. A margining function allows the user to adjust system output voltage in increments of ±1%, ±3% or ±5%. The IC incorporates a unique tracking function to control a buck regulator powering the LT3070’s input. This tracking function drives the buck regulator to maintain the LT3070’s input voltage to VOUT + 300mV, minimizing power dissipation. Internal protection includes UVLO, reverse-current protection, precision current limiting with power foldback and thermal shutdown. The LT3070 regulator is available in a thermally enhanced 28-lead, 4mm × 5mm QFN package. L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and UltraFast and VLDO are trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. Patents pending. Typical Application Dropout Voltage 0.9V, 5A Regulator VIN 1.2V 50k 150 2.2µF IN 330µF BIAS PWRGD EN VO0 SENSE LT3070 OUT VO1 VO2 MARGSEL 2.2µF* 1nF REF/BYP GND 4.7µF* *X5R OR X7R CAPACITORS MARGTOL VIOC VIN = VOUT(NOMINAL) PWRGD 0.01µF 3070 TA01a VOUT 0.9V 5A 10µF* DROPOUT VOLTAGE (mV) VBIAS 2.2V TO 3.6V 120 90 VOUT = 1.8V VBIAS = 3.3V 60 VOUT = 0.8V VBIAS = 2.5V 30 0 0 1 3 4 2 OUTPUT CURRENT (A) 5 3070 TA01b 3070fa LT3070 VO0 VO1 VO2 GND BIAS TOP VIEW EN 28 27 26 25 24 23 VIOC 1 22 MARGTOL PWRGD 2 21 MARGSEL REF/BYP 3 20 GND GND 4 19 SENSE 29 GND IN 5 18 OUT IN 6 17 OUT IN 7 16 OUT IN 8 15 OUT GND GND GND 9 10 11 12 13 14 GND IN, OUT...................................................... –0.3V to 3.3V BIAS.............................................................. –0.3V to 4V VO2, VO1, VO0 Inputs..................................... –0.3V to 4V MARGSEL, MARGTOL Input......................... –0.3V to 4V EN Input........................................................ –0.3V to 4V SENSE Input................................................. –0.3V to 4V VIOC, PWRGD Outputs................................. –0.3V to 4V REF/BYP Output............................................ –0.3V to 4V Output Short-Circuit Duration……...................Indefinite Operating Junction Temperature (Note 2) LT3070E/LT3070I.............................. –40°C to 125°C LT3070MP.......................................... –55°C to 125°C Storage Temperature Range................... –65°C to 150°C Pin Configuration GND (Note 1) GND Absolute Maximum Ratings UFD PACKAGE 28-LEAD (4mm s 5mm) PLASTIC QFN TJMAX = 125°C, θJA = 30°C/W TO 35°C/W EXPOSED PAD (PIN 29) IS GND, MUST BE SOLDERED TO PCB Order Information LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3070EUFD#PBF LT3070EUFD#TRPBF 3070 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LT3070IUFD#PBF LT3070IUFD#TRPBF 3070 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LT3070MPUFD#PBF LT3070MPUFD#TRPBF 3070 28-Lead (4mm × 5mm) Plastic QFN –55°C to 125°C LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LT3070EUFD LT3070EUFD#TR 3070 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LT3070IUFD LT3070IUFD#TR 3070 28-Lead (4mm × 5mm) Plastic QFN –40°C to 125°C LT3070MPUFD LT3070MPUFD#TR 3070 28-Lead (4mm × 5mm) Plastic QFN –55°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ 3070fa LT3070 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless otherwise noted. PARAMETER CONDITIONS IN Pin Voltage Range VIN ≥ VOUT + 150mV, IOUT= 5A MIN l TYP 0.95 2.2 UNITS 3.0 V 3.6 V Regulated Output Voltage VOUT = 0.8V, 10mA ≤ IOUT ≤ 5A, 1.05V ≤ VIN ≤ 1.25V VOUT = 0.9V, 10mA ≤ IOUT ≤ 5A, 1.15V ≤ VIN ≤ 1.35V VOUT = 1V, 10mA ≤ IOUT ≤ 5A, 1.25V ≤ VIN ≤ 1.45V VOUT = 1.1V, 10mA ≤ IOUT ≤ 5A, 1.35V ≤ VIN ≤ 1.55V VOUT = 1.2V, 10mA ≤ IOUT ≤ 5A, 1.45V ≤ VIN ≤ 1.65V, VBIAS = 3.3V VOUT = 1.5V, 10mA ≤ IOUT ≤ 5A, 1.75V ≤ VIN ≤ 1.95V, VBIAS = 3.3V VOUT = 1.8V, 10mA ≤ IOUT ≤ 5A, 2.05V ≤ VIN ≤ 2.25V, VBIAS = 3.3V l l l l l l l 0.792 0.891 0.990 1.089 1.188 1.485 1.782 0.800 0.900 1.000 1.100 1.200 1.500 1.800 0.808 0.909 1.010 1.111 1.212 1.515 1.818 V V V V V V V Regulated Output Voltage Margining (Note 3) MARGTOL = 0V, MARGSEL = VBIAS MARGTOL = 0V, MARGSEL = 0V, IOUT = 10mA l l 0.8 –1.2 1 –1 1.2 –0.8 % % MARGTOL = FLOAT, MARGSEL = VBIAS MARGTOL = FLOAT, MARGSEL = 0V, IOUT = 10mA l l 2.7 –3.3 3 –3 3.3 –2.7 % % MARGTOL = VBIAS, MARGSEL= VBIAS MARGTOL = VBIAS, MARGSEL = 0V, IOUT = 10mA l l 4.6 –5.4 5 –5 5.4 –4.6 % % Line Regulation to VIN VOUT = 0.8V, ∆VIN = 1.05V to 2.7V, VBIAS = 3.3V, IOUT = 10mA VOUT = 1.8V, ∆VIN = 2.05V to 2.7V, VBIAS = 3.3V, IOUT = 10mA l l 1.0 1.0 mV mV Line Regulation to VBIAS VOUT = 0.8V, ∆VBIAS = 2.2V to 3.6V, VIN = 1.1V, IOUT = 10mA VOUT = 1.8V, ∆VBIAS = 3.25V to 3.6V, VIN = 2.1V, IOUT = 10mA l l 2.0 1.0 mV mV Load Regulation, ∆IOUT = 10mA to 5A VBIAS = 2.5V, VIN = 1.05V, VOUT = 0.8V –1.5 –3.0 –5.5 mV mV –2 –4.0 –7.5 mV mV –2 –4.0 –7.5 mV mV –2.5 –5.0 –9.0 mV mV –3 –7.0 –13 mV mV 20 35 mV 50 65 85 mV mV 85 120 150 mV mV BIAS Pin Voltage Range (Note 3) l MAX l VBIAS = 2.5V, VIN = 1.25V, VOUT = 1.0V l VBIAS = 3.3V, VIN = 1.45V, VOUT = 1.2V l VBIAS = 3.3V, VIN = 1.75V, VOUT = 1.5V l VBIAS = 3.3V, VIN = 2.05V, VOUT = 1.8V l Dropout Voltage, VIN = VOUT(NOMINAL) (Note 6) IOUT = 1A, VOUT = 1V l IOUT = 2.5A, VOUT = 1V l IOUT = 5A, VOUT = 1V l SENSE Pin Current VIN = 1.1V, VSENSE = 0.8V VBIAS = 3.3V, VIN = 2.1V, VSENSE = 1.8V l l 35 200 50 300 65 400 µA µA Ground Pin Current, VIN = 1.3V, VOUT = 1V IOUT = 10mA IOUT = 5A l l 0.65 0.9 1.1 1.35 1.8 2.3 mA mA 3070fa LT3070 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless otherwise noted. PARAMETER CONDITIONS MIN TYP MAX UNITS BIAS Pin Current in Nap Mode EN = Low (After POR Completed) l 120 200 320 µA BIAS Pin Current, VIN = 1.3V, VOUT = 1V IOUT = 10mA IOUT = 100mA IOUT = 500mA IOUT = 1A IOUT = 2.5A IOUT = 5A l l l l l l 0.75 1.25 2.0 2.6 3.5 4.5 1.08 1.8 3.0 3.8 5.2 6.9 1.5 2.4 4.0 5.0 7.0 10.0 mA mA mA mA mA mA Current Limit (Note 5) VIN – VOUT < 0.3V, VBIAS = 3.3V VIN – VOUT = 1.0V, VBIAS = 3.3V VIN – VOUT = 1.7V, VBIAS = 3.3V l l l 5.1 3.2 1.2 6.4 4.5 2.5 7.7 5.8 4.3 A A A Reverse Output Current (Note 8) VIN = 0V, VOUT = 1.8V l 300 450 µA PWRGD VOUT Threshold Percentage of VOUT(NOMINAL), VOUT Rising Percentage of VOUT(NOMINAL), VOUT Falling l l 90 85 93 88 % % PWRGD VOL IPWRGD = 200µA (Fault Condition) l 50 150 mV VBIAS Undervoltage Lockout VBIAS Rising VBIAS Falling l l 1.1 0.9 1.55 1.4 2.1 1.7 V V VIN-VOUT Servo Voltage by VIOC 87 82 l 250 300 350 mV VIOC Output Current VIN = VOUT(NOMINAL) + 150mV, Sourcing Out of the Pin VIN = VOUT(NOMINAL) + 450mV, Sinking Into the Pin l l 160 170 235 255 310 340 µA µA VIL Input Threshold (Logic-0 State), VO2, VO1, VO0, MARGSEL, MARGTOL Input Falling l 0.25 V VBIAS – 0.9 V VIZ Input Range (Logic-Z State), VO2, VO1, VO0, MARGSEL, MARGTOL VIH Input Threshold (Logic-1 State), VO2, VO1, VO0, MARGSEL, MARGTOL Input Rising l 0.75 l VBIAS – 0.25 Input Hysteresis (Both Thresholds), VO2, VO1, VO0, MARGSEL, MARGTOL V 60 mV Input Current High, VO2, VO1, VO0, MARGSEL, MARGTOL VIH = VBIAS = 2.5V, Current Flows Into Pin l 25 40 µA Input Current Low, VO2, VO1, VO0, MARGSEL, MARGTOL VIL = 0V, VBIAS = 2.5V, Current Flows Out of Pin l 25 40 µA EN Pin Threshold VOUT = Off to On VOUT = On to Off l l 0.9 1.4 V V EN Pin Logic High Current VEN = VBIAS = 2.5V l 2.5 6.5 µA EN Pin Logic Low Current VEN = 0V l 0.1 µA 4.0 3070fa LT3070 Electrical Characteristics The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. COUT = 15µF (Note 9), VIN = VOUT + 0.3V (Note 5), VBIAS = 2.5V unless otherwise noted. PARAMETER CONDITIONS VBIAS Ripple Rejection VBIAS = VOUT + 1.5VAVG, VRIPPLE =0.5VP-P , fRIPPLE = 120Hz, VIN – VOUT = 300mV, IOUT = 2.5A 75 dB VIN Ripple Rejection (Notes 3, 4, 5) VBIAS = 2.5V, VRIPPLE = 50mVP-P , fRIPPLE = 120Hz, VIN – VOUT = 300mV, IOUT = 2.5A 66 dB Reference Voltage Noise (REF/BYP Pin) CREF/BYP = 10nF, BW = 10Hz to 100kHz 10 µVRMS Output Voltage Noise VOUT = 1V, IOUT = 5A, CREF/BYP = 10nF, COUT = 15µF, BW = 10Hz to 100kHz 25 µVRMS Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The LT3070 regulators are tested and specified under pulse load conditions such that TJ ≅ TA. The LT3070E is 100% tested at TA = 25°C. Performance at –40°C and 125°C is assured by design, characterization and correlation with statistical process controls. The LT3070I is guaranteed over the –40°C to 125°C operating junction temperature range. The LT3070MP is 100% tested and guaranteed over the –55°C to 125°C operating junction temperature range. Note 3: To maintain proper performance and regulation, the BIAS supply voltage must be higher than the IN supply voltage. For a given VOUT , the BIAS voltage must satisfy the following conditions: 2.2V ≤ VBIAS ≤ 3.6V and VBIAS ≥ (1.25 • VOUT + 1V). For VOUT ≤ 0.95V, the minimum BIAS voltage is limited to 2.2V. Note 4: Operating conditions are limited by maximum junction temperature. The regulated output voltage specification does not apply for all possible combinations of input voltage and output current. When operating at maximum output current, limit the input voltage range to VIN < VOUT + 500mV. MIN TYP MAX UNITS Note 5: The LT3070 incorporates safe operating area protection circuitry. Current limit decreases as the VIN-VOUT voltage increases. Current limit foldback starts at VIN – VOUT > 500mV. See the Typical Performance Characteristics for a graph of Current Limit vs VIN – VOUT voltage. The current limit foldback feature is independent of the thermal shutdown circuity. Note 6: Dropout voltage, VDO, is the minimum input to output voltage differential at a specified output current. In dropout, the output voltage equals VIN – VDO. Note 7: GND pin current is tested with VIN = VOUT(NOMINAL) + 300mV and a current source load. VIOC is a buffered output determined by the value of VOUT as programmed by the VO2-VO0 pins. VIOC’s output is independent of the margining function. Note 8: Reverse output current is tested with the IN pins grounded and the OUT + SENSE pins forced to the rated output voltage. This is measured as current into the OUT + SENSE pins. Note 9: Frequency Compensation: The LT3070 must be frequency compensated at its OUT pins with a minimum COUT of 15µF configured as a cluster of (15×) 1µF ceramic capacitors or as a graduated cluster of 10µF/4.7µF/2.2µF ceramic capacitors of the same case size. Linear Technology only recommends X5R or X7R dielectric capacitors. 3070fa LT3070 Typical Performance Characteristics Dropout Voltage vs Temperature 30 VIN = VOUT(NOMINAL) TJ = 25°C 25 120 VOUT = 1.8V VBIAS = 3.3V 60 VOUT = 0.8V VBIAS = 2.5V 30 0 VIN = VOUT(NOMINAL) IOUT = 1A 20 15 10 VOUT = 1.8V, VBIAS = 3.3V VOUT = 0.8V, VBIAS = 2.5V VOUT = 1.2V, VBIAS = 3.3V 5 0 1 3 4 2 OUTPUT CURRENT (A) 90 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 5 Dropout Voltage vs Temperature 60 30 VOUT = 1.8V, VBIAS = 3.3V VOUT = 0.8V, VBIAS = 2.5V VOUT = 1.2V, VBIAS = 3.3V 30 20 0.808 160 140 120 100 80 60 40 0 OUT = 1.8V OUT = 1.5V OUT = 0.8V 2.2 2.4 2.6 2.8 3.0 3.2 BIAS VOLTAGE (V) 3.4 1.212 ILOAD = 10mA 0.802 0.800 0.798 0.796 0.794 0.792 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3.6 3070 G06 Output Voltage (1.5V) vs Temperature 1.515 ILOAD = 10mA 1.208 OUTPUT VOLTAGE (V) 1.006 1.002 1.000 0.998 0.996 0.994 ILOAD = 10mA 0.804 Output Voltage (1.2V) vs Temperature 1.004 VOUT = 1.8V, VBIAS = 3.3V VOUT = 0.8V, VBIAS = 2.5V VOUT = 1.2V, VBIAS = 3.3V 3070 G05 Output Voltage (1V) vs Temperature OUTPUT VOLTAGE (V) 40 0.806 3070 G04 1.008 50 Output Voltage (0.8V) vs Temperature Dropout Voltage vs VBIAS 20 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 1.010 60 3070 G03 OUTPUT VOLTAGE (V) 90 70 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) IOUT = 5A 180 TJ = 25°C DROPOUT VOLTAGE (mV) DROPOUT VOLTAGE (mV) 200 VIN = VOUT(NOMINAL) IOUT = 5A 120 80 3070 G02 3070 G01 150 VIN = VOUT(NOMINAL) IOUT = 2.5A 10 ILOAD = 10mA 1.510 OUTPUT VOLTAGE (V) 90 Dropout Voltage vs Temperature 100 DROPOUT VOLTAGE (mV) Dropout Voltage vs IOUT DROPOUT VOLTAGE (mV) DROPOUT VOLTAGE (mV) 150 1.204 1.200 1.196 1.505 1.500 1.495 1.192 1.490 1.188 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 1.485 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 0.992 0.990 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3070 G07 3070 G08 3070 G09 3070fa LT3070 Typical Performance Characteristics Output Voltage (1.8V) vs Temperature GND PIN CURRENT (mA) OUTPUT VOLTAGE (V) 1.806 1.802 1.798 1.794 1.790 2.0 1.5 1.0 VOUT = 1.8V, VBIAS = 3.3V VOUT = 1.2V, VBIAS = 3.3V VOUT = 0.8V, VBIAS = 2.5V 0.5 1.786 1.782 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 0 0 1 10 250 200 150 100 50 2.5 8 7 VOUT = 1.8V VBIAS = 3.3V 6 5 4 VOUT = 0.8V VBIAS = 2.5V 3 2 0 0 1 3 4 2 OUTPUT CURRENT (A) EN Pin Thresholds VBIAS = 2.5V PWRGD TRESHOLD VOLTAGE (V) ENABLE PIN THRESHOLD (V) VBIAS RISING 1.5 1.0 VBIAS FALLING 0.5 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 5 3070 G15 PWRGD Threshold Voltage 1.00 1.6 0.8 2.0 3070 G14 3070 G13 1.0 3070 G12 1 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 1.2 594 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) BIAS Pin Undervoltage Lockout Threshold VIN = VOUT + 300mV TJ = 25°C 9 BIAS PIN CURRENT (mA) BIAS PIN CURRENT (µA) VBIAS = 2.5V 350 VEN = 0V 1.4 598 BIAS Pin Current vs IOUT 400 1.8 600 3070 G11 BIAS Pin Current in Nap Mode 2.0 602 596 5 2 3 4 OUTPUT CURRENT (A) 3070 G10 300 CREF/BYP = 0.01µF 604 REF/BYP VOLTAGE (mV) 2.5 1.810 606 VIN = VOUT + 300mV TJ = 25°C UVLO THRESHOLD VOLTAGE (V) 1.814 3.0 ILOAD = 10mA EN PIN RISING EN PIN FALLING 0.6 0.4 100 VBIAS = 2.5V VOUT = 1V PWRGD VOL VOLTAGE (mV) 1.818 REF/BYP Pin Voltage vs Temperature GND Pin Current vs IOUT 0.95 VOUT RISING 0.90 0.85 VOUT FALLING PWRGD VOL vs Temperature VBIAS = 2.5V IPWRGD = 200µA 80 60 40 20 0.2 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3070 G16 0.80 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3070 G17 0 –75 –50 –25 0 25 50 75 100 125 150 TEMPERATURE (°C) 3070 G50 3070fa LT3070 Typical Performance Characteristics Logic Input Threshold Voltages Logic Low to Hi-Z State Transitions 0.7 0.5 INPUT FALLING LOGIC Hi-Z TO LOW 0.4 0.3 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 2.9 2.8 INPUT RISING LOGIC Hi-Z TO HIGH 2.7 INPUT FALLING LOGIC HIGH TO Hi-Z 2.6 3070 G18 4.0 3.5 3.0 2.5 2.0 1.5 3070 G16 SENSE Pin Current 65 40 VLOGIC = VBIAS = 2.5V CURRENT FLOWS INTO THE PIN 30 25 20 15 10 5 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) VBIAS = 2.5V 35 VLOGIC = 0V CURRENT FLOWS OUT OF THE PIN 30 25 20 15 10 VBIAS = 2.5V 60 VOUT = 0.8V CURRENT FLOWS INTO SENSE 55 50 45 40 35 5 30 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 25 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3070 G21 3070 G23 3070 G22 SENSE Pin Current Current Limit vs Temperature 400 7.50 VBIAS = 3.3V 375 VOUT = 1.8V CURRENT FLOWS INTO SENSE 350 7.25 Current Limit vs VIN – VOUT 8 VIN – VOUT(NOMINAL) = 300mV 300 275 250 6.75 6.50 6.25 6.00 5.75 5.50 225 5.25 200 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3070 G24 CURRENT LIMIT (A) 325 VBIAS = 3.3V TJ = 25°C 7 7.00 CURRENT LIMIT (A) SENSE PIN CURRENT (µA) 4.5 Logic Pin Input Current, Low State LOGIC PIN INPUT CURRENT (µA) LOGIC PIN INPUT CURRENT (µA) 35 5.0 3070 G19 Logic Pin Input Current, High State 40 VEN = VBIAS = 2.5V 5.5 1.0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 2.5 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) SENSE PIN CURRENT (µA) 0.6 INPUT RISING LOGIC LOW TO Hi-Z VBIAS = 3.3V LOGIC Hi-Z TO HIGH THRESHOLD IS RELATIVE TO VBIAS VOLTAGE SEE APPLICATIONS INFORMATION FOR MORE DETAILS EN Pin Logic High Current 6.0 EN PIN LOGIC HIGH CURRENT (µA) 3.0 SEE APPLICATIONS INFORMATION FOR MORE DETAILS LOGIC INPUT THRESHOLD VOLTAGE (V) LOGIC INPUT THRESHOLD VOLTAGE (V) 0.8 Logic Input Threshold Voltages Logic Hi-Z to High State Transitions 6 5 4 3 2 VOUT = 1.8V, VBIAS = 3.3V VOUT = 1.2V, VBIAS = 3.3V VOUT = 0.8V, VBIAS = 2.5V 5.00 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3070 G25 VOUT = 1.8V VOUT = 1.2V VOUT = 0.8V 1 0 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 IN-TO-OUT VOLTAGE DIFFERENTIAL (V) 3070 G26 3070fa LT3070 Typical Performance Characteristics 60 50 40 30 20 VBIAS = 2.5V + 500mVP-P VBIAS = 2.7V + 500mVP-P VBIAS = 3.3V + 500mVP-P 10 0 10 100 70 70 60 50 40 COUT = 117µF COUT = 16.9µF 30 20 VOUT = 1V VIN = 1.3V + 50mVP-P RIPPLE VBIAS = 2.5V IOUT = 1A 10 1k 10k 100k FREQUENCY (Hz) 1M 0 10M 10 100 1k 10k 100k FREQUENCY (Hz) 1M 3070 G27 IOUT = 5A 3.6 VOUT = 1.8V VOUT = 1.2V VOUT = 0.8V 3.4 3.2 3.0 2.8 2.6 2.4 3.2 3.0 0 1 2 4 3 OUTPUT CURRENT (A) BIAS VOLTAGE LINE REGULATION (µV) LOAD REGULATION (mV) 10M IOUT = 5A TJ = 25°C 2.8 2.6 2.4 2.2 1.8 0.7 5 0.9 1.5 1.1 1.3 OUTPUT VOLTAGE (V) 1.7 1.9 3070 G51 Bias Voltage Line Regulation 400 800 3070 G32 1M 3.0 Bias Voltage Line Regulation Load Regulation –10 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 1k 10k 100k FREQUENCY (Hz) 3070 G31 0 VOUT = 0.8V VOUT = 1.2V VOUT = 1.8V 100 2.0 3070 G30 VIN = VOUT(NOMINAL) + 300mV VBIAS = 3.3V $IOUT = 100mA TO 5A 10 3070 G29 3.2 2.4 2.0 –4 VOUT = 1V VIN = 1.3V + 50mVP-P RIPPLE VBIAS = 2.5V IOUT = 5A Minimum BIAS Voltage vs VOUT 2.6 2.0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) –8 20 3.4 2.8 2.2 –2 COUT = 117µF COUT = 16.9µF 30 0 10M VIN = VOUT(NOMINAL) + 300mV $VOUT = –1%, TJ = 25°C VOUT = 1.8V VOUT = 1.5V VOUT = 1.2V VOUT = 0.8V TO 1V 3.4 2.2 –6 40 Minimum BIAS Voltage vs IOUT 3.6 MINIMUM BIAS VOLTAGE (V) MINIMUM BIAS VOLTAGE (V) 3.8 50 3070 G28 Minimum BIAS Voltage vs Temperature 4.0 60 10 MINIMUM BIAS VOLTAGE (V) 70 80 VBIAS = 2.2V TO 3.6V 700 VIN = 1.1V VOUT = 0.8V 600 IOUT = 10mA BIAS VOLTAGE LINE REGULATION (µV) BIAS PIN RIPPLE REJECTION (dB) 80 80 IN PIN RIPPLE REJECTION (dB) VIN = 1.3V VOUT = 1V IOUT = 5A COUT = 10µF + 4.7µF + 2.2µF 90 IN Pin Ripple Rejection IN Pin Ripple Rejection IN PIN RIPPLE REJECTION (dB) BIAS Pin Ripple Rejection 100 500 400 300 200 100 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3070 G33 VBIAS = 3.25V TO 3.6V 300 VIN = 2.1V VOUT = 1.8V 200 IOUT = 10mA 100 0 –100 –200 –300 –400 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3070 G34 3070fa LT3070 Typical Performance Characteristics 200 150 100 50 250 200 150 100 50 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 0 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) Nap Mode Recovery Time vs IOUT 1.0 250 200 150 NOISE SPECTRAL DENSITY (µV/√Hz) NAP MODE RECOVERY TIME (µs) 300 100 50 0 0 1 2 4 3 OUTPUT CURRENT (A) 14 12 10 8 6 4 2 0.1 0.3 0.4 0.2 REF/BYP CAPACITANCE (µF) 0 RMS Output Noise vs Output Current 5 80 VBIAS = 2.5V VOUT = 1V IOUT = 5A COUT = 16.9µF CREF/BYP = 0.01µF 0.1 70 0.01 0.001 VIN = VOUT(NOMINAL) + 300mV VBIAS = 3.3V COUT = 16.9µF 60 50 40 30 20 10 100 10 3070 G38 1k 10k FREQUENCY (Hz) 0.5 3070 G37 Output Noise Spectral Density VBIAS = 3.3V VIN = VOUT(NOM) + 300mV EN = LOW TO HIGH IOUT = 5A (SET BY A RESISTOR LOAD) TJ = 25°C VOUT = 1.8V, COUT = 117µF VOUT = 1.2V, COUT = 117µF VOUT = 0.8V, COUT = 117µF 350 16 3070 G36 3070 G35 400 VBIAS = 2.5V TO 3.3V IOUT = 10mA COUT = 10µF + 4.7µF + 2.2µF TJ = 25°C SEE APPLICATIONS INFORMATION FOR START-UP DETAILS 18 0 OUTPUT NOISE (µVRMS) 250 20 VBIAS = 3.3V VIN = 2.05V TO 2.7V VOUT = 1.8V IOUT = 10mA OUTPUT VOLTAGE START-UP TIME (ms) 300 VBIAS = 3.3V VIN = 1.05V TO 2.7V VOUT = 0.8V IOUT = 10mA INPUT VOLTAGE LINE REGULATION (µV) INPUT VOLTAGE LINE REGULATION (µV) 300 Output Voltage Start-Up Time vs CREF/BYP Input Voltage Line Regulation Input Voltage Line Regulation 100k 0 0.01 VOUT = 1.8V VOUT = 1.2V VOUT = 0.8V 0.1 1 OUTPUT CURRENT (A) 3070 G39 10 3070 G40 Input Voltage Line Transient Response Output Noise (10Hz to 100kHz) VOUT 1mV/DIV VOUT 100µV/DIV VIN 50mV/DIV VOUT = 1V IOUT = 5A COUT = 16.9µF 1ms/DIV 3070 G41 VIN = 1.3V VOUT = 1V IOUT = 5A COUT = 16.9µF 20µs/DIV 3070 G42 3070fa 10 LT3070 Typical Performance Characteristics VIOC Amplifier IN-to-OUT Servo Voltage VOUT 10mV/DIV VBIAS 200mV/DIV VIN = 1.3V VBIAS = 2.5V VOUT = 1V IOUT = 5A COUT = 16.9µF 20µs/DIV 3070 G43 VIOC IN-TO-OUT SERVO VOLTAGE (mV) 350 340 VIOC Amplifier Output Current vs Temperature 300 VBIAS = 2.5V VIOC AMPLIFIER OUTPUT CURRENT (µA) Bias Voltage Line Transient Response 330 320 310 300 290 280 270 260 250 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 275 IVIOC SOURCING 250 IVIOC SINKING 225 200 175 150 –75 –50 –25 0 25 50 75 100 125 150 175 TEMPERATURE (°C) 3070 G44 Transient Load Response Transient Load Response VOUT 50mV/DIV AC-COUPLED VOUT 50mV/DIV AC-COUPLED IOUT 2A/DIV ∆I = 500mA TO 5A IOUT 2A/DIV ∆I = 500mA TO 5A VOUT = 1V 20µs/DIV COUT = 10µF + 4.7µF + 2.2µF IOUT tRISE/tFALL = 100ns 3070 G46 VOUT = 1V 20µs/DIV COUT = 117µF IOUT tRISE/tFALL = 100ns Transient Load Response 3070 G47 Transient Load Response VOUT 50mV/DIV AC-COUPLED VOUT 50mV/DIV AC-COUPLED IOUT 2A/DIV ∆I = 500mA TO 5A IOUT 2A/DIV ∆I = 500mA TO 5A VOUT = 1V 20µs/DIV COUT = 10µF + 4.7µF + 2.2µF IOUT tRISE/tFALL = 1µs 3070 G45 3070 G48 VOUT = 1V 20µs/DIV COUT = 117µF IOUT tRISE/tFALL = 1µs 3070 G49 3070fa 11 LT3070 Pin Functions VIOC (Pin 1): Voltage for In-to-Out Control. The IC incorporates a unique tracking function to control a buck regulator powering the LT3070’s input. The VIOC pin is the output of this tracking function that drives the buck regulator to maintain the LT3070’s input voltage at VOUT + 300mV. This function maximizes efficiency and minimizes power dissipation. See the Applications Information section for more information on proper control of the buck regulator. PWRGD (Pin 2): Power Good. The PWRGD pin is an opendrain NMOS output that actively pulls low if any one of these fault modes is detected: • VOUT is less than 90% of VOUT(NOMINAL) on the rising edge of VOUT . • VOUT drops below 85% of VOUT(NOMINAL) for more than 25µs. • Junction temperature typically exceeds 145°C. • VBIAS is less than its undervoltage lockout threshold. • The OUT-to-IN reverse-current detector activates. See the Applications Information section for more information on PWRGD fault modes. REF/BYP (Pin 3): Reference Filter. The pin is the output of the bandgap reference and has an impedance of approximately 19kΩ. This pin must not be externally loaded. Bypassing the REF/BYP pin to GND with a 10nF capacitor decreases output voltage noise and provides a soft-start function to the reference. LTC recommends the use of a high quality, low leakage capacitor. See the Applications Information section for more information on noise and output voltage margining considerations. GND (Pins 4, 9-14, 20, 26, 29): Ground. The exposed pad (Pin 29) of the QFN package is an electrical connection to GND. To ensure proper electrical and thermal performance, solder Pin 29 to the PCB ground and tie to all GND pins of the package. These GND pins are fused to the internal die attach paddle and the exposed pad to optimize heat sinking and thermal resistance characteristics. See the Applications Information section for thermal considerations and calculating junction temperature. IN (Pins 5, 6, 7, 8): Input Supply. These pins supply power to the high current pass transistor. Tie all IN pins together for proper performance. The LT3070 requires a bypass capacitor at IN to maintain stability and low input impedance over frequency. A 47µF input bypass capacitor suffices for most battery and power plane impedances. Minimizing input trace inductance optimizes performance. Applications that operate with low VIN-VOUT differential voltages and that have large, fast load transients may require much higher input capacitor requirements to prevent the input supply from drooping and allowing the regulator to enter dropout. See the Applications Information section for more information on input capacitor requirements. OUT (Pins 15, 16, 17, 18): Output. These pins supply power to the load. Tie all OUT pins together for proper performance. A minimum output capacitance of 15µF is required for stability. LTC recommends low ESR, X5R or X7R dielectric ceramic capacitors for best performance. A parallel ceramic capacitor combination of 10µF + 4.7µF + 2.2µF or 15 1µF ceramic capacitors in parallel provide excellent stability and load transient response. Large load transient applications require larger output capacitors to limit peak voltage transients. See the Applications Information section for more information on output capacitor requirements. SENSE (Pin 19): Kelvin Sense for OUT . The SENSE pin is the inverting input to the error amplifier. Optimum regulation is obtained when the SENSE pin is connected to the OUT pins of the regulator. In critical applications, the resistance (RP) of PCB traces between the regulator and the load cause small voltage drops, creating a load regulation error at the point of load. Connecting the SENSE pin at the load instead of directly to OUT eliminates this voltage error. Figure 1 illustrates this Kelvin-Sense connection method. Note that the voltage drop across the external PCB traces adds to the dropout voltage of the regulator. The SENSE pin input bias current depends on the selected output voltage. SENSE pin input current varies from 50µA typically at VOUT = 0.8V to 300µA typically at VOUT = 1.8V. 3070fa 12 LT3070 Pin Functions + VBIAS EN BIAS SENSE IN VO2 + OUT LT3070 VO1 VIN RP PWRGD VO0 LOAD MARGSEL MARGTOL VIOC REF/BYP GND RP 3070 F01 Figure 1. Kelvin Sense Connection MARGSEL (Pin 21): Margining Enable and Polarity Selection. This three-state pin determines both the polarity and the active state of the margining function. The logic low threshold is less than 250mV referenced to GND and enables negative voltage margining. The logic high threshold is greater than VBIAS – 250mV and enables positive voltage margining. The voltage range between these two logic thresholds as set by a window comparator defines the logic Hi-Z state and disables the margining function. MARGTOL (Pin 22): Margining Tolerance. This threestate pin selects the absolute value of margining (1%, 3% or 5%) if enabled by the MARGSEL input. The logic low threshold is less than 250mV referenced to GND and enables either ±1% change in VOUT depending on the state of the MARGSEL pin. The logic high threshold is greater than VBIAS – 250mV and enables either ±5% change in VOUT depending on the state of the MARGSEL pin. The voltage range between these two logic thresholds as set by a window comparator defines the logic Hi-Z state and enables either ±3% change in VOUT depending on the state of the MARGSEL pin. VO0, VO1 and VO2 (Pins 23, 24, 25): Output Voltage Select. These three-state pins combine to select a nominal output voltage from 0.8V to 1.8V in increments of 50mV. Output voltage is limited to 1.8V maximum by an internal override of VO1 when VO2 = high. The input logic low threshold is less than 250mV referenced to GND and the logic high threshold is greater than VBIAS – 250mV. The range between these two thresholds as set by a window comparator defines the logic Hi-Z state. See Table 1 in the Applications Information section that defines the VO2, VO1 and VO0 settings versus VOUT . BIAS (Pin 27): Bias Supply. This pin supplies current to the internal control circuitry and the output stage driving the pass transistor. The LT3070 requires a minimum 2.2µF bypass capacitor for stability and proper operation. To ensure proper operation, the BIAS voltage must satisfy the following conditions: 2.2V ≤ VBIAS ≤ 3.6V and VBIAS ≥ (1.25 • VOUT + 1V). For VOUT ≤ 0.95V, the minimum BIAS voltage is limited to 2.2V. EN (Pin 28): Enable. This pin enables/disables the output device only. The internal reference and all support functions are active if VBIAS is above its UVLO threshold. Pulling EN low keeps the reference circuit active, but disables the output pass transistor and puts the LT3070 into a low power nap mode. Drive the EN pin with either a digital logic port or an open-collector NPN or an open-drain NMOS terminated with a pull-up resistor to VBIAS. The pull-up resistor must be less than 35k to meet the VIH condition of the EN pin. If unused, connect EN to BIAS. 3070fa 13 LT3070 Block Diagram 27 BIAS IN 5-8 UVLO AND THERMAL SHUTDOWN + ISENSE REF/BYP – + EAMP BUF – OUT 15-18 LDO CORE SENSE DETECT + – 1 VIOC PWRGD 19 2 VOUT(NOM) + 300mV VREF GND 4,9-14,20,26,29 REF/BYP 600mV 3 PROGRAM CONTROL EN 28 VO2 VO1 VO0 MARGSEL MARGTOL 25 24 23 21 22 3070 BD LOGIC HIGH STATE VBIAS – 0.25V – + LOGIC Hi-Z STATE VBIAS VO2, VO1, VO0 MARGSEL OR MARGTOL 100k VBIAS – 0.9V 100k 0.75V + – + – HIGH IF IN > VBIAS – 0.25V HIGH IF IN < VBIAS – 0.9V AND IN > 0.75V TO LOGIC HIGH IF IN < 0.25V LOGIC LOW STATE – 0.25V + 3070fa 14 LT3070 Applications Information Introduction Current generation FPGA and ASIC processors place stringent demands on the power supplies that power the core, I/O and transceiver channels. These microprocessors may cycle load current from near zero to amps in tens of nanoseconds. Output voltage specifications, especially in the 1V range, require tight tolerances including transient response as part of the requirement. Some ASIC processors require only a single output voltage from which the core and I/O circuitry operate. Some high performance FPGA processors require separate power supply voltages for the processor core, the I/O, and the transceivers. Often, these supply voltages must be low noise and high bandwidth to achieve the lowest bit-error rates. These requirements mandate the need for very accurate, low noise, high current, very high speed regulator circuits that operate at low input and output voltages. The LT3070 is a low voltage, UltraFast transient response linear regulator. The device supplies up to 5A of output current with a typical dropout voltage of 85mV. A 0.01µF reference bypass capacitor decreases output voltage noise to 25µVRMS (BW = 10Hz to 100kHz). The LT3070’s high bandwidth provides UltraFast transient response using low ESR ceramic output capacitors (15µF minimum), saving bulk capacitance, PCB area and cost. The LT3070’s features permit state-of-the-art linear regulator performance. The LT3070 is ideal for high performance FPGAs, microprocessors, sensitive communication supplies, and high current logic applications that also operate over low input and output voltages. Output voltage for the LT3070 is digitally selectable in 50mV increments over a 0.8V to 1.8V range. A margining function allows the user to adjust system output voltage in increments of ±1%, ±3% or ±5%. The IC incorporates a unique tracking function, which if enabled by the user, controls an upsteam regulator powering the LT3070’s input (see Figure 8). This tracking function drives the buck regulator to maintain the LT3070’s input voltage to VOUT + 300mV. This input-to-output voltage control allows the user to change the regulator output voltage, and have the switching regulator powering the LT3070’s input to track to the optimum input voltage with no component changes. This combines the efficiency of a switching regulator with superior linear regulator response. It also permits thermal management of the system even with a maximum 5A output load. LT3070 internal protection includes input undervoltage lockout (UVLO), reverse-current protection, precision current limiting with power foldback and thermal shutdown. The LT3070 regulator is available in a thermally enhanced 28-lead, 4mm × 5mm QFN package. The LT3070’s architecture drives an internal N-channel power MOSFET as a source follower. This configuration permits a user to obtain an extremely low dropout, UltraFast transient response regulator with excellent high frequency PSRR performance. The LT3070 achieves superior regulator bandwidth and transient load performance by eliminating expensive bulk tantalum or electrolytic capacitors in the most modern and demanding microprocessor applications. Users realize significant cost savings as all additional bulk capacitance is removed. The additional savings of insertion cost, purchasing/inventory cost and board space are readily apparent. Precision incremental output voltage control accommodates legacy and future microprocessor power supply voltages. Output capacitor networks simplify to direct parallel combinations of ceramic capacitors. Often, the high frequency ceramic decoupling capacitors required by these various FPGA and ASIC processors are sufficient to stabilize the system (see Stability and Output Capacitance section). This regulator design provides ample bandwidth and responds to transient load changes in a few hundred nanoseconds versus regulators that respond in many microseconds. The LT3070 also incorporates precision current limiting, enable/disable control of output voltage and integrated overvoltage and thermal shutdown protection. The LT3070’s unique design combines the benefits of low dropout voltage, high functional integration, precision performance and UltraFast transient response, as well as providing significant cost savings on the output capacitance needed in fast load transient applications. As lower voltage applications become increasingly prevalent with higher frequency switching power supplies, the LT3070 offers superior regulation and an appreciable 3070fa 15 LT3070 Applications Information component cost savings. The LT3070 steps to the next level of performance for the latest generation FPGAs, DSPs and microprocessors. The simple versatility and benefits derived from these circuits exceed the power supply needs of today’s high performance microprocessors. Programming Output Voltage Three tri-level input pins, VO2, VO1 and VO0, select the value of output voltage. Table 1 illustrates the 3-bit digital word to output voltage resulting from setting these pins high, low or allowing them to float. These pins may be tied high or low by either pin-strapping them to VBIAS or driving them with digital ports. Pins that float may either actually float or require logic that has Hi-Z output capability. This allows output voltage to be dynamically changed if necessary. Output voltage is selectable from a minimum of 0.8V to a maximum of 1.8V in increments of 50mV. The MSB, VO2, sets the pedestal voltage, and the LSB’s, VO1 and VO0 increment VOUT . Output voltage is limited to 1.8V maximum by an internal override of VO1 (default to low) when VO2 = high. Table 1: VO2 to VO0 Settings vs Output Voltage VO2 VO1 VO0 VOUT(NOM) VO2 VO1 VO0 VOUT(NOM) 0 0 0 0.80V Z 0 1 1.35V 0 0 Z 0.85V Z Z 0 1.40V 0 0 1 0.90V Z Z Z 1.45V 0 Z 0 0.95V Z Z 1 1.50V 0 Z Z 1.00V Z 1 0 1.55V 0 Z 1 1.05V Z 1 Z 1.60V 0 1 0 1.10V Z 1 1 1.65V 0 1 Z 1.15V 1 X 0 1.70V 0 1 1 1.20V 1 X Z 1.75V Z 0 0 1.25V 1 X 1 1.80V Z 0 Z 1.30V X = Don’t Care, 0 = Low, Z = Float, 1 = High The input logic low threshold is less than 250mV referenced to GND and the logic high threshold is greater than VBIAS – 250mV. The range between these two thresholds as set by a window comparator defines the logic Hi-Z state. REF/BYP—Voltage Reference This pin is the buffered output of the internal bandgap reference and has an output impedance of ≅19kΩ. The design includes an internal compensation pole at fC = 4kHz. A 10nF REF/BYP capacitor to GND creates a lowpass pole at fLP = 840Hz. The 10nF capacitor decreases reference voltage noise to about 10µVRMS and soft-starts the reference. The LT3070 only soft-starts the reference voltage during an initial turn-on sequence. If the EN pin is toggled low after initial turn-on, the reference remains powered-up. Therefore, toggling the EN pin from low to high does not soft-start the reference. Only by turning the BIAS supply voltage on and off will the reference be soft-started. Output voltage noise is the RMS sum of the reference voltage noise in addition to the amplifier noise. The REF/BYP pin must not be DC loaded by anything except for applications that parallel other LT3070 regulators for higher output currents. Consult the Applications Section on Paralleling for further details. Output Voltage Margining Two tri-level input pins, MARGSEL (polarity) and MARGTOL (scale), select the polarity and amount of output voltage margining. Margining is programmable in increments of ±1%, ±3% and ±5%. Margining is internally implemented as a scaling of the reference voltage. Table 2 illustrates the 2-bit digital word to output voltage margining resulting from setting these pins high, low or allowing them to float. These pins may be set high or low by either pin-strapping them to VBIAS or driving them with digital ports. Pins that float may either actually float or require logic that has “Hi-Z” output capability. This allows output voltage to be dynamically margined if necessary. The MARGSEL pin determines both the polarity and the active state of the margining function. The logic low threshold is less than 250mV referenced to GND and enables negative voltage margining. The logic high threshold is greater than VBIAS – 250mV and enables positive voltage margining. The voltage range between these two logic thresholds as set by a window comparator defines the logic Hi-Z state and disables the margining function. 3070fa 16 LT3070 Applications Information The MARGTOL pin selects the absolute value of margining (1%, 3% or 5%) if enabled by the MARGSEL input. The logic low threshold is less than 250mV referenced to GND and enables either ±1% change in VOUT depending on the state of the MARGSEL pin. The logic high threshold is greater than VBIAS – 250mV and enables either ±5% change in VOUT depending on the state of the MARGSEL pin. The voltage range between these two logic thresholds as set by a window comparator defines the logic Hi-Z state and enables either ±3% change in VOUT depending on the state of the MARGSEL pin. Table 2: Programming Margining MARGSEL 0 0 0 Z Z Z 1 1 1 MARGTOL 0 Z 1 0 Z 1 0 Z 1 % OF VOUT(NOM) –1 –3 –5 0 0 0 1 3 5 Enable Function—Turning On and Off The EN pin enables/disables the output device only. The LT3070 reference and all support functions remain active if VBIAS is above its UVLO threshold. Pulling the EN pin low puts the LT3070 into nap mode. In nap mode, the reference circuit is active, but the output is disabled and quiescent current decreases. Drive the EN pin with either a digital logic port or an opencollector NPN or an open-drain NMOS terminated with a pull-up resistor to VBIAS. The pull-up resistor must be less than 35k to meet the VIH condition of the EN pin. If unused, connect EN to BIAS. Input Undervoltage Lockout on BIAS Pin An internal undervoltage lockout (UVLO) comparator monitors the BIAS supply voltage. If VBIAS drops below the UVLO threshold, all functions shut down, the pass transistor is gated off and output current falls to zero. The typical BIAS pin UVLO threshold is 1.55V on the rising edge of VBIAS. The UVLO circuit incorporates about 150mV of hysteresis on the falling edge of VBIAS. High Efficiency Linear Regulator—Input-to-Output Voltage Control The VIOC (voltage input-to-output control) pin is a function to control a switching regulator and facilitate a design solution that maximizes system efficiency at high load currents and still provides low dropout voltage performance. The VIOC pin is the output of an integrated transconductance amplifier that sources and sinks about 250µA of current. It typically regulates the output of most LTC® switching regulators or LTM® power modules, by sinking current from the ITH compensation node. The VIOC function controls a buck regulator powering the LT3070’s input by maintaining the LT3070’s input voltage to VOUT + 300mV. This 300mV VIN-VOUT differential voltage is chosen to provide fast transient response and good high frequency PSRR while minimizing power dissipation and maximizing efficiency. For example, 1.5V to 1.2V conversion and 1.3V to 1V conversion yield 1.5W maximum power dissipation at 5A full output current. Figure 2 depicts that the switcher’s feedback resistor network sets the maximum switching regulator output voltage if the linear regulator is disabled. However, once the LT3070 is enabled, the VIOC feedback loop decreases the switching regulator output voltage back to VOUT + 300mV. Using the VIOC function creates a feedback loop between the LT3070 and the switching regulator. As such, the feedback loop must be frequency compensated for stability. Fortunately, the connection of VIOC to many LTC switching regulator ITH pins represents a high impedance characteristic which is the optimum circuit node to frequency compensate the feedback loop. Figure 2 illustrates the typical frequency compensation network used at the VIOC node to GND. The VIOC amplifier characteristics are: gm = 3.2mS, IOUT = ±250µA, BW = 10MHz. If the VIOC function is not used, terminate the VIOC pin to GND with a small capacitor (1000pF) to prevent oscillations. 3070fa 17 LT3070 Applications Information LT3070 IN OUT SWITCHING REGULATOR REF + – LOAD – + PWM FB VOUT + VREF 300mV VIOC REFERENCE ITH 3070 F02 Figure 2. VIOC Control Block Diagram PWRGD—Power Good PWRGD pin is an open-drain NMOS digital output that actively pulls low if any one of these fault modes is detected: • VOUT is less than 90% of VOUT(NOMINAL) on the rising edge of VOUT . • VOUT drops below 85% of VOUT(NOMINAL) for more than 25µs. • VBIAS is less than its undervoltage lockout threshold. • The OUT-to-IN reverse-current detector activates. • Junction temperature exceeds 145°C typically.* *The junction temperature detector is an early warning indicator that trips approximately 20°C before thermal shutdown engages. Stability and Output Capacitance The LT3070’s feedback loop requires an output capacitor for stability. Choose COUT carefully and mount it in close proximity to the LT3070’s OUT and GND pins. Include wide routing planes for OUT and GND to minimize inductance. If possible, mount the regulator immediately adjacent to the application load to minimize distributed inductance for optimal load transient performance. Point-of-Load applications present the best case layout scenario for extracting full LT3070 performance. Low ESR, X5R or X7R ceramic chip capacitors are the LTC recommended choice for stabilizing the LT3070. Additional bulk capacitors distributed beyond the immediate decoupling capacitors are acceptable as their parasitic ESL and ESR, combined with the distributed PCB inductance isolates them from the primary compensation pole provided by the local surface mount ceramic capacitors. The LT3070 requires a minimum output capacitance of 15µF for stability. LTC strongly recommends that the output capacitor network consist of several low value ceramic capacitors in parallel. Why Do Multiple, Small-Value Output Capacitors Connected in Parallel Work Better? The LT3070’s unity-gain bandwidth with COUT of 15µF is about 1MHz at its full-load current of 5A. Surface mounted MLCC capacitors have a self-resonance frequency of fR = 1/(2π√LC), which must be pushed to a frequency higher than the regulator bandwidth. Standard MLCC capacitors are acceptable. To keep the resonant frequency greater than 1MHz, the product 1/(2π√LC) must be greater than 1MHz. At this bandwidth, PCB vias can add significant inductance, thus the fundamental decoupling capacitors must be mounted on the same plane as the LT3070. Typical 0603 or 0805 case-size capacitors have an ESL of ~800pH and PCB mounting can contribute up to ~200pH. Thus, it becomes necessary to reduce the parasitic 3070fa 18 LT3070 Applications Information inductance by using a parallel capacitor combination. A suitable methodology must control this paralleling as capacitors with the same self-resonant frequency, fR, will form a tank circuit that can induce ringing of their own accord. Small amounts of ESR (5mΩ to 20mΩ) have some benefit in dampening the resonant loop, but higher ESRs degrade the capacitor response to transient load steps with rise/fall times less than 1µs. The most area efficient parallel capacitor combination is a graduated 4/2/1 scale of fR of the same case size. Under these conditions, the individual ESLs are relatively uniform, and the resonance peaks are deconstructively spread beyond the regulator bandwidth. The recommended parallel combination that approximates 15µF is 10µF + 4.7µF + 2.2µF. Capacitors with case sizes larger than 0805 have higher ESL and lower ESR (<5mΩ). Therefore, more capacitors with smaller values (<10µF) must be chosen. Users should consider new generation, low inductance capacitors to push out fR and maximize stability. Refer to the surface mount ceramic capacitor manufacturer’s data sheets for capacitor specifications. Figure 3 illustrates an optimum PCB layout for the parallel output capacitor combination, but also illustrates the GND connection between the IN capacitor and the OUT capacitors to minimize the AC GND loop for fast load transients. This tight bypassing connection minimizes EMI and optimizes bypassing. Many of the applications in which the LT3070 excels, such as FPGA, ASIC processor or DSP supplies, typically require a high frequency decoupling capacitor network for the device being powered. This network generally consists of many low value ceramic capacitors in parallel. In some LT3070 SENSE IN OUT GND Lo-Z INPUT LOAD PLANE 2.2µF 47µF 4.7µF 10µF 3070 F03 applications, this total value of capacitance may be close to the LT3070’s minimum 15µF capacitance requirement. This may reduce the required value of capacitance directly at the LT3070’s output. Multiple low value capacitors in parallel present a favorable frequency characteristic that pushes many of the parasitic poles/zeroes beyond the LT3070’s unity-gain crossover frequency. This technique illustrates the method that extracts the full bandwidth performance of the LT3070. Give additional consideration to the use of ceramic capacitors. Ceramic capacitors are manufactured with a variety of dielectrics, each with different behavior across temperature and applied voltage. The most common dielectrics used are specified with EIA temperature characteristic codes of Z5U, Y5V, X5R and X7R. The Z5U and Y5V dielectrics are good for providing high capacitances in a small package, but they tend to have strong voltage and temperature coefficients as shown in Figures 4 and 5. When used with a 5V regulator, a 16V 10µF Y5V capacitor can exhibit an effective value as low as 1µF to 2µF for the DC bias voltage applied and over the operating temperature range. The X5R and X7R dielectrics result in more stable characteristics and are more suitable for use as the output capacitor. The X7R type has better stability across temperature, while the X5R is less expensive and is available in higher values. Care still must be exercised when using X5R and X7R capacitors; the X5R and X7R codes only specify operating temperature range and maximum capacitance change over temperature. Capacitance change due to DC bias with X5R and X7R capacitors is better than Y5V and Z5U capacitors, but can still be significant enough to drop capacitor values below appropriate levels. Capacitor DC bias characteristics tend to improve as component case size increases, but expected capacitance at operating voltage should be verified. Voltage and temperature coefficients are not the only sources of problems. Some ceramic capacitors have a piezoelectric response. A piezoelectric device generates voltage across its terminals due to mechanical stress, similar to the way a piezoelectric microphone works. For a ceramic capacitor the stress can be induced by vibrations in the system or thermal transients. Figure 3. Example PCB Layout 3070fa 19 LT3070 Applications Information 20 0 CHANGE IN VALUE (%) the LT3070 back to the power supply ground), large input capacitors are required to avoid an unstable application. BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10µF X5R –20 –40 –60 Y5V –80 –100 0 2 10 12 4 8 6 DC BIAS VOLTAGE (V) 14 16 3070 F04 Figure 4. Ceramic Capacitor DC Bias Characteristics 40 CHANGE IN VALUE (%) 20 0 BOTH CAPACITORS ARE 16V, 1210 CASE SIZE, 10µF X5R –20 –40 Y5V –60 –80 –100 –50 –25 50 25 75 0 TEMPERATURE (°C) 100 125 3070 F05 Figure 5. Ceramic Capacitor Temperature Characteristics Stability and Input Capacitance The LT3070 is stable with a minimum capacitance of 47µF connected to its IN pins. Use low ESR capacitors to minimize instantaneous voltage drops under large load transient conditions. Large VIN droops during large load transients may cause the regulator to enter dropout with corresponding degradation in load transient response. Increased values of input and output capacitance may be necessary depending on an application’s requirements. Sufficient input capacitance is critical as the circuit is intentionally operated close to dropout to minimize power. Ideally, the output impedance of the supply that powers IN should be less than 10mΩ to support a 5A load with large transients. In cases where wire is used to connect a power supply to the input of the LT3070 (and also from the ground of This is due to the inductance of the wire forming an LC tank circuit with the input capacitor and not a result of the LT3070 being unstable. The self inductance, or isolated inductance, of a wire is directly proportional to its length. However, the diameter of a wire does not have a major influence on its self inductance. For example, one inch of 18-AWG, 0.04 inch diameter wire has 28nH of self inductance. The self inductance of a 2-AWG isolated wire with a diameter of 0.26 inch is about half the inductance of a 18-AWG wire. The overall self inductance of a wire can be reduced in two ways. One is to divide the current flowing towards the LT3070 between two parallel conductors which flows in the same direction in each. In this case, the farther the wires are placed apart from each other, the more inductance will be reduced, up to a 50% reduction when placed a few inches apart. Splitting the wires basically connects two equal inductors in parallel. However, when placed in close proximity from each other, mutual inductance is added to the overall self inductance of the wires. The most effective way to reduce overall inductance is to place the forward and return-current conductors (the wire for the input and the wire for the return ground) in very close proximity. Two 18-AWG wires separated by 0.05 inch reduce the overall self inductance to about onefourth of a single isolated wire. If the LT3070 is powered by a battery mounted in close proximity with ground and power planes on the same circuit board, a 47µF input capacitor is sufficient for stability. However, if the LT3070 is powered by a distant supply, use a low ESR, large value input capacitor on the order of 330µF. As power supply output impedance varies, the minimum input capacitance needed for application stability also varies. Bias Pin Capacitance Requirements The BIAS pin supplies current to most of the internal control circuitry and the output stage driving the pass transistor. The LT3070 requires a minimum 2.2µF bypass capacitor for stability and proper operation. To ensure proper operation, the BIAS voltage must satisfy the following conditions: 2.2V ≤ VBIAS ≤ 3.6V and VBIAS ≥ (1.25 • VOUT + 1V). For VOUT ≤ 0.95V, the minimum BIAS voltage is limited to 2.2V. 3070fa 20 LT3070 Applications Information Load Regulation The LT3070 provides a Kelvin sense pin for VOUT , allowing the application to correct for parasitic package and PCB I-R drops. However, LTC recommends that the SENSE pin terminate in close proximity to the LT3070’s OUT pins. This minimizes parasitic inductance and optimizes regulation. The LT3070 handles moderate levels of output line impedance, but excessive impedance between VOUT and COUT causes excessive phase shift in the feedback loop and adversely affects stability. Figure 1 in the Pin Functions section illustrates the KelvinSense connection method that eliminates voltage drops due to PCB trace resistance. However, note that the voltage drop across the external PCB traces adds to the dropout voltage of the regulator. The SENSE pin input bias current depends on the selected output voltage. SENSE pin input current varies from 50µA typically at VOUT = 0.8V to 300µA typically at VOUT = 1.8V. Short-Circuit and Overload Recovery Like many IC power regulators, the LT3070 has safe operating area (SOA) protection. The safe area protection decreases current limit as input-to-output voltage increases and keeps the power transistor inside a safe operating region for all values of input-to-output voltage up to the absolute maximum voltage rating. VBIAS must be above the UVLO threshold for any function. The LT3070 has a precision current limit specified at ±20% that is active if VBIAS is above UVLO. Under conditions of maximum ILOAD and maximum VIN-VOUT the device’s power dissipation peaks at about 3W. If ambient temperature is high enough, die junction temperature will exceed the 125°C maximum operating temperature. If this occurs, the LT3070 relies on two additional thermal safety features. At about 145°C, the PWRGD output pulls low providing an early warning of an impending thermal shutdown condition. At 165°C typically, the LT3070’s thermal shutdown engages and the output is shut down until the IC temperature falls below the thermal hysteresis limit. The SOA protection decreases current limit as the IN-to-OUT voltage increases and keeps the power dissipation at safe levels for all values of input-to-output voltage. The LT3070 provides some output current at all values of input-to-output voltage up to the absolute maximum voltage rating. See the Current Limit vs VIN curve in the Typical Performance Characteristics. During start-up, after the BIAS voltage has cleared its UVLO threshold and VIN is increasing, output voltage increases at the rate of current limit charging COUT . With a high input voltage, a problem can occur where the removal of an output short will not allow the output voltage to recover. Other regulators with current limit foldback also exhibit this phenomenon, so it is not unique to the LT3070. The load line for such a load may intersect the output current curve at two points: normal operation and the SOA restricted load current settings. A common situation is immediately after the removal of a short circuit, but with a static load ≥ 1A. In this situation, removal of the load or reduction of IOUT to <1A will clear this condition and allow VOUT to return to normal regulation. Reverse Voltage The LT3070 incorporates a circuit that detects if VIN decreases below VOUT . This reverse-voltage detector has a typical threshold of about (VIN – VOUT) = –6mV. If the threshold is exceeded, this detector circuit turns off the drive to the internal NMOS pass transistor, thereby turning off the output. The output pulls low with the load current discharging the output capacitance. This circuit’s intent is to limit and prevent back-feed current from OUT to IN if the input voltage collapses due to a fault or overload condition. Thermal Considerations The LT3070’s maximum rated junction temperature of 125°C limits its power handling capability and is dominated by the output current multiplied by the input/output voltage differential: IOUT • (VIN – VOUT) The LT3070’s internal power and thermal limiting circuitry protect it under overload conditions. For continuous normal load conditions, do not exceed the maximum junction temperature of 125°C. Give careful consideration to all sources of thermal resistance from junction to ambient. This includes junction to case, case-to-heat sink interface, 3070fa 21 LT3070 Applications Information heat sink resistance or circuit board to ambient as the application dictates. Also, consider additional heat sources mounted in proximity to the LT3070. The LT3070 is a surface mount device and as such, heat sinking is accomplished by using the heat spreading capabilities of the PC board and its copper traces. Surface mount heat sinks and plated through-holes can also be used to spread the heat generated by power devices. Junction-to-case thermal resistance is specified from the IC junction to the bottom of the case directly below the die. This is the lowest resistance path for heat flow. Proper mounting is required to ensure the best possible thermal flow from this area of the package to the heat sinking material. Note that the exposed pad is electrically connected to GND. where: IOUT(MAX) = 4A VIN(MAX) = 1.26V IBIAS at (IOUT = 4A, VBIAS = 2.5V) = 6.91mA IGND at (IOUT = 4A, VBIAS = 2.5V) = 0.87mA thus: P = 4A(1.26V – 0.9V) + (6.91mA – 0.87mA)0.9V + 0.87mA(2.5V) = 1.448W With the QFN package soldered to maximum copper area, the thermal resistance is 30°C/W. So the junction temperature rise above ambient equals: Table 3 lists thermal resistance as a function of copper area in a fixed board size. All measurements were taken in still air on a 4-layer FR-4 board with 1 oz solid internal planes and 2 oz top/bottom external trace planes with a total board thickness of 1.6mm. PCB layers, copper weight, board layout and thermal vias affect the resultant thermal resistance. For further information on thermal resistance and high thermal conductivity test boards, refer to JEDEC standard JESD51, notably JESD51-12 and JESD51-7. Achieving low thermal resistance necessitates attention to detail and careful PCB layout. 1.448W at 30°C/W = 43.44°C Table 3, UFD Plastic Package, 28-Lead QFN Multiple LT3070s may be paralleled to obtain higher output current. This paralleling concept borrows from the scheme employed by the LT3080. COPPER AREA TOPSIDE* BACK SIDE BOARD AREA THERMAL RESISTANCE (JUNCTION-TO-AMBIENT) 2500mm2 2500mm2 2500mm2 30°C/W 1000mm2 2500mm2 2500mm2 32°C/W 225mm2 2500mm2 2500mm2 33°C/W 100mm2 2500mm2 2500mm2 35°C/W *Device is mounted on topside Calculating Junction Temperature Example: Given an output voltage of 0.9V, an input voltage range of 1.2V ± 5%, a BIAS voltage of 2.5V, a maximum output current of 4A and a maximum ambient temperature of 50°C, what will the maximum junction temperature be? The power dissipated by the device equals: IOUT(MAX) • (VIN(MAX) – VOUT) + (IBIAS – IGND) • VOUT + IGND • VBIAS 22 The maximum junction temperature equals the maximum ambient temperature plus the maximum junction temperature rise above ambient or: TJMAX = 50°C + 43.44°C = 93.44°C Applications that cannot support extensive PCB space for heat sinking the LT3070 require a derating of output current or increased airflow. Paralleling Devices for Higher IOUT To accomplish this paralleling, tie the REF/BYP pins of the paralleled regulators together. This effectively gives an averaged value of multiple 600mV reference voltage sources. Tie the OUT pins of the paralleled regulators to the common load plane through a small piece of PC trace ballast or an actual surface mount sense resistor beyond the primary output capacitors of each regulator. The required ballast is dependent upon the application output voltage and peak load current. The recommended ballast is that value which contributes 1% to load regulation. For example, two LT3070 regulators configured to output 1V, sharing a 10A load require 2mΩ of ballast at each output. The Kelvin SENSE pins connect to the regulator side of the ballast resistors to keep the individual control loops from conflicting with each other (see Figures 8 and 9). 3070fa LT3070 Applications Information Keep this ballast trace area free of solder to maintain a controlled resistance. Table 4 shows a simple guideline for PCB trace resistance as a function of weight and trace width. Table 4. PC Board Trace Resistance WEIGHT (Oz) 100 MIL WIDTH* 200 MIL WIDTH* 1 5.43 2.71 2 2.71 1.36 *Trace resistance is measured in milliohms/in Quieting the Noise The LT3070 offers numerous noise performance advantages. Each LDO has several sources of noise. An LDO’s most critical noise source is the reference, followed by the LDO error amplifier. Traditional low noise regulators buffer the voltage reference out to an external pin (usually through a large value resistor) to allow for bypassing and PWRGD 2.2µF IN 330µF EN VO0 BIAS PWRGD SENSE LT3070 OUT VO1 2.2µF* VO2 NC MARGSEL NC MARGTOL VIOC 1nF This approach also accommodates reference sharing between LT3070 regulators that are hooked up in current sharing applications. The REF/BYP filter capacitor delays the initial power-up time by a factor of the RC time constant. VREF remains active in nap mode, thus start-up time is significantly reduced and well controlled coming out of nap mode (EN:LO↑HI). 50k VBIAS 2.5V TO 3.6V VIN 1.5V noise reduction of reference noise. The LT3070 deviates from the traditional voltage reference by generating a low voltage VREF from a reference current into an internal resistor ≅19k. This intermediate impedance node (REF/BYP) facilitates external filtering directly. A 10nF filter capacitor minimizes reference noise to 10µVRMS at the 600mV REF/BYP pin, equivalently a 17µV contribution to output noise at VOUT = 1V. See the Typical Performance Characteristics for Noise vs Output Voltage performance as a function of CREF/BYP . REF/BYP GND 4.7µF* 10µF* VOUT 1.2V 5A *X5R OR X7R CAPACITORS 0.01µF 3070 F06 Figure 6. 1.5V to 1.2V Linear Regulator 3070fa 23 LT3070 Applications Information VBIAS 3.3V 47µF 6.3V s3 1Ω 50k SVIN NC PGOOD RUN PVIN PVIN SVIN TRACK PVIN SW PVIN SW PLLLPF SW LTC3415EUHF CLKOUT VO0 ITH VO1 VO2 NC MARGTOL MGN NC MARGSEL 100µF 6.3V s2 NC SVIN 4.7µF* *X5R OR X7R CAPACITORS REF/BYP GND 2k 4.7nF VOUT 1V 5A 10µF* OUT 2.2µF* VIOC 10k PWRGD SENSE LT3070 NC ITHM MODE IN NC 20k VFB PGND CLKIN BIAS EN 1.3V/5A 47µF BSEL PHMODE NC 0.2µH SW SGND NC PWRGD 2.2µF 0.1µF 0.01µF 1nF SGND PGND PGND PGND PGND 3070 F07 PGND PGND NOTE: LTC3415 SWITCHER, 2MHz INTERNAL OSCILLATOR LTC3415 AND LT3070 ON SAME PCB POWER PLANE Figure 7. Regulator with VIOC Buck Control VBIAS 3.3V 47µF 6.3V s3 50k 1Ω PWRGD 2.2µF SVIN NC 0.1µF PGOOD RUN NC PVIN PVIN SVIN TRACK SW PVIN SW PVIN SW PLLLPF SW CLKOUT LTC3415EUHF CLKIN MODE PGND PGND PGND PGND PGND BIAS EN 1.3V/7A IN 47µF NC VO0 NC VO1 VO2 NC MARGTOL NC MARGSEL ITHM NC VIOC 17.5k 1% 15k 1% 4.7µF* 10µF* RTRACE 3mΩ CONTROLLED P.O.L. 1 POWER PLANE 1V/8A 0.01µF P.O.L. 2 2.2µF SGND PGND PGND NOTE: LTC3415 SWITCHER, 2MHz INTERNAL OSCILLATOR LTC3415 AND LT3070 s2 ON SAME PCB POWER PLANE 2.2µF* REF/BYP GND 1nF 100µF 6.3V s2 VOUT 1V 3.5A OUT *X5R OR X7R CAPACITORS ITH BSEL PWRGD SENSE LT3070 MGN VFB PHMODE NC 0.2µH SGND EN BIAS IN 47µF VO0 NC VO1 VO2 NC MARGTOL NC MARGSEL VIOC 1nF PWRGD SENSE LT3070 NC RTRACE 3mΩ CONTROLLED OUT 2.2µF* 4.7µF* 10µF* VOUT 1V 3.5A *X5R OR X7R CAPACITORS REF/BYP GND 0.01µF 3070 F08 Figure 8. 1V, 7A Point-of-Load Current Sharing Regulators 3070fa 24 LT3070 Typical Applications 50k VIN 3.3V EN NC VO0 NC VO1 VO2 NC MARGTOL NC MARGSEL 1nF NC 10µF 10µF NC NC NC SW1 CLKIN1 CLKOUT1 CLKIN2 CLKOUT2 VIN1 VOUT1 SVIN1 MGN1 RUN1 FB1 PLLLPF1 ITH1 MODE1 ITHM1 PHMODE1 BSEL1 TRACK1 PGOOD1 LTM4616 VIN2 VOUT2 SVIN2 MGN2 RUN2 FB2 PLLLPF2 ITH2 MODE2 ITHM2 PHMODE2 BSEL2 TRACK2 PGOOD2 SW2 SGND1 GND1 VIN 3.3V NC EN 100µF 6.3V X5R 10k NC NC 4.7nF VBUCK2 2.1V/8A VO1 VO2 NC MARGTOL NC MARGSEL VIOC EN VO0 4.7nF RTRACE 2.5mΩ CONTROLLED P.O.L. 1 POWER PLANE 1V/7A 0.01µF RTRACE 2.5mΩ CONTROLLED PWRGD SENSE 10µF* VOUT 1V 4A 10µF* VOUT 1.8V 5A 10µF* VOUT 1.5V 3A OUT 2.2µF* 4.7µF* *X5R OR X7R CAPACITORS REF/BYP GND BIAS 0.01µF VO1 VO2 NC MARGTOL NC MARGSEL 1nF VIN 3.3V PWRGD SENSE LT3070 NC VIOC 2k 10µF* *X5R OR X7R CAPACITORS LT3070 IN 20k 4.7µF* 2.2µF 47µF 10k BIAS NC VIN 3.3V NC 2.2µF* P.O.L. 2 VO0 1nF VOUT 1V 4A OUT REF/BYP GND NC NC NC SGND2 GND2 NOTE: THE TWO LTM4616 MODULE CHANNELS ARE INDEPENDENTLY CONTROLLED BY THE VIOC CONTROLS FROM THE LINEAR REGULATORS LT3070 IN 47µF 2k 100µF 6.3V X5R VIOC PWRGD SENSE 2.2µF VBUCK1 1.3V/8A 20k BIAS IN 47µF VIN 3.3V PWRGD 2.2µF OUT 2.2µF* 4.7µF* *X5R OR X7R CAPACITORS REF/BYP GND 0.01µF 2.2µF EN BIAS IN 47µF VO0 LT3070 NC VO1 NC NC VO2 NC MARGSEL OUT MARGTOL VIOC 1nF PWRGD SENSE REF/BYP GND 2.2µF* 4.7µF* *X5R OR X7R CAPACITORS 0.01µF 3070 F09 Figure 9. Triple Output Supply Providing 1V, 8A and 1.8V, 5A and 1.5V, 3A 3070fa 25 LT3070 Package Description UFD Package 28-Lead Plastic QFN (4mm × 5mm) (Reference LTC DWG # 05-08-1712 Rev B) 0.70 p0.05 4.50 p 0.05 3.10 p 0.05 2.50 REF 2.65 p 0.05 3.65 p 0.05 PACKAGE OUTLINE 0.25 p0.05 0.50 BSC 3.50 REF 4.10 p 0.05 5.50 p 0.05 RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED 4.00 p 0.10 (2 SIDES) 0.75 p 0.05 R = 0.05 TYP PIN 1 NOTCH R = 0.20 OR 0.35 s 45o CHAMFER 2.50 REF R = 0.115 TYP 27 28 0.40 p 0.10 PIN 1 TOP MARK (NOTE 6) 1 2 5.00 p 0.10 (2 SIDES) 3.50 REF 3.65 p 0.10 2.65 p 0.10 (UFD28) QFN 0506 REV B 0.200 REF 0.00 – 0.05 0.25 p 0.05 0.50 BSC BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X). 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3070fa 26 LT3070 Revision History REV DATE DESCRIPTION PAGE NUMBER A 5/10 Entire data sheet revised 1 to 28 3070fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 27 LT3070 Typical Application 50k VBIAS 2.5V TO 3.6V VIN 1.5V PWRGD 2.2µF IN 330µF EN VO0 BIAS PWRGD SENSE LT3070 OUT VO1 2.2µF* VO2 NC MARGSEL NC MARGTOL VIOC 1nF REF/BYP GND 4.7µF* 10µF* VOUT 1.2V 5A *X5R OR X7R CAPACITORS 0.01µF 3070 TA02 1.5V to 1.2V Linear Regulator Related Parts PART DESCRIPTION COMMENTS LT1763 500mA, Low Noise LDO 300mV Dropout Voltage, Low Noise: 20µVRMS, VIN: 1.8V to 20V, SO-8 Package LT1764/LT1764A 3A, Fast Transient Response, Low Noise LDO 340mV Dropout Voltage, Low Noise: 40µVRMS, VIN: 2.7V to 20V, TO-220 and DD Packages “A” Version Stable Also with Ceramic Caps LT1963/LT1963A 1.5A Low Noise, Fast Transient Response LDO 340mV Dropout Voltage, Low Noise: 40µVRMS, VIN: 2.5V to 20V, “A” Version Stable with Ceramic Caps, TO-220, DD, SOT-223 and SO-8 Packages LT1965 1.1A, Low Noise, Low Dropout Linear Regulator 290mV Dropout Voltage, Low Noise: 40µVRMS, VIN: 1.8V to 20V, VOUT : 1.2V to 19.5V, Stable with Ceramic Caps, TO-220, DD-Pak, MSOP and 3mm × 3mm DFN Packages LT3021 500mA, Low Voltage, VLDO™ Linear Regulator VIN: 0.9V to 10V, Dropout Voltage = 160mV (Typ), Adjustable Output (VREF = VOUT(MIN) = 200mV), Fixed Output Voltages: 1.2V, 1.5V, 1.8V, Stable with Low ESR, Ceramic Output Capacitors 16-Pin DFN (5mm × 5mm) and 8-Lead SO Packages LT3080/LT3080-1 1.1A, Parallelable, Low Noise, Low Dropout Linear Regulator 300mV Dropout Voltage (2-Supply Operation), Low Noise: 40µVRMS, VIN: 1.2V to 36V, VOUT : 0V to 35.7V, Current-Based Reference with 1 Resistor VOUT Set; Directly Parallelable (No Op Amp Required), Stable with Ceramic Caps, TO-220, SOT-223, MSOP-8 and 3mm × 3mm DFN-8 Packages; LT3080-1 has Integrated Internal Ballast Resistor LT3085 500mA, Parallelable, Low Noise, Low Dropout Linear Regulator 275mV Dropout Voltage (2-Supply Operation), Low Noise: 40µVRMS, VIN: 1.2V to 36V, VOUT : 0V to 35.7V, Current-Based Reference with 1 Resistor VOUT Set; Directly Parallelable (No Op Amp Required), Stable with Ceramic Caps, MSOP-8 and 2mm × 3mm DFN-6 Packages LTC3025-1/ LTC3025-2 500mA Micropower VLDO Linear Regulator in 2mm × 2mm DFN VIN = 0.9V to 5.5V, Dropout Voltage: 75mV, Low Noise 80µVRMS, Low IQ: 54µA, Fixed Output: 1.2V (LTC3025-2); Adjustable Output Range: 0.4V to 3.6V (LTC3025-1) 2mm × 2mm 6-Lead DFN Package LTC3026 1.5A, Low Input Voltage VLDO Regulator VIN: 1.14V to 3.5V (Boost Enabled), 1.14V to 5.5V (with External 5V), VDO = 0.1V, IQ = 950µA, Stable with 10µF Ceramic Capacitors, 10-Lead MSOP and DFN-10 Packages 3070fa 28 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LT 0510 REV A • PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2009