LINEAR_DIMENSIONS LTC1658CS8PBF

LTC1658
14-Bit Rail-to-Rail
Micropower DAC in MSOP
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DESCRIPTION
FEATURES
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■
■
■
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14-Bit Resolution
8-Lead MSOP Package
Buffered True Rail-to-Rail Voltage Output
3V or 5V Single Supply Operation
Very Low Power: ICC(TYP) = 270µA
Power-On Reset
3-Wire Cascadable Serial Interface is Compatible
with SPI and MICROWIRETM
Maximum DNL Error: 1LSB
Low Cost
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APPLICATIONS
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The LTC®1658 is a single supply, rail-to-rail voltage output, 14-bit digital-to-analog converter (DAC) in an 8-lead
MSOP package. It includes an output buffer amplifier and
an easy-to-use 3-wire cascadable serial interface.
The LTC1658 output swings from 0V to VREF. The REF pin
can be tied to VCC for rail-to-rail output swing. The LTC1658
operates from a single 2.7V to 5.5V supply. The typical
power supply current is 270µA.
The low power supply current makes the LTC1658 ideal
for battery-powered applications. The space saving MSOP
provides the smallest 14-bit DAC system available.
, LTC and LT are registered trademarks of Linear Technology Corporation.
MICROWIRE is a trademark of National Semiconductor Corporation.
Digital Calibration
Industrial Process Control
Automatic Test Equipment
Cellular Telephones
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TYPICAL APPLICATION
Functional Block Diagram: 14-Bit Rail-to-Rail DAC
8
6
VCC
0.8
2 DIN
1 CLK
µP
3 CS/LD
1.0
REF
+
16-BIT
SHIFT
REG
AND
DAC
LATCH
14
14-BIT
DAC
–
VOUT
7
RAIL-TO-RAIL
VOLTAGE
OUTPUT
4 DOUT
TO
OTHER
DACS
0.6
DNL ERROR (LSB)
2.7V TO 5.5V
Differential Nonlinearity
vs Input Code
0.4
0.2
0
– 0.2
– 0.4
– 0.6
POWER-ON
RESET
– 0.8
GND
5
– 1.0
1658 TA01
0
4096
8192
CODE
12288
16383
1658 TA02
1
LTC1658
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ABSOLUTE MAXIMUM RATINGS
(Note 1)
VCC to GND .............................................. – 0.5V to 7.5V
TTL Input Voltage .................................... – 0.5V to 7.5V
VREF ..........................................................– 0.5V to 7.5V
VOUT ........................................... – 0.5V to (VCC + 0.5V)
Junction Temperature .......................... – 65°C to 125°C
Operating Temperature Range
Commercial ............................................ 0°C to 70°C
Industrial ............................................. –40°C to 85°C
Storage Temperature Range ................ – 65°C to 150°C
Lead Temperature (Soldering, 10 sec)................. 300°C
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
CLK
DIN
CS/LD
DOUT
1
2
3
4
8
7
6
5
VCC
VOUT
REF
GND
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 250°C/W
LTC1658CMS8
LTC1658IMS8
ORDER PART
NUMBER
TOP VIEW
CLK 1
8
VCC
DIN 2
7
VOUT
CS/LD 3
6
REF
DOUT 4
5
GND
MS8 PART MARKING
LTCW
LTFW
N8 PACKAGE
8-LEAD PDIP
S8 PACKAGE
8-LEAD PLASTIC SO
LTC1658CN8
LTC1658IN8
LTC1658CS8
LTC1658IS8
S8 PART MARKING
TJMAX = 125°C, θJA = 100°C/W(N8)
TJMAX = 125°C, θJA = 150°C/W(S8)
1658
1658I
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
VCC = 2.7V to 5.5V, VOUT unloaded, REF ≤ VCC, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DAC
Resolution
Monotonicity
DNL
INL
14
●
14
Bits
Bits
VREF ≤ VCC – 0.1V (Note 2)
●
±1.0
LSB
Integral Nonlinearity
VREF ≤ VCC – 0.1V (Note 2)
●
±8.0
LSB
Zero Scale Error
TA = 25°C, N8 and S8 Package
TA = TMIN to TMAX, N8 and S8 Package
TA = TMIN to TMAX, MSOP Package
●
●
1.5
4.0
7.0
mV
mV
mV
TA = 25°C, N8 and S8 Package, (Note 7)
TA = TMIN to TMAX, N8 and S8 Package, (Note 7)
TA = TMIN to TMAX, MSOP Package, (Note 7)
●
●
±1.5
±4.0
±7.0
mV
mV
mV
Differential Nonlinearity
Offset Error
VOSTC
●
±5
Offset Error Temperature
Coefficient
Gain Error
µV/°C
±20
●
±2.5
Gain Error Drift
LSB
ppm/°C
Power Supply
VCC
Positive Supply Voltage
For Specified Performance
●
ICC
Supply Current
2.7V ≤ VCC ≤ 5.5V (Note 4)
●
Short-Circuit Current Low
VOUT Shorted to GND
Short-Circuit Current High
VOUT Shorted to VCC
2.7
5.5
V
270
550
µA
●
55
120
mA
●
55
120
mA
Op Amp DC Performance
2
LTC1658
ELECTRICAL CHARACTERISTICS
VCC = 2.7V to 5.5V, VOUT unloaded, REF ≤ VCC, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
MIN
Output Impedance to GND
Input Code = 0
●
Output Line Regulation
Input Code = 16383, VCC = 2.7V to 5.5V, REF = 2.5V
●
TYP
MAX
UNITS
70
200
Ω
1.5
mV/V
AC Performance
Voltage Output Slew Rate
Voltage Output Settling Time
●
0.35
(Note 3) to ±0.5LSB
Digital Feedthrough
1.0
V/µs
12
µs
0.3
nV • s
Reference Input
RIN
REF Input Resistance
●
30
VREF
REF Input Range
(Notes 5, 6)
●
0
60
kΩ
VIH
Digital Input High Voltage
VCC = 5V
●
2.4
VIL
Digital Input Low Voltage
VCC = 5V
●
VOH
Digital Output High Voltage
VCC = 5V, IOUT = – 1mA, DOUT Only
●
VOL
Digital Output Low Voltage
VCC = 5V, IOUT = 1mA, DOUT Only
●
VIH
Digital Input High Voltage
VCC = 3V
●
VIL
Digital Input Low Voltage
VCC = 3V
●
VOH
Digital Output High Voltage
VCC = 3V, IOUT = – 1mA, DOUT Only
●
VOL
Digital Output Low Voltage
VCC = 3V, IOUT = 1mA, DOUT Only
●
0.4
V
ILEAK
Digital Input Leakage
VIN = GND to VCC
●
±10
µA
CIN
Digital Input Capacitance
(Note 6)
●
10
pF
VCC
V
Digital I/O
V
0.8
VCC – 0.7
V
V
0.4
2.0
V
V
0.6
VCC – 0.7
V
V
Switching (VCC = 4.5V to 5.5V)
t1
DIN Valid to CLK Setup
●
40
ns
t2
DIN Valid to CLK Hold
●
0
ns
t3
CLK High Time
(Note 6)
●
40
ns
t4
CLK Low Time
(Note 6)
●
40
ns
t5
CS/LD Pulse Width
(Note 6)
●
50
ns
t6
LSB CLK to CS/LD
(Note 6)
●
40
ns
t7
CS/LD Low to CLK
(Note 6)
●
20
t8
DOUT Output Delay
CLOAD = 15pF
●
5
t9
CLK Low to CS/LD Low
(Note 6)
●
20
ns
ns
100
ns
Switching (VCC = 2.7V to 5.5V)
t1
DIN Valid to CLK Setup
●
60
ns
t2
DIN Valid to CLK Hold
●
0
ns
t3
CLK High Time
(Note 6)
●
60
ns
t4
CLK Low Time
(Note 6)
●
60
ns
t5
CS/LD Pulse Width
(Note 6)
●
80
ns
t6
LSB CLK to CS/LD
(Note 6)
●
60
ns
t7
CS/LD Low to CLK
(Note 6)
●
30
ns
t8
DOUT Output Delay
CLOAD = 15pF
●
10
t9
CLK Low to CS/LD Low
(Note 6)
●
30
150
ns
ns
3
LTC1658
ELECTRICAL CHARACTERISTICS
The ● denotes specifications which apply over the full operating
temperature range.
Note 1: Absolute Maximum Ratings are those values beyond which the life
a device may be impaired.
Note 2: Nonlinearity is defined from code 50 to code 16383 (full scale).
See Applications Information.
Note 3: DAC switched between code 16383 and code 50.
Note 4: Digital inputs at 0V or VCC.
Note 5: VOUT can only swing from (GND + VOS) to (VCC – VOS) when
output is unloaded. See Applications Information.
Note 6: Guaranteed by design. Not subject to test.
Note 7: Measured at code 50.
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TYPICAL PERFOR A CE CHARACTERISTICS
Differential Nonlinearity (DNL) vs
Input Code
1.0
4
0.8
3
0.6
2
0.4
1
0
–1
–2
3
ALL DIGITAL INPUTS
TIED TOGETHER
0.2
0
–0.2
–0.4
–3
–0.6
–4
–0.8
0
4096
8192
CODE
0
16383
12288
4096
8192
CODE
Offset Error vs Temperature
125°C
0.7
0.6
0.5
–55°C
0.4
0.3
0.2
0.1
0
0
5
10
LOAD CURRENT (mA)
15
1658 G04
CODE: ALL ZEROS
0.9
–0.5
–1.0
0.8
0.7
OFFSET ERROR (LSB)
OUTPUT PULL-DOWN VOLTAGE (V)
25°C
5
0
1.0
0.8
1
2
3
4
LOGIC INPUT VOLTAGE (V)
1658 G03
Minimum Output Voltage vs
Output Sink Current
1.0
VCC – VOUT (V)
0
1658 G02
Minimum Supply Headroom for
Full Output Swing vs Load Current
∆VOUT < 1LSB
CODE: ALL 1s
VOUT = 4.096V
1
16383
12288
1658 G01
0.9
2
0
–1.0
–5
4
Supply Current vs Logic Input
Voltage
SUPPLY CURRENT (mA)
5
DNL ERROR (LSB)
INL ERROR (LSB)
Integral Nonlinearity (INL) vs
Input Code
125°C
0.6
0.5
25°C
0.4
0.3
–55°C
0.2
–1.5
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
0.1
0
0
5
10
OUTPUT SINK CURRENT (mA)
15
1658 G05
–5.0
–55
–25
5
35
65
TEMPERATURE (°C)
95
125
1658 G06
LTC1658
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TYPICAL PERFOR A CE CHARACTERISTICS
Gain Error vs Temperature
Broadband Noise
5
4
3
GAIN ERROR (LSB)
2
1LSB/DIV
1
0
–1
–2
–3
BW = 1Hz TO
100kHz
–4
–5
–55
–25
5
35
65
TEMPERATURE (°C)
95
200µs/DIV
1658 G08
125
1658 G06
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PIN FUNCTIONS
CLK (Pin 1): The TTL Level Input for the Serial Interface
Clock.
DOUT (Pin 4): Output of the Shift Register Which Becomes
Valid on the Rising Edge of the Serial Clock.
DIN (Pin 2): The TTL Level Input for the Serial Interface
Data. Data on the DIN pin is latched into the shift register
on the rising edge of the serial clock and is loaded MSB
first. The LTC1658 requires a 16-bit word to be loaded in.
The last two bits are don’t cares.
GND (Pin 5): Ground.
CS/LD (Pin 3): The TTL Level Input for the Serial Interface Enable and Load Control. When CS/LD is low the
CLK signal is enabled, so the data can be clocked in.
When CS/LD is pulled high, data is loaded from the shift
register into the DAC register, updating the DAC output.
REF (Pin 6): Reference Input. There is a gain of one from
this pin to the output. When tied to VCC the output will
swing from GND to VCC. The output can only swing to
within it’s offset specification of VCC (see Applicatons
Information).
VOUT (Pin 7): Buffered Rail-to-Rail DAC Output.
VCC (Pin 8): Positive Supply Input. 2.7V ≤ VCC ≤ 5.5V.
5
LTC1658
WU
W
TI I G DIAGRA
t1
t2
t4
t3
t6
t7
CLK
t9
B13
MSB
DIN
B12
CS/LD
DOUT
B11
B0
LSB
BX
DUMMY
BX
DUMMY
t8
B13
PREVIOUS WORD
B12
t5
B11
BX
BX
B13
CURRENT WORD
1658 TD
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DEFI ITIO S
Differential Nonlinearity (DNL): The difference between
the measured change and the ideal 1LSB change for any
two adjacent codes. The DNL error between any two codes
is calculated as follows:
DNL = (∆VOUT – LSB)/LSB
Where ∆VOUT is the measured voltage difference between
two adjacent codes.
Digital Feedthrough: The glitch that appears at the analog
output caused by AC coupling from the digital inputs when
they change state. The area of the glitch is specified in
(nV)(sec).
Gain Error: Gain error is the difference between the output
of a DAC from its ideal full-scale value after offset error has
been adjusted.
Integral Nonlinearity (INL): The deviation from a straight
line passing through the endpoints of the DAC transfer
curve (Endpoint INL). Because the output cannot go below
zero, the linearity is measured between full scale and the
lowest code which guarantees the output will be greater
6
than zero. The INL error at a given input code is calculated
as follows:
INL = [VOUT – VOS – (VFS – VOS)(code/16383)]/LSB
Where VOUT is the output voltage of the DAC measured at
the given input code.
Least Significant Bit (LSB): The ideal voltage difference
between two successive codes.
LSB = VREF/16384
Resolution (n): Defines the number of DAC output states
(2n) that divide the full-scale range. Resolution does not
imply linearity.
Voltage Offset Error (VOS): Nominally, the voltage at the
output when the DAC is loaded with all zeros. A single
supply DAC can have a true negative offset, but the output
cannot go below zero (see Applications Information).
For this reason, single supply DAC offset is measured at
the lowest code that guarantees the output will be greater
than zero.
LTC1658
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OPERATIO
Serial Interface
The data on the DIN input is loaded into the shift register
on the rising edge of the clock. The MSB is loaded first. The
DAC register loads the data from the shift register when
CS/LD is pulled high. The clock is disabled internally when
CS/LD is high. Note: CLK must be low before CS/LD is
pulled low to avoid an extra internal clock pulse. The input
word must be 16 bits wide. The last two bits are don’t
cares.
the chips then the CS/LD signal is pulled high to update all
of them simultaneously.
Voltage Output
The buffered output of the 16-bit shift register is available
on the DOUT pin which swings from GND to VCC.
The LTC1658 rail-to-rail buffered output can source or sink
5mA over the entire operating temperature range while
pulling to within 400mV of the positive supply voltage or
ground. The output swings to within a few millivolts of either supply rail when unloaded and has an equivalent output resistance of 40Ω, at 5V VCC, when driving a load to the
rails. The output can drive 1000pF without going into oscillation.
Multiple LTC1658s may be daisy-chained together by
connecting the DOUT pin to the DIN pin of the next chip
while the clock and CS/LD signals remain common to all
chips in the daisy chain. The serial data is clocked to all of
The output swings from 0V to the voltage at the REF pin,
i.e., there is a gain of 1 from REF to VOUT. Please note, if
REF is tied to VCC the output can only swing to (VCC – VOS).
See Applications Information.
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LTC1658
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APPLICATIONS INFORMATION
Rail-to-Rail Output Considerations
In any rail-to-rail DAC, the output swing is limited to
voltages within the supply range.
If the DAC offset is negative, the output for the lowest
codes limits at 0V as shown in Figure 1b.
(FSE) is positive, the output for the highest codes limits at
VCC as shown in Figure 1c. No full-scale limiting can occur
if VREF is less than VCC – FSE.
Offset and linearity are defined and tested over the region
of the DAC transfer function where no output limiting can
occur.
Similarly, limiting can occur near full scale when the REF
pin is tied to VCC. If VREF = VCC and the DAC full-scale error
VREF = VCC
POSITIVE
FSE
OUTPUT
VOLTAGE
INPUT CODE
(c)
VREF = VCC
OUTPUT
VOLTAGE
0
8192
INPUT CODE
(a)
16383
OUTPUT
VOLTAGE
0V
NEGATIVE
OFFSET
INPUT CODE
(b)
Figure 1. Effects of Rail-to-Rail Operation On a DAC Transfer Curve. (a) Overall Transfer Function (b) Effect of Negative
Offset for Codes Near Zero Scale (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
8
1658 F01
LTC1658
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TYPICAL APPLICATIO S
An Optoisolated 4mA to 20mA Process Controller
VLOOP
3.8V TO 30V
LT®1121-3.3
IN
OUT
237k
1%
20k
60.4k
1%
5k
+
1µF
FROM
OPTOISOLATED
INPUTS
CLK
REF
VCC
DIN
LTC1658
VOUT
+
3.01k
1%
CS/LD
1k
LT1077
Q1
2N3440
–
RS
10Ω
IOUT
3.3V
1658 TA04
OPTOISOLATORS
CLK
DIN
CS/LD
500Ω
3.6k
4N28
CLK
DIN
CS/LD
This circuit shows how to use an LTC1658 to make an
optoisolated digitally controlled 4mA to 20mA process
controller. The controller circuitry, including the
optoisolation, is powered by the loop voltage that can have
a wide range of 3.8V to 30V. The 3.3V output of the
LT1121-3.3 is used for the 4mA offset current and VOUT is
used for the digitally controlled 0mA to 16mA current. RS
is a sense resistor and the op amp modulates the transistor Q1 to provide the 4mA to 20mA current through this
resistor. The potentiometers allow for offset and full-scale
adjustment. The control circuitry dissipates well under the
4mA budget at zero-scale.
9
LTC1658
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TYPICAL APPLICATIO S
A 14-Bit Analog Input/Output Channel for a PC
5V
D1
510Ω
DIFFERENTIAL
INPUT
D2
510Ω 1
510Ω
D3
U1
LTC1417
510Ω 2
3
D4
1µF
4
10µF
5
6
7
8
U2
LTC1658
1
2
3
4
CLK
VCC
DIN
VOUT
CS/LD
DOUT
REF
GND
1µF
AIN +
VCC
AIN –
VSS
VREF
BUSY
VREFCOMP
15
14
13
CONVST
12
RD
AGND
EXTCLKIN
SHDN
SCLK
DGND
CLKOUT
16
11
10
9
DOUT
U3
1/2 74HC74
1µF
8
2
7
4
6
3
D
6
Q
PR
CLR
CK
Q
5
1
6
U4
LT1021-5
C5
47µF
5V
2
C4
150µF
4
5
D6
ANALOG
OUTPUT
U3
1/2 74HC74
12
10
11
D
4
3
2
1
51k SELECT
8
9
6
5
51k DIN
12
Q
PR
CLR
CK
Q
13 51k SCLK
D5
TX
RTS
DTR
9
13
8
5V
11
10
DOUT
CTS
C3
0.1µF
5V
10
1658 TA05
1658 TA05
LTC1658
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PACKAGE DESCRIPTION
Dimensions in inches (millimeters) unless otherwise noted.
MS8 Package
8-Lead Plastic MSOP
(LTC DWG # 05-08-1660)
0.118 ± 0.004*
(3.00 ± 0.102)
0.040 ± 0.006
(1.02 ± 0.15)
0.007
(0.18)
0.034 ± 0.004
(0.86 ± 0.102)
8
7 6
5
0° – 6° TYP
SEATING
PLANE 0.012
(0.30)
0.0256
REF
(0.65)
TYP
0.021 ± 0.006
(0.53 ± 0.015)
0.006 ± 0.004
(0.15 ± 0.102)
0.118 ± 0.004**
(3.00 ± 0.102)
0.192 ± 0.004
(4.88 ± 0.10)
MSOP (MS8) 1197
1
* DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH,
PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
4
2 3
N8 Package
8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
+0.035
0.325 –0.015
8.255
+0.889
–0.381
)
0.045 – 0.065
(1.143 – 1.651)
0.400*
(10.160)
MAX
0.130 ± 0.005
(3.302 ± 0.127)
0.065
(1.651)
TYP
8
7
6
5
1
2
3
4
0.255 ± 0.015*
(6.477 ± 0.381)
0.125
(3.175) 0.020
MIN (0.508)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
0.100 ± 0.010
(2.540 ± 0.254)
N8 1197
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
S8 Package
8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
0.010 – 0.020
× 45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
0.004 – 0.010
(0.101 – 0.254)
8
7
6
5
0°– 8° TYP
0.016 – 0.050
0.406 – 1.270
0.014 – 0.019
(0.355 – 0.483)
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.050
(1.270)
TYP
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
SO8 0996
1
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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3
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LTC1658
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TYPICAL APPLICATION
14-Bit, 3V to 5V Single Supply, Voltage Output DAC
2.7V TO 5.5V
0.1µF
REF
DIN VCC
µP
CLK
LTC1658
VOUT
CS/LD
DOUT
OUTPUT
0V TO REF
GND
TO NEXT DAC FOR
DAISY-CHAINING
1658 TA03
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1257
Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V,
Reference Can Be Overdriven Up to 12V, i.e., FSMAX = 12V
5V to 15V Single Supply, Complete VOUT DAC in
SO-8 Package
LTC1446/LTC1446L
Dual 12-Bit VOUT DACs in SO-8 Package
LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1448
Dual 12-Bit VOUT DAC, VCC: 2.7V to 5.5V
Output Swings from GND to REF. REF Input
Can Be Tied to VCC
LTC1450/LTC1450L
Single 12-Bit VOUT DACs with Parallel Interface
LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1451
Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V,
Internal 2.048V Reference Brought Out to Pin
5V, Low Power Complete VOUT DAC in SO-8 Package
LTC1452
Single Rail-to-Rail 12-Bit VOUT Multiplying DAC, VCC: 2.7V to 5.5V
Low Power, Multiplying VOUT DAC with Rail-to-Rail
Buffer Amplifier in SO-8 Package
LTC1453
Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V
3V, Low Power, Complete VOUT DAC in SO-8 Package
LTC1454/LTC1454L
Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality
LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1456
Single Rail-to-Rail Output 12-Bit DAC with Clear Pin,
Full Scale: 4.095V, VCC: 4.5V to 5.5V
Low Power, Complete VOUT DAC in SO-8
Package with Clear Pin
LTC1458/LTC1458L
Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality
LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V
LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V
LTC1659
Single Rail-to-Rail 12-Bit VOUT DAC in 8-Pin MSOP, VCC: 2.7V to 5.5V
Low Power, Multiplying VOUT DAC in MS8 Package.
Output Swings from GND to REF. REF Input Can Be
Tied to VCC.
References
LT1019
Precision Voltage Reference
Ultralow Drift 5ppm/°C, Initial Accuracy: 0.05%
LT1634
Micropower Precision Reference
Low Drift 10ppm/°C, Initial Accuracy: 0.05%
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Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
1658f LT/TP 0299 4K • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 1998