LTC3564 2.25MHz, 1.25A Synchronous Step-Down Regulator U DESCRIPTIO FEATURES ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The LTC ®3564 is a high efficiency monolithic synchronous buck regulator using a constant frequency, current mode architecture. Supply current during operation is only 20μA, dropping to ≤1μA in shutdown. The 2.5V to 5.5V input voltage range makes the LTC3564 ideally suited for single Li-Ion battery-powered or 3.3V to 5V input voltage applications. 100% duty cycle provides low dropout operation, extending battery life in portable systems. Automatic Burst Mode® operation increases efficiency at light loads, further extending battery runtime. High Efficiency: Up to 96% Very Low Quiescent Current: Only 20μA 1.25A Output Current 2.5V to 5.5V Input Voltage Range 2.25MHz Constant Frequency Operation No Schottky Diode Required Low Dropout Operation: 100% Duty Cycle 0.6V Reference Allows Low Output Voltages Shutdown Mode Draws ≤ 1μA Supply Current Current Mode Operation for Excellent Line and Load Transient Response Overtemperature Protected Low Profile (1mm) ThinSOTTM and 6-Lead (2mm × 3mm) DFN Packages Switching frequency is internally set at 2.25MHz, allowing the use of small surface mount inductors and capacitors. The internal synchronous switch increases efficiency and eliminates the need for an external Schottky diode. Low output voltages are easily supported with the 0.6V feedback reference voltage. The LTC3564 is available in low profile (1mm) ThinSOT and 6-Lead (2mm × 3mm) DFN packages. U APPLICATIO S ■ ■ ■ ■ ■ Cellular Telephones Wireless and DSL Modems Digital Still Cameras Media Players Portable Instruments Point of Load Regulation , LT, LTC and LTM are registered trademarks of Linear Technology Corporation. Burst Mode is a registered trademark of Linear Technology Corporation. ThinSOT is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners. Protected by U.S. Patents including 5481178, 6580258, 6304066, 6498466, 6611131. U ■ TYPICAL APPLICATIO 100 90 10 VOUT = 1.8V 1 CIN 22μF CER VIN SW COUT 22μF CER LTC3564 RUN GND VOUT 1.8V 22pF VFB 634k 316k 3564 TA01a 70 0.1 60 50 0.01 40 0.001 30 20 VIN = 2.7V VIN = 3.6V VIN = 4.2V 10 0 0.1 1 10 100 1000 OUTPUT CURRENT (mA) POWER LOSS (W) 1.1μH VIN EFFICIENCY (%) 80 0.0001 0.00001 10000 3564 TA01b 3564f 1 LTC3564 W W U W ABSOLUTE AXI U RATI GS (Note 1) Input Supply Voltage .................................. – 0.3V to 6V RUN, VFB Voltages ..................................... – 0.3V to VIN SW Voltage (DC) ......................... – 0.3V to (VIN + 0.3V) Operating Junction Temperature Range (Notes 2, 3, 6) ...................................... – 40°C to 125°C Storage Temperature Range ................ – 65°C to 150°C Lead Temperature (Soldering, 10 sec)................. 300°C U U U PI CO FIGURATIO TOP VIEW TOP VIEW VFB 1 6 RUN SW 1 5 RUN 7 PGND 2 5 SGND GND 2 VIN 3 4 VFB VIN 3 4 SW S5 PACKAGE 5-LEAD PLASTIC TSOT-23 TJMAX = 125°C, θJA = 215°C/ W, θJC = 50°C/ W DCB PACKAGE 6-LEAD (2mm × 3mm) PLASTIC DFN TJMAX = 125°C, θJA = 64°C/ W, θJC = 10.6°C/ W EXPOSED PAD (PIN 7) IS SGND, MUST BE SOLDERED TO PCB U W U ORDER I FOR ATIO LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC3564ES5#PBF LTC3564ES5#TRPBF LTCYJ 5-Lead Plastic TSOT-23 –40°C to 125°C LTC3564IS5#PBF LTC3564IS5#TRPBF LTCYJ 5-Lead Plastic TSOT-23 –40°C to 125°C LTC3564EDCB#PBF LTC3564EDCB#TRPBF LDTQ 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C LTC3564IDCB#PBF LTC3564IDCB#TRPBF LDTQ 6-Lead (2mm × 3mm) Plastic DFN –40°C to 125°C Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container. Consult LTC Marketing for information on nonstandard lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating junction temperature range, otherwise specifications are TA = 25°C. VIN = 3.6V unless otherwise specified. SYMBOL PARAMETER CONDITIONS IVFB Feedback Current VFB Regulated Feedback Voltage (Note 4) ΔVFB Reference Voltage Line Regulation VIN = 2.5V to 5.5V (Note 4) IPK Peak Inductor Current VIN = 3V, VFB = 0.5V, Duty Cycle < 35% VLOADREG Output Voltage Load Regulation VIN Input Voltage Range MIN TYP MAX UNITS ±30 nA 0.5880 0.6 0.6120 V 0.04 0.4 2.0 2.5 ● ● 1.5 0.5 ● 2.5 %/V A % 5.5 V 3564f 2 LTC3564 ELECTRICAL CHARACTERISTICS The ● denotes specifications which apply over the full operating junction temperature range, otherwise specifications are TA = 25°C. VIN = 3.6V unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN IS Input DC Bias Current Active Mode Sleep Mode Shutdown (Note 5) VFB = 0.5V or VOUT = 90%, ILOAD = 0A VFB = 0.62V or VOUT = 103%, ILOAD = 0A VRUN = 0V, VIN = 4.2V ● MAX UNITS 300 20 0.1 400 35 1 μA μA μA fOSC Oscillator Frequency VFB = 0.6V or VOUT = 100% 2.25 2.7 MHz RPFET RDS(ON) of P-Channel FET S5 Package DCB Package 0.15 0.15 0.2 Ω Ω RNFET RDS(ON) of N-Channel FET S5 Package DCB Package 0.15 0.15 0.2 Ω Ω ILSW SW Leakage VRUN = 0V, VSW = 0V or 5V, VIN = 5V ±0.01 ±1 μA VRUN RUN Threshold 1 1.5 V IRUN RUN Leakage Current tSOFTSTART Soft-Start Time ● 1.8 TYP 0.3 ● VFB from 10% to 90% Full Scale Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliabilty and lifetime. Note 2: The LTC3564E is guaranteed to meet performance specifications from 0°C to 125°C junction temperature. Specifications over the –40°C to 125°C operating junction termperature range are assured by design, characterization and correlation with statistical process controls. The LTC3564I is guaranteed over the full –40°C to 125°C operating junction temperature range. High junction temperatures degrade operating lifetimes. Operating lifetime is derated at junction temperatures greater than 125°C. 0.6 ±0.01 ±1 μA 0.9 1.2 ms Note 3: TJ is calculated from the ambient temperature TA and power dissipation PD according to the following formula: LTC3564ES5: TJ = TA + (PD)(215°C/W) LTC3564EDCB: TJ = TA + (PD)(64°C/W) Note 4: The LTC3564 is tested in a proprietary test mode. Note 5: Dynamic supply current is higher due to the gate charge being delivered at the switching frequency. Note 6: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specified maximum operating junction temperature may impair device reliability. 3564f 3 LTC3564 U W TYPICAL PERFOR A CE CHARACTERISTICS Efficiency vs Input Voltage IOUT = 100mA 90 90 EFFICIENCY (%) 70 EFFICIENCY (%) IOUT = 1.25A IOUT = 1mA 60 100 VOUT = 1.2V 90 80 80 70 70 EFFICIENCY (%) 100 IOUT = 10mA 60 50 40 20 VOUT = 1.8V 3.5 4.0 4.5 INPUT VOLTAGE (V) 3.0 5.0 0 0.1 5.5 1 10 100 1000 OUTPUT CURRENT (mA) Reference Voltage vs Temperature 0 0.1 10000 605 600 595 590 2.40 2.35 4 2.30 2.25 2.20 2.15 2.10 2.00 –50 –25 125 0.6 0 50 75 25 TEMPERATURE (°C) 100 –4 0.25 0 –0.25 400 600 800 1000 1200 1400 OUTPUT CURRENT (mA) 3564 G07 3.5 4.0 VIN (V) 4.5 5.0 5.5 RDS(ON) vs Input Voltage 0.25 VOUT = 1.8V ILOAD = 400mA 0.20 MAIN SWITCH 0.2 0 0.15 SYNCHRONOUS SWITCH 0.10 –0.2 0.05 –0.4 –0.50 3.0 3564 G06 RDS(ON) (Ω) VOUT ERROR (%) VOUT ERROR (%) –2 –8 2.5 125 0.4 0.75 200 0 Line Regulation VOUT = 1.8V 0 2 3564 G05 Load Regulation 0.50 10000 –6 3564 G04 1.00 10 100 1000 OUTPUT CURRENT (mA) Frequency Variation vs VIN 6 2.05 100 1 3564 G04 FREQUENCY VARIATION (%) OSCILLATOR FREQUENCY (MHz) REFERENCE VOLTAGE (mV) 610 VIN = 2.7V VIN = 3.6V VIN = 4.2V 10 Oscillator Frequency vs Temperature 615 50 25 75 0 TEMPERATURE (°C) 50 40 3564 G02 3564 G01 585 –50 –25 60 20 VIN = 2.7V VIN = 3.6V VIN = 4.2V 10 2.5 VOUT = 1.5V 30 30 IOUT = 0.1mA 50 40 Efficiency vs Output Current Efficiency vs Output Current 100 80 TA = 25°C, VIN = 3.6V, unless otherwise specified. –0.6 0 2.5 3.0 3.5 4.0 4.5 INPUT VOLTAGE (V) 5.0 5.5 3564 G08 2.5 3.0 3.5 4.0 4.5 INPUT VOLTAGE (V) 5.0 5.5 3564 G09 3564f 4 LTC3564 U W TYPICAL PERFOR A CE CHARACTERISTICS RDS(ON) vs Temperature Supply Current vs Supply Voltage Supply Current vs Temperature 35 0.30 0.25 40 35 MAIN SWITCH 0.15 SYNCHRONOUS SWITCH 0.10 SUPPLY CURRENT (μA) SUPPLY CURRENT (μA) 30 0.20 25 20 15 0.05 0 –50 –25 10 50 25 75 0 TEMPERATURE (°C) 100 125 2.5 3.0 3.5 4.0 4.5 SUPPLY VOLTAGE (V) 30 25 20 5.0 5.5 10 –50 –25 50 25 75 0 TEMPERATURE (°C) 3564 G11 Switch Leakage vs Temperature 100 125 3564 G12 Switch Leakage vs Input Voltage 600 2500 SYNCHRONOUS SWITCH MAIN SWITCH 500 RUN = 0V SWITCH LEAKAGE (pA) 2000 400 300 200 MAIN SWITCH 1500 1000 SYNCHRONOUS SWITCH 500 100 0 –50 –25 VIN = 3.6V RUN = VIN ILOAD = 0A 15 3564 G10 SWITCH LEAKAGE (nA) RDS(ON) (Ω) TA = 25°C, VIN = 3.6V, unless otherwise specified. 50 25 75 0 TEMPERATURE (°C) 100 125 3564 G13 0 0 1 2 3 4 INPUT VOLTAGE (V) 5 6 3564 G14 3564f 5 LTC3564 U W TYPICAL PERFOR A CE CHARACTERISTICS Burst Mode Operation TA = 25°C, VIN = 3.6V, unless otherwise specified. Start-Up from Shutdown Start-Up from Shutdown RUN 2V/DIV SW 2V/DIV VOUT 50mV/DIV AC COUPLED RUN 2V/DIV VOUT 1V/DIV VOUT 1V/DIV IL 200mA/DIV IL 1A/DIV IL 500mA/DIV VIN = 3.6V VOUT = 1.8V ILOAD = 40mA 2.5μs/DIV 3564 G15 VIN = 3.6V VOUT = 1.8V ILOAD = 0mA Load Step 400μs/DIV Load Step VOUT 100mV/DIV AC COUPLED IL 1A/DIV IL 1A/DIV ILOAD 1A/DIV ILOAD 1A/DIV 3564 G18 400μs/DIV 3564 G17 Load Step VOUT 100mV/DIV AC COUPLED VIN = 3.6V 20μs/DIV VOUT = 1.8V ILOAD = 0A TO 1.25A VIN = 3.6V VOUT = 1.8V ILOAD = 1.25A 3564 G16 VOUT 100mV/DIV AC COUPLED IL 1A/DIV ILOAD 1A/DIV VIN = 3.6V 20μs/DIV VOUT = 1.8V ILOAD = 50mA TO 1.25A 3564 G19 VIN = 3.6V 20μs/DIV VOUT = 1.8V ILOAD = 0.25A TO 1.25A 3564 G20 3564f 6 LTC3564 U U U PI FU CTIO S (S5/DCB) VFB (Pin 1/Pin 4) : Feedback Pin. Receives the feedback voltage from an external resistive divider across the output. GND (Pin 2/NA): Ground Pin. RUN (Pin 5/Pin 6): Run Control Input. Forcing this pin above 1.5V enables the part. Forcing this pin below 0.3V shuts down the device. In shutdown, all functions are disabled drawing <1μA supply current. Do not leave RUN floating. VIN (Pin 3/Pin 3): Main Supply Pin. Must be closely decoupled to GND, Pin 2, with a 10μF or greater ceramic capacitor. PGND (NA/Pin 2): Main Power Ground Pin. Connect to the (–) terminal of COUT, and (–) terminal of CIN. SW (Pin 4/Pin 1): Switch Node Connection to Inductor. This pin connects to the drains of the internal main and synchronous power MOSFET switches. SGND (NA/Pins 5, 7): The Signal Ground Pin. All small signal components and compensation components should be connected to this ground (see Board Layout Considerations.) W FU CTIO AL DIAGRA U U SLOPE COMP 0.65V OSC OSC VIN FREQ SHIFT – VFB + 0.6V – + – EA 0.52V SLEEP – + BURST S Q R Q RS LATCH VIN RUN RSENSE + ICOMP SWITCHING LOGIC AND BLANKING CIRCUIT ANTISHOOTTHRU SW 0.6V REF + IRCMP – SHUTDOWN GND 3564 FD 3564f 7 LTC3564 U OPERATIO (Refer to Functional Diagram) Main Control Loop Short-Circuit Protection The LTC3564 uses a constant frequency, current mode step-down architecture. Both the main (P-channel MOSFET) and synchronous (N-channel MOSFET) switches are internal. During normal operation, the internal top power MOSFET is turned on each cycle when the oscillator sets the RS latch, and turned off when the current comparator, ICOMP, resets the RS latch. The peak inductor current at which ICOMP resets the RS latch, is controlled by the output of error amplifier EA. When the load current increases, it causes a slight decrease in the feedback voltage, FB, relative to the 0.6V reference, which in turn, causes the EA amplifier’s output voltage to increase until the average inductor current matches the new load current. While the top MOSFET is off, the bottom MOSFET is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator IRCMP, or the beginning of the next clock cycle. When the output is shorted to ground, the inductor current may exceed the maximum inductor peak current if not allowed enough time to decay. To prevent the inductor current from running away, the bottom N-channel MOSFET is allowed to stay on for more than one cycle, thereby allowing the inductor current time to decay. Burst Mode Operation The LTC3564 is capable of Burst Mode operation in which the internal power MOSFETs operate intermittently based on load demand. In Burst Mode operation, the peak current of the inductor is set to approximately 180mA regardless of the output load. Each burst event can last from a few cycles at light loads to almost continuously cycling with short sleep intervals at moderate loads. In between these burst events, the power MOSFETs and any unneeded circuitry are turned off, reducing the quiescent current to 20μA. In this sleep state, the load current is being supplied solely from the output capacitor. As the output voltage droops, the EA amplifier’s output rises above the sleep threshold signaling the BURST comparator to trip and turn the top MOSFET on. This process repeats at a rate that is dependent on the load demand. Dropout Operation As the input supply voltage decreases to a value approaching the output voltage, the duty cycle increases toward the maximum on-time. Further reduction of the supply voltage forces the main switch to remain on for more than one cycle until it reaches 100% duty cycle. The output voltage will then be determined by the input voltage minus the voltage drop across the P-channel MOSFET and the inductor. An important detail to remember is that at low input supply voltages, the RDS(ON) of the P-channel switch increases (see Typical Performance Characteristics). Therefore, the user should calculate the power dissipation when the LTC3564 is used at 100% duty cycle with low input voltage (See Thermal Considerations in the Applications Information section). Slope Compensation and Inductor Peak Current Slope compensation provides stability in constant frequency architectures by preventing subharmonic oscillations at high duty cycles. It is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. Normally, this results in a reduction of maximum inductor peak current for duty cycles > 40%. However, the LTC3564 uses a patented scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. 3564f 8 LTC3564 W U U SW U VIN APPLICATIO S I FOR ATIO The DC current rating of the inductor should be at least equal to the maximum load current plus half the ripple current to prevent core saturation. Thus, a 1.5A rated inductor should be enough for most applications (1.25A + 250mA). For better efficiency, choose a low DC-resistance inductor. L VIN CIN CF LTC3564 R2 VFB RUN VOUT COUT 3564 F01 R1 GND Figure 1. LTC3564 General Schematic The basic LTC3564 application circuit is shown in Figure 1. External component selection is driven by the load requirement and begins with the selection of L followed by CIN and COUT. Inductor Selection For most applications, the value of the inductor will fall in the range of 0.47μH to 2.2μH. Its value is chosen based on the desired ripple current. Large value inductors lower ripple current and small value inductors result in higher ripple currents. Higher VIN or VOUT also increases the ripple current as shown in equation 1. A reasonable starting point for setting ripple current is ΔIL = 500mA (40% of 1.25A). ΔIL = ⎛ ⎞ V 1 VOUT ⎜ 1− OUT ⎟ VIN ⎠ ( f )(L ) ⎝ (1) The inductor value also has an effect on Burst Mode operation. The transition to low current operation begins when the inductor current peaks fall to approximately 300mA. Lower inductor values (higher ΔIL) will cause this to occur at lower load currents, which can cause a dip in efficiency in the upper range of low current operation. In Burst Mode operation, lower inductance values will cause the burst frequency to increase. Inductor Core Selection Different core materials and shapes will change the size/ current and price/current relationship of an inductor. Toroid or shielded pot cores in ferrite or permalloy materials are small and don’t radiate much energy, but generally cost more than powdered iron core inductors with similar electrical characteristics. The choice of which style inductor to use often depends more on the price vs size requirements and any radiated field/EMI requirements than on what the LTC3564 requires to operate. Table 1 shows some typical surface mount inductors that work well in LTC3564 applications. Table 1. Representative Surface Mount Inductors MANUFATURER VALUE (μH) MAX DC CURRENT (A) DCR (mΩ) HEIGHT (mm) A915AY-1R1M-DC53LC 1.1 3.25 16 3 1070AS-1R0N-DB3020C 1 1.9 47 2 CDRH4D18C/LD-1R1 1.1 2.1 24 2 CDRH3D14-1R2 1.2 2.2 36 1.5 1 2.2 40 1.2 CDRH2D18/HP-2R2 2.2 1.6 48 2 FDK MIPW3226D0R9M 0.9 1.4 70 1 Coilcraft LPO6610-122ML 1.2 2.1 80 1 LPS4018-222ML 2.2 2.5 70 1.8 IHLP1616ABERR47M01 0.47 5 20 1.2 IHLP1616ABER1R0M01 1 4 45 1.2 Toko Sumida PART NUMBER CR5D11-1R0 Vishay 3564f 9 LTC3564 U W U U APPLICATIO S I FOR ATIO CIN and COUT Selection In continuous mode, the source current of the top MOSFET is a square wave of duty cycle VOUT/VIN. To prevent large voltage transients, a low ESR input capacitor sized for the maximum RMS current must be used. The maximum RMS capacitor current is given by: 1/ 2 VOUT (VIN − VOUT )] [ CIN required IRMS ≅ IOMAX VIN This formula has a maximum at VIN = 2VOUT, where IRMS = IOUT/2. This simple worst-case condition is commonly used for design because even significant deviations do not offer much relief. Note that the capacitor manufacturer’s ripple current ratings are often based on 2000 hours of life. This makes it advisable to further derate the capacitor, or choose a capacitor rated at a higher temperature than required. Always consult the manufacturer if there is any question. The selection of COUT is driven by the required effective series resistance (ESR). Typically, once the ESR requirement for COUT has been met, the RMS current rating generally far exceeds the IRIPPLE(P-P) requirement. The output ripple ΔVOUT is determined by: ⎛ 1 ⎞ ΔVOUT ≅ ΔIL ⎜ ESR + ⎟ ⎝ 8fC OUT ⎠ where f = operating frequency, COUT = output capacitance and ΔIL = ripple current in the inductor. For a fixed output voltage, the output ripple is highest at maximum input voltage since ΔIL increases with input voltage. Aluminum electrolytic and dry tantalum capacitors are both available in surface mount configurations. In the case of tantalum, it is critical that the capacitors are surge tested for use in switching power supplies. An excellent choice is the AVX TPS series of surface mount tantalum capacitors. These are specially constructed and tested for low ESR so they give the lowest ESR for a given volume. Other capacitor types include Sanyo POSCAP, Kemet T510 and T495 series, and Sprague 593D and 595D series. Consult the manufacturer for other specific recommendations. Using Ceramic Input and Output Capacitors Higher values, lower cost ceramic capacitors are now becoming available in smaller case sizes. Their high ripple current, high voltage rating and low ESR make them ideal for switching regulator applications. Because the LTC3564’s control loop does not depend on the output capacitor’s ESR for stable operation, ceramic capacitors can be used freely to achieve very low output ripple and small circuit size. However, care must be taken when ceramic capacitors are used at the input and the output. When a ceramic capacitor is used at the input and the power is supplied by a wall adapter through long wires, a load step at the output can induce ringing at the input, VIN. At best, this ringing can couple to the output and be mistaken as loop instability. At worst, a sudden inrush of current through the long wires can potentially cause a voltage spike at VIN, large enough to damage the part. When choosing the input and output ceramic capacitors, choose the X5R or X7R dielectric formulations. These dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size. 3564f 10 LTC3564 U W U U APPLICATIO S I FOR ATIO 1 Output Voltage Programming ⎛ R2 ⎞ VOUT = 0.6 V ⎜ 1 + ⎟ ⎝ R1⎠ (2) The external resistive divider is connected to the output, allowing remote voltage sensing as shown in Figure 2. 0.6V ≤ VOUT ≤ 5.5V R2 0.1 POWER LOSS (W) In the adjustable version, the output voltage is set by a resistive divider according to the following formula: VIN = 3.6V 0.01 0.001 0.0001 0.1 VOUT = 1.2V VOUT = 1.5V VOUT = 1.8V 1 10 100 1000 LOAD CURRENT (A) 10000 3564 F03 VFB LTC3564 Figure 3. Power Lost vs Load Current R1 GND 3564 F02 Figure 2. Setting the LTC3564 Output Voltage Efficiency Considerations The efficiency of a switching regulator is equal to the output power divided by the input power times 100%. It is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. Efficiency can be expressed as: Efficiency = 100% – (L1 + L2 + L3 + ...) where L1, L2, etc. are the individual losses as a percentage of input power. Although all dissipative elements in the circuit produce losses, two main sources usually account for most of the losses in LTC3564 circuits: VIN quiescent current and I2R losses. The VIN quiescent current loss dominates the efficiency loss at very low load currents whereas the I2R loss dominates the efficiency loss at medium to high load currents. In a typical efficiency plot, the efficiency curve at very low load currents can be misleading since the actual power lost is of no consequence as illustrated in Figure 3. 1. The VIN quiescent current is due to two components: the DC bias current as given in the electrical characteristics and the internal main switch and synchronous switch gate charge currents. The gate charge current results from switching the gate capacitance of the internal power MOSFET switches. Each time the gate is switched from high to low to high again, a packet of charge, dQ, moves from VIN to ground. The resulting dQ/dt is the current out of VIN that is typically larger than the DC bias current. In continuous mode, IGATECHG = f(QT + QB) where QT and QB are the gate charges of the internal top and bottom switches. Both the DC bias and gate charge losses are proportional to VIN and thus their effects will be more pronounced at higher supply voltages. 2. I2R losses are calculated from the resistances of the internal switches, RSW, and external inductor RL. In continuous mode, the average output current flowing through inductor L is “chopped” between the main switch and the synchronous switch. Thus, the series resistance looking into the SW pin is a function of both top and bottom MOSFET RDS(ON) and the duty cycle (DC) as follows: RSW = (RDS(ON)TOP)(DC) + (RDS(ON)BOT)(1 – DC) 3564f 11 LTC3564 U W U U APPLICATIO S I FOR ATIO The RDS(ON) for both the top and bottom MOSFETs can be obtained from the Typical Performance Characteristics curves. Thus, to obtain I2R losses, simply add RSW to RL and multiply the result by the square of the average output current. Other losses including CIN and COUT ESR dissipative losses and inductor core losses which generally account for less than 2% total additional loss. Thermal Considerations In most applications the LTC3564 does not dissipate much heat due to its high efficiency. But, in applications where the LTC3564 is running at high ambient temperature with low supply voltage and high duty cycles, such as in dropout, the heat dissipated may exceed the maximum junction temperature of the part. If the junction temperature reaches approximately 150°C, both power switches will be turned off and the SW node will become high impedance. To avoid the LTC3564 from exceeding the maximum junction temperature, the user will need to do some thermal analysis. The goal of the thermal analysis is to determine whether the power dissipated exceeds the maximum junction temperature of the part. The temperature rise is given by: TR = (PD)(θJA) where PD is the power dissipated by the regulator and θJA is the thermal resistance from the junction of the die to the ambient temperature. The junction temperature, TJ, is given by: T J = TA + TR where TA is the ambient temperature. As an example, consider the LTC3564 in dropout at an input voltage of 2.7V, a load current of 1.2A and an ambient temperature of 70°C. From the typical perfor- mance graph of switch resistance, the RDS(ON) of the P-channel switch at 70°C is approximately ~0.2Ω. Therefore, power dissipated by the part is: PD = ILOAD2 • RDS(ON) = 288mW For the SOT-23 package, the θJA is 215°C/ W. Thus, the junction temperature of the regulator is: TJ = 70°C + (0.288)(215) = 131.9°C which is above the maximum junction temperature of 125°C. Note that at higher supply voltages, the junction temperature is lower due to reduced switch resistance (RDS(ON)). Checking Transient Response The regulator loop response can be checked by looking at the load transient response. Switching regulators take several cycles to respond to a step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to (ΔILOAD • ESR), where ESR is the effective series resistance of COUT. ΔILOAD also begins to charge or discharge COUT, which generates a feedback error signal. The regulator loop then acts to return VOUT to its steadystate value. During this recovery time VOUT can be monitored for overshoot or ringing that would indicate a stability problem. For a detailed explanation of switching control loop theory, see Application Note 76. A second, more severe transient is caused by switching in loads with large (>1μF) supply bypass capacitors. The discharged bypass capacitors are effectively put in parallel with COUT, causing a rapid drop in VOUT. No regulator can deliver enough current to prevent this problem if the load switch resistance is low and it is driven quickly. The only solution is to limit the rise time of the switch drive so that the load rise time is limited to approximately (25 • CLOAD). Thus, a 10μF capacitor charging to 3.3V would require a 250μs rise time, limiting the charging current to about 130mA. 3564f 12 LTC3564 U U W U APPLICATIO S I FOR ATIO R1 1 VFB RUN 5 LTC3564 2 R2 GND CIN 3 VIN VIN SW – CFWD L1 4 COUT + VOUT 3564 F04a BOLD LINES INDICATE HIGH CURRENT PATH Figure 4a. LTC3564 TSOT-23 Layout Diagram CFWD R2 L1 VOUT + – COUT 1 SW RUN 6 LTC3564 2 PGND SGND 5 CIN VIN R1 3 VIN VFB 4 3564 F04b BOLD LINES INDICATE HIGH CURRENT PATH Figure 4b. LTC3564 DFN Layout Diagram 3564f 13 LTC3564 U U W U APPLICATIO S I FOR ATIO VIA TO GND VIN R1 VIA TO VIN VIA TO VOUT PIN 1 R2 CFWD LTC3564 VOUT SW CIN L1 COUT GND 3564 F05a Figure 5a. LTC3564 TSOT-23 Suggested Layout VOUT COUT L1 VIA TO VIN SW 2 SGND 6 1 PGND 7 5 R1 3 4 VFB CIN R2 CFWD VIN VIA TO VOUT 3564 F05b Figure 5b. LTC3564 DFN Suggested Layout 3564f 14 LTC3564 U U W U APPLICATIO S I FOR ATIO PC Board Layout Checklist When laying out the printed circuit board, the following checklist should be used to ensure proper operation of the LTC3564. These items are also illustrated graphically in Figures 4 and 5. Check the following in your layout: 1. The power traces, consisting of the GND trace, the SW trace and the VIN trace should be kept short, direct and wide. 2. Does the VFB pin connect directly to the feedback resistors? The resistive divider R1/R2 must be connected between the (+) plate of COUT and ground. 3. Does the (+) plate of CIN connect to VIN as closely as possible? This capacitor provides the AC current to the internal power MOSFETs. and high load currents is important. Output voltage is 2.5V. With this information we can calculate L using equation (1), L= ⎛ V ⎞ 1 VOUT ⎜ 1 − OUT ⎟ ( f)(ΔIL ) ⎝ VIN ⎠ (3) Substituting VOUT = 2.5V, VIN = 4.2V, ΔIL = 500mA and f = 2.25MHz in equation (3) gives: L= 2.5V ⎛ 2 . 5V ⎞ 1− = 0 . 9μH H 2.25MHz(500mA) ⎜⎝ 4 . 2V ⎟⎠ A 1μH or 1.1μH inductor works well for this application. For best efficiency choose a 1.5A or greater inductor with less than 0.1Ω series resistance. 5. Keep the (–) plates of CIN and COUT as close as possible. CIN will require an RMS current rating of at least 0.6A ≅ ILOAD(MAX)/2 at temperature and COUT will require an ESR of less than 0.125Ω. In most cases, a ceramic capacitor will satisfy this requirement. Design Example For the feedback resistors, choose R1 = 316k. R2 can then be calculated from equation (2) to be: 4. Keep the switching node, SW, away from the sensitive VFB node. As a design example, assume the LTC3564 is used in a single lithium-ion battery-powered cellular phone application. The VIN will be operating from a maximum of 4.2V down to about 2.7V. The load current requirement is a maximum of 1.25A but most of the time it will be in standby mode, requiring only 2mA. Efficiency at both low ⎛V ⎞ R2 = ⎜ OUT − 1⎟ R1 = 1000k ⎝ 0.6 ⎠ Figure 6 shows the complete circuit along with its efficiency curve. 100 95 VIN 2.7V TO 4.2V 3 CIN** 22μF CER VIN SW 4 1.1μH* 22pF COUT** 22μF CER LTC3564 5 VFB RUN GND 2 VOUT 2.5V 1 1M 316k 3564 F06a *TOKO A915AY-1R1M (D53LC SERIES) ** TAIYO YUDEN JMK316BJ226ML Figure 6a. Typical Application EFFICIENCY (%) 90 85 80 75 70 65 VIN = 2.7V VIN = 3.6V VIN = 4.2V VOUT = 2.5V 60 1 0.1 10 100 OUTPUT CURRENT (mA) 1000 3564 F06b Figure 6b. Efficiency vs Output Current 3564f 15 LTC3564 U TYPICAL APPLICATIO S Single Li-Ion 1.8V/1.25A Regulator for High Efficiency and Small Footprint VIN 2.7V TO 5.5V 4 CIN** 10μF CER VIN SW 3 1μH* COUT† 22μF CER LTC3564 1 VFB RUN GND 2 VOUT 1.8V 22pF 5 806k *MURATA LQH32CN2R2M33 ** TAIYO YUDEN JMK316BJ106ML † TAIYO YUDEN JMK316BJ226ML-BR 3564 TA02a 402k 100 90 VOUT 100mV/DIV AC COUPLED EFFICIENCY (%) 80 70 IL 1A/DIV 60 50 ILOAD 1A/DIV 40 30 20 10 VIN = 2.7V VIN = 3.6V VIN = 4.2V VOUT = 1.8V 0 1 10 100 1000 0.1 OUTPUT CURRENT (mA) VIN = 3.6V 20μs/DIV VOUT = 1.8V ILOAD = 100mA TO 1.25A 3564 TA02c 10000 3564 TA02b 3564f 16 LTC3564 U TYPICAL APPLICATIO S Single Li-Ion 1.5V/1.25A Regulator for High Efficiency and Low Profile, <1mm Height VIN 2.7V TO 5.5V 4 CIN** 10μF CER VIN SW 3 0.9μH* VOUT 1.5V 22pF COUT** 10μF×2 CER LTC3564 1 VFB RUN GND 2 5 604k 402k *FDK MIPW3226D0R9M **TAIYO YUDEN JMK107BJ106MA 3564 TA03a 100 90 VOUT 100mV/DIV AC COUPLED EFFICIENCY (%) 80 70 IL 1A/DIV 60 50 ILOAD 1A/DIV 40 30 20 10 VIN = 2.7V VIN = 3.6V VIN = 4.2V VOUT = 1.5V 0 1 10 100 1000 0.1 OUTPUT CURRENT (mA) VIN = 3.6V 20μs/DIV VOUT = 1.5V ILOAD = 0.3A TO 1.25A 3564 TA04c 10000 3564 TA03b 3564f 17 LTC3564 U PACKAGE DESCRIPTIO S5 Package 5-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1635) 0.62 MAX 0.95 REF 2.90 BSC (NOTE 4) 1.22 REF 1.4 MIN 3.85 MAX 2.62 REF 2.80 BSC 1.50 – 1.75 (NOTE 4) PIN ONE RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.30 – 0.45 TYP 5 PLCS (NOTE 3) 0.95 BSC 0.80 – 0.90 0.20 BSC 0.01 – 0.10 1.00 MAX DATUM ‘A’ 0.30 – 0.50 REF 0.09 – 0.20 (NOTE 3) NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 1.90 BSC S5 TSOT-23 0302 REV B 3564f 18 LTC3564 U PACKAGE DESCRIPTIO DCB Package 6-Lead Plastic DFN (2mm × 3mm) (Reference LTC DWG # 05-08-1715 Rev A) 0.70 ±0.05 3.55 ±0.05 1.65 ±0.05 (2 SIDES) 2.15 ±0.05 PACKAGE OUTLINE 0.25 ± 0.05 0.50 BSC 1.35 ±0.05 (2 SIDES) RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS R = 0.115 TYP 2.00 ±0.10 (2 SIDES) R = 0.05 TYP 3.00 ±0.10 (2 SIDES) 0.40 ± 0.10 4 6 1.65 ± 0.10 (2 SIDES) PIN 1 NOTCH R0.20 OR 0.25 × 45° CHAMFER PIN 1 BAR TOP MARK (SEE NOTE 6) 3 0.200 REF 0.75 ±0.05 1 (DCB6) DFN 0405 0.25 ± 0.05 0.50 BSC 1.35 ±0.10 (2 SIDES) 0.00 – 0.05 BOTTOM VIEW—EXPOSED PAD NOTE: 1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (TBD) 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE 3564f Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 19 LTC3564 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC3405/LTC3405A 300mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converters 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 20μA, ISD = <1μA, ThinSOT Package LTC3406/LTC3406B 600mA (IOUT), 1.5MHz, Synchronous Step-Down DC/DC Converters 96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20μA, ISD = <1μA, ThinSOT Package LTC3407/LTC3407-2 Dual 600mA/800mA (IOUT), 1.5MHz/2.25MHz, Synchronous Step-Down DC/DC Converters 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, ISD = <1μA, MS10E, DFN Packages LTC3409 600mA (IOUT), 1.7MHz/2.6MHz, Synchronous Step-Down DC/DC Converter 96% Efficiency, VIN: 1.6V to 5.5V, VOUT(MIN) = 0.6V, IQ = 65μA, ISD = <1μA, DFN Package LTC3410/LTC3410B 300mA (IOUT), 2.25MHz, Synchronous Step-Down DC/DC Converters 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 26μA, ISD = <1μA, SC70 Package LTC3411 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA, ISD = <1μA, MS10, DFN Packages LTC3412 2.5A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA, ISD = <1μA, TSSOP-16E Package LTC3441/LTC3442 LTC3443 1.2A (IOUT), 2MHz, Synchronous Buck-Boost DC/DC Converters 95% Efficiency, VIN: 2.4V to 5.5V, VOUT(MIN): 2.4V to 5.25V, IQ = 50μA, ISD = <1μA, DFN Package LTC3531/LTC3531-3 LTC3531-3.3 200mA (IOUT), 1.5MHz, Synchronous Buck-Boost DC/DC Converters 95% Efficiency, VIN: 1.8V to 5.5V, VOUT(MIN): 2V to 5V, IQ = 16μA, ISD = <1μA, ThinSOT, DFN Packages LTC3532 500mA (IOUT), 2MHz, Synchronous Buck-Boost DC/DC Converter 95% Efficiency, VIN: 2.4V to 5.5V, VOUT(MIN): 2.4V to 5.25V, IQ = 35μA, ISD = <1μA, MS10, DFN Packages LTC3542 500mA (IOUT), 2.25MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN): 0.6V, IQ = 26μA, ISD = <1μA, ThinSOT, 2 × 2 DFN Packages LTC3548/LTC3548-1 LTC3548-2 Dual 400mA/800mA (IOUT), 2.25MHz, Synchronous Step-Down DC/DC Converters 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA, ISD = <1μA, MS10E, DFN Packages LTC3560 800mA (IOUT), 2.25MHz, Synchronous Step-Down DC/DC Converters 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 16μA, ISD = <1μA, ThinSOT Package LTC3561 1.25A (IOUT), 4MHz, Synchronous Step-Down DC/DC Converter 95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 240μA, ISD = <1μA, DFN Package 3564f 20 Linear Technology Corporation LT 0608 • PRINTED IN USA 1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2008