M50FW002 2 Mbit (256Kb x8, Boot Block) 3V Supply Firmware Hub Flash Memory PRELIMINARY DATA FEATURES SUMMARY ■ SUPPLY VOLTAGE Figure 1. Packages – VCC = 3 V to 3.6 V for Program, Erase and Read Operations – VPP = 12 V for Fast Program and Fast Erase (optional) ■ TWO INTERFACES – Firmware Hub (FWH) Interface for embedded operation with PC Chipsets – Address/Address Multiplexed (A/A Mux) Interface for programming equipment compatibility ■ FIRMWARE HUB (FWH) HARDWARE INTERFACE MODE PLCC32 (K) – 5 Signal Communication Interface supporting Read and Write Operations – Hardware Write Protect Pins for Block Protection – Register Based Read and Write Protection – 5 Additional General Purpose Inputs for platform design flexibility – Synchronized with 33MHz PCI clock – Multi-byte Read Operation (1-byte, 16-byte, 32-byte) ■ PROGRAMMING TIME ■ ELECTRONIC SIGNATURE – 10 µs typical – Manufacturer Code: 20h – Quadruple Byte Programming Option – Device Code: 29h ■ 7 MEMORY BLOCKS – 1 Boot Block (Top Location) – 4 Main Blocks and 2 Parameter Blocks ■ PROGRAM/ERASE CONTROLLER – Embedded Byte Program, Block Erase and Chip Erase algorithms – Status Register Bits ■ PROGRAM and ERASE SUSPEND ■ FOR USE in PC BIOS APPLICATIONS May 2002 This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice. 1/39 M50FW002 TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Firmware Hub (FWH) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Address/Address Multiplexed (A/A Mux) Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Supply Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Firmware Hub (FWH) Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 FWH Bus Read Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 FWH Bus Write Field Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Address/Address Multiplexed (A/A Mux) Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 A/A Mux Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Manufacturer and Device Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS . . . . . . . . . . . . . . . . . . . . . . 17 Lock Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Firmware Hub (FWH) General Purpose Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Manufacturer Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Firmware Hub Register Configuration Map (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Lock Register Bit Definitions(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 General Purpose Input Register Definition(1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 AC Measurement Conditions (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 AC Measurement Conditions (A/A Mux Interface). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Device Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Clock Characteristics (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 AC Signal Timing Characteristics (FWH Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Program and Erase Times. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 2/39 M50FW002 Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Read AC Characteristics (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Write AC Characteristics (A/A Mux Interface) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data . . . . . . . . . . . . . . . . . 36 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 3/39 M50FW002 SUMMARY DESCRIPTION The M50FW002 is a 2 Mbit (256Kb x8) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (3.0 to 3.6V) supply. For fast programming and fast erasing in production lines an optional 12V power supply can be used to reduce the programming and the erasing times. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Blocks can be protected individually to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The device features an asymmetrical blocked architecture. The device has an array of 7 blocks: ■ 1 Boot Block of 16 KByte ■ 2 Parameter Blocks of 8 KByte each ■ 1 Main Block of 32 KByte ■ 3 Main Blocks of 64 KByte each Two different bus interfaces are supported by the memory. The primary interface, the Firmware Hub (or FWH) Interface, uses Intel’s proprietary FWH protocol. This has been designed to remove the need for the ISA bus in current PC Chipsets; the M50FW002 acts as the PC BIOS on the Low Pin Count bus for these PC Chipsets. The secondary interface, the Address/Address Multiplexed (or A/A Mux) Interface, is designed to be compatible with current Flash Programmers for production line programming prior to fitting to a PC Motherboard. The memory is delivered with all the bits erased (set to 1). A8 A9 RP VPP VCC RC A10 Figure 2. PLCC Connections A/A Mux FGPI2 FGPI3 RP VPP VCC CLK FGPI4 A/A Mux 1 32 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 FGPI1 FGPI0 WP TBL ID3 ID2 ID1 ID0 FWH0 9 M50FW002 25 IC (VIL) NC NC VSS VCC INIT FWH4 RFU RFU IC (VIH) NC NC VSS VCC G W RB DQ7 A/A Mux DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6 FWH1 FWH2 VSS FWH3 RFU RFU RFU 17 A/A Mux AI05749 Note: Pins 27 and 28 are not internally connected. 4/39 M50FW002 Figure 3. Logic Diagram (FWH Interface) Figure 4. Logic Diagram (A/A Mux Interface) VCC VPP VCC VPP 4 4 FWH0FWH3 ID0-ID3 11 5 DQ0-DQ7 A0-A10 FGPI0FGPI4 FWH4 8 WP M50FW002 RC TBL IC CLK M50FW002 RB G IC W RP RP INIT VSS VSS AI05748 AI05747 Table 1. Signal Names (FWH Interface) Table 2. Signal Names (A/A Mux Interface) FWH0-FWH3 Input/Output Communications IC Interface Configuration FWH4 Input Communication Frame A0-A10 Address Inputs ID0-ID3 Identification Inputs DQ0-DQ7 Data Inputs/Outputs FGPI0-FGPI4 General Purpose Inputs G Output Enable IC Interface Configuration W Write Enable RP Interface Reset RC Row/Column Address Select INIT CPU Reset RB Ready/Busy Output CLK Clock RP Interface Reset TBL Top Block Lock VCC Supply Voltage WP Write Protect VPP Optional Supply Voltage for Fast Program and Fast Erase Operations RFU Reserved for Future Use. Leave disconnected VSS Ground VCC Supply Voltage NC Not Connected Internally VPP Optional Supply Voltage for Fast Erase Operations VSS Ground NC Not Connected Internally 5/39 M50FW002 SIGNAL DESCRIPTIONS There are two different bus interfaces available on this part. The active interface is selected before power-up or during Reset using the Interface Configuration Pin, IC. The signals for each interface are discussed in the Firmware Hub (FWH) Signal Descriptions section and the Address/Address Multiplexed (A/A Mux) Signal Descriptions section below. The supply signals are discussed in the Supply Signal Descriptions section below. Firmware Hub (FWH) Signal Descriptions For the Firmware Hub (FWH) Interface see Figure 4, Logic Diagram, and Table 1, Signal Names. Input/Output Communications (FWH0-FWH3). All Input and Output Communication with the memory take place on these pins. Addresses and Data for Bus Read and Bus Write operations are encoded on these pins. Input Communication Frame (FWH4). The Input Communication Frame (FWH4) signals the start of a bus operation. When Input Communication Frame is Low, VIL, on the rising edge of the Clock a new bus operation is initiated. If Input Communication Frame is Low, VIL, during a bus operation then the operation is aborted. When Input Communication Frame is High, VIH, the current bus operation is proceeding or the bus is idle. Identification Inputs (ID0-ID3). The Identification Inputs select the address that the memory responds to. Up to 16 memories can be addressed on a bus. For an address bit to be ‘0’ the pin can be left floating or driven Low, VIL; an internal pull-down resistor is included with a value of R IL. For an address bit to be ‘1’ the pin must be driven High, V IH; there will be a leakage current of ILI2 through each pin when pulled to V IH; see Table 19. By convention the boot memory must have address ‘0000’ and all additional memories take sequential addresses starting from ‘0001’. General Purpose Inputs (FGPI0-FGPI4). The General Purpose Inputs can be used as digital inputs for the CPU to read. The General Purpose Input Register holds the values on these pins. The pins must have stable data from before the start of the cycle that reads the General Purpose Input Register until after the cycle is complete. These pins must not be left to float, they should be driven Low, VIL, or High, VIH. Interface Configuration (IC). The Interface Configuration input selects whether the Firmware Hub (FWH) or the Address/Address Multiplexed (A/A Mux) Interface is used. The chosen interface must be selected before power-up or during a Reset and, thereafter, cannot be changed. The state of 6/39 the Interface Configuration, IC, should not be changed during operation. To select the Firmware Hub (FWH) Interface the Interface Configuration pin should be left to float or driven Low, VIL; to select the Address/Address Multiplexed (A/A Mux) Interface the pin should be driven High, VIH. An internal pull-down resistor is included with a value of RIL; there will be a leakage current of ILI2 through each pin when pulled to VIH; see Table 19. Interface Reset (RP). The Interface Reset (RP) input is used to reset the memory. When Interface Reset (RP) is set Low, VIL, the memory is in Reset mode: the outputs are put to high impedance and the current consumption is minimized. When RP is set High, V IH, the memory is in normal operation. After exiting Reset mode, the memory enters Read mode. CPU Reset (INIT). The CPU Reset, INIT, pin is used to Reset the memory when the CPU is reset. It behaves identically to Interface Reset, RP, and the internal Reset line is the logical OR (electrical AND) of RP and INIT. Clock (CLK). The Clock, CLK, input is used to clock the signals in and out of the Input/Output Communication Pins, FWH0-FWH3. The Clock conforms to the PCI specification. Top Block Lock (TBL). The Top Block Lock input is used to prevent the Top Block (Block 6) from being changed. When Top Block Lock, TBL, is set Low, V IL, Program and Erase operations in the Top Block have no effect, regardless of the state of the Lock Register. When Top Block Lock, TBL, is set High, VIH, the protection of the Block is determined by the Lock Register. The state of Top Block Lock, TBL, does not affect the protection of the other blocks (Blocks 0 to 5). Top Block Lock, TBL, must be set prior to a Program or Erase operation is initiated and must not be changed until the operation completes or unpredictable results may occur. Care should be taken to avoid unpredictable behavior by changing TBL during Program or Erase Suspend. Write Protect (WP). The Write Protect input is used to prevent the blocks 0 to 5 from being changed. When Write Protect, WP, is set Low, VIL, Program and Erase operations in these blocks have no effect, regardless of the state of the Lock Register. When Write Protect, WP, is set High, VIH, the protection of the Block is determined by the Lock Register. The state of Write Protect, WP, does not affect the protection of the Top Block (Block 6). Write Protect, WP, must be set prior to a Program or Erase operation is initiated and must not be changed until the operation completes or unpre- M50FW002 dictable results may occur. Care should be taken to avoid unpredictable behavior by changing WP during Program or Erase Suspend. Reserved for Future Use (RFU). These pins do not have assigned functions in this revision of the part. They must be left disconnected. Address/Address Multiplexed (A/A Mux) Signal Descriptions For the Address/Address Multiplexed (A/A Mux) Interface see Figure 4, and Table 2. Address Inputs (A0-A10). The Address Inputs are used to set the Row Address bits (A0-A10) and the Column Address bits (A11-A17). They are latched during any bus operation by the Row/Column Address Select input, RC. Data Inputs/Outputs (DQ0-DQ7). The Data Inputs/Outputs hold the data that is written to or read from the memory. They output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. The Data Inputs/Outputs, DQ0-DQ7, are latched during a Bus Write operation. Output Enable (G). The Output Enable, G, controls the Bus Read operation of the memory. Write Enable (W). The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface. Row/Column Address Select (RC). The Row/ Column Address Select input selects whether the Address Inputs should be latched into the Row Address bits (A0-A10) or the Column Address bits (A11-A17). The Row Address bits are latched on the falling edge of RC whereas the Column Address bits are latched on the rising edge. Ready/Busy Output (RB). The Ready/Busy pin gives the status of the memory’s Program/Erase Controller. When Ready/Busy is Low, VOL, the memory is busy with a Program or Erase operation and it will not accept any additional Program or Erase command except the Program/Erase Suspend command. When Ready/Busy is High, VOH, the memory is ready for any Read, Program or Erase operation. Supply Signal Descriptions The Supply Signals are the same for both interfaces. VCC Supply Voltage. The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.). The Command Interface is disabled when the V CC Supply Voltage is less than the Lockout Voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/ Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. After VCC becomes valid the Command Interface is reset to Read mode. A 0.1µF capacitor should be connected between the VCC Supply Voltage pins and the VSS Ground pin to decouple the current surges from the power supply. Both V CC Supply Voltage pins must be connected to the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations. VPP Optional Supply Voltage. The VPP Optional Supply Voltage pin is used to select the Fast Program (see the Quadruple Byte Program Command description) and Fast Erase options of the memory and to protect the memory. When VPP < VPPLK Program and Erase operations cannot be performed and an error is reported in the Status Register if an attempt to change the memory contents is made. When VPP = VCC Program and Erase operations take place as normal. When VPP = VPPH Fast Program (if A/A Mux interface is selected) and Fast Erase operations are used. Any other voltage input to V PP will result in undefined behavior and should not be used. VPP should not be set to V PPH for more than 80 hours during the life of the memory. VSS Ground. VSS is the reference for all the voltage measurements. Table 3. Block Addresses Size (Kbytes) Address Range Block Number Block Type 16 3C000h-3FFFFh 6 Boot Block (Top) 8 3A000h-3BFFFh 5 Parameter Block 8 38000h-39FFFh 4 Parameter Block 32 30000h-37FFFh 3 Main Block 64 20000h-2FFFFh 2 Main Block 64 10000h-1FFFFh 1 Main Block 64 00000h-0FFFFh 0 Main Block 7/39 M50FW002 BUS OPERATIONS The two interfaces have similar bus operations but the signals and timings are completely different. The Firmware Hub (FWH) Interface is the usual interface and all of the functionality of the part is available through this interface. Only a subset of functions are available through the Address/ Address Multiplexed (A/A Mux) Interface. Follow the section Firmware Hub (FWH) Bus Operations below and the section Address/ Address Multiplexed (A/A Mux) Interface Bus Operations below for a description of the bus operations on each interface. Firmware Hub (FWH) Bus Operations The Firmware Hub (FWH) Interface consists of four data signals (FWH0-FWH3), one control line (FWH4) and a clock (CLK). In addition protection against accidental or malicious data corruption can be achieved using two further signals (TBL and WP). Finally two reset signals (RP and INIT) are available to put the memory into a known state. The data signals, control signal and clock are designed to be compatible with PCI electrical specifications. The interface operates with clock speeds up to 33MHz. The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Standby, Reset and Block Protection. Bus Read. Bus Read operations read from the memory cells, specific registers in the Command Interface or Firmware Hub Registers. A valid Bus Read operation starts when Input Communication Frame, FWH4, is Low, VIL, as Clock rises and the correct Start cycle is on FWH0-FWH3. On the following clock cycles the Host will send the Memory ID Select, Address and other control bits on FWH0-FWH3. The memory responds by outputting Sync data until the wait-states have elapsed followed by Data0-Data3 and Data4Data7. Refer to Table 4, FWH Bus Read Field Definitions, and Figure 5, FWH Bus Read Waveforms (1-byte), for a description of the Field definitions for each clock cycle of the transfer. See Table 16, AC Measurement Conditions (FWH Interface), and Figure 10, AC Signal Timing Waveforms (FWH Interface), for details on the timings of the signals. Bus Write. Bus Write operations write to the Command Interface or Firmware Hub Registers. A 8/39 valid Bus Write operation starts when Input Communication Frame, FWH4, is Low, V IL, as Clock rises and the correct Start cycle is on FWH0-FWH3. On the following Clock cycles the Host will send the Memory ID Select, Address, other control bits, Data0-Data3 and Data4-Data7 on FWH0-FWH3. The memory outputs Sync data until the wait-states have elapsed. Refer to Table 5, FWH Bus Write Field Definitions, and Figure 6, FWH Bus Write Waveforms, for a description of the Field definitions for each clock cycle of the transfer. See Table 16, AC Measurement Conditions (FWH Interface), and Figure 10, AC Signal Timing Waveforms (FWH Interface), for details on the timings of the signals. Bus Abort. The Bus Abort operation can be used to immediately abort the current bus operation. A Bus Abort occurs when FWH4 is driven Low, VIL, during the bus operation; the memory will tri-state the Input/Output Communication pins, FWH0FWH3. Note that, during a Bus Write operation, the Command Interface starts executing the command as soon as the data is fully received; a Bus Abort during the final TAR cycles is not guaranteed to abort the command; the bus, however, will be released immediately. Standby. When FWH4 is High, VIH, the memory is put into Standby mode where FWH0-FWH3 are put into a high-impedance state and the Supply Current is reduced to the Standby level, ICC1. Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when Interface Reset, RP, or CPU Reset, INIT, is Low, VIL. RP or INIT must be held Low, VIL, for tPLPH. The memory resets to Read mode upon return from Reset mode and the Lock Registers return to their default states regardless of their state before Reset, see Table 12. If RP or INIT goes Low, VIL, during a Program or Erase operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to tPLRH to abort a Program or Erase operation. Block Protection. Block Protection can be forced using the signals Top Block Lock, TBL, and Write Protect, WP, regardless of the state of the Lock Registers. M50FW002 Table 4. FWH Bus Read Field Definitions Clock Cycle Number Clock Cycle Count Field FWH0FWH3 Memory I/O Description 1 1 START 1101b I On the rising edge of CLK with FWH4 Low, the contents of FWH0-FWH3 indicate the start of a FWH Read cycle. 2 1 IDSEL XXXX I Indicates which FWH Flash Memory is selected. The value on FWH0-FWH3 is compared to the IDSEL strapping on the FWH Flash Memory pins to select which FWH Flash Memory is being addressed. 3-9 7 ADDR XXXX I A 28-bit address phase is transferred starting with the most significant nibble first. 10 1 MSIZE 0X0Xb I Indicates how many bytes will be transferred during multi-byte read operations. The FWH Flash Memory supports 1-byte (0000b), 16-byte (0100b) and 32-byte (0101b) transfers. 11 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle. 12 1 TAR 1111b (float) O The FWH Flash Memory takes control of FWH0-FWH3 during this cycle. 13-14 2 WSYNC 0101b O The FWH Flash Memory drives FWH0-FWH3 to 0101b (short wait-sync) for two clock cycles, indicating that the data is not yet available. Two wait-states are always included. 15 1 RSYNC 0000b O The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating that data will be available during the next clock cycle. 16-17 2 DATA XXXX O Data transfer is two CLK cycles, starting with the least significant nibble. 17+ 5(2n-1) 0 (1-byte) 75 (16-byte) 155 (32-byte) MULTIBYTE 2 WSYNC + 1 RSYNC + 2 DATA O For each subsequent byte of data repeat cycles 13-17 (2WSYNC + 1RSYNC + 2DATA) 2n-1 times. The FWH Flash Memory supports n = 0000b (1-byte), n = 0100b (16-byte) and n = 0101b (32-byte) reads. Previous +1 1 TAR 1111b O The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate a turnaround cycle. Previous +1 1 TAR 1111b (float) N/A The FWH Flash Memory floats its outputs, the host takes control of FWH0-FWH3. Figure 5. FWH Bus Read Waveforms (1-byte) CLK FWH4 FWH0-FWH3 Number of clock cycles START IDSEL ADDR MSIZE TAR SYNC DATA TAR 1 1 7 1 2 3 2 2 AI03437 9/39 M50FW002 Table 5. FWH Bus Write Field Definitions Clock Cycle Number Clock Cycle Count Field FWH0FWH3 Memory I/O 1 1 START 1110b I On the rising edge of CLK with FWH4 Low, the contents of FWH0-FWH3 indicate the start of a FWH Write Cycle. 2 1 IDSEL XXXX I Indicates which FWH Flash Memory is selected. The value on FWH0-FWH3 is compared to the IDSEL strapping on the FWH Flash Memory pins to select which FWH Flash Memory is being addressed. 3-9 7 ADDR XXXX I A 28-bit address phase is transferred starting with the most significant nibble first. 10 1 MSIZE 0000b I Always 0000b (single byte transfer). 11-12 2 DATA XXXX I Data transfer is two cycles, starting with the least significant nibble. 13 1 TAR 1111b I The host drives FWH0-FWH3 to 1111b to indicate a turnaround cycle. 14 1 TAR 1111b (float) O The FWH Flash Memory takes control of FWH0-FWH3 during this cycle. 15 1 SYNC 0000b O The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating it has received data or a command. 16 1 TAR 1111b O The FWH Flash Memory drives FWH0-FWH3 to 1111b, indicating a turnaround cycle. 17 1 TAR 1111b (float) N/A Description The FWH Flash Memory floats its outputs and the host takes control of FWH0-FWH3. Figure 6. FWH Bus Write Waveforms CLK FWH4 FWH0-FWH3 Number of clock cycles START IDSEL ADDR MSIZE DATA TAR SYNC TAR 1 1 7 1 2 2 1 2 AI03441 10/39 M50FW002 Address/Address Multiplexed (A/A Mux) Bus Operations The Address/Address Multiplexed (A/A Mux) Interface has a more traditional style interface. The signals consist of a multiplexed address signals (A0-A10), data signals, (DQ0-DQ7) and three control signals (RC, G, W). An additional signal, RP, can be used to reset the memory. The Address/Address Multiplexed (A/A Mux) Interface is included for use by Flash Programming equipment for faster factory programming. Only a subset of the features available to the Firmware Hub (FWH) Interface are available; these include all the Commands but exclude the Security features and other registers. The following operations can be performed using the appropriate bus cycles: Bus Read, Bus Write, Output Disable and Reset. When the Address/Address Multiplexed (A/A Mux) Interface is selected all the blocks are unprotected. It is not possible to protect any blocks through this interface. Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature and the Status Register. A valid Bus Read operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC. Then Write Enable (W) and Interface Reset (RP) must be High, V IH, and Output Enable, G, Low, VIL, in order to perform a Bus Read operation. The Data Inputs/Outputs will output the value, see Figure 12, Read AC Waveforms (A/A Mux Interface), and Table 24, A/A Mux Interface Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write to the Command Interface. A valid Bus Write operation begins by latching the Row Address and Column Address signals into the memory using the Address Inputs, A0-A10, and the Row/Column Address Select RC. The data should be set up on the Data Inputs/Outputs; Output Enable, G, and Interface Reset, RP, must be High, VIH and Write Enable, W, must be Low, V IL. The Data Inputs/ Outputs are latched on the rising edge of Write Enable, W. See Figure 13, and Table 25, A/A Mux Interface Write AC Characteristics, for details of the timing requirements. Output Disable. The data outputs are high-impedance when the Output Enable, G, is at VIH. Reset. During Reset mode all internal circuits are switched off, the memory is deselected and the outputs are put in high-impedance. The memory is in Reset mode when RP is Low, VIL. RP must be held Low, VIL for tPLPH. If RP is goes Low, VIL, during a Program or Erase operation, the operation is aborted and the memory cells affected no longer contain valid data; the memory can take up to tPLRH to abort a Program or Erase operation. Table 6. A/A Mux Bus Operations G W RP VPP DQ7-DQ0 Bus Read VIL VIH VIH Don’t Care Data Output Bus Write VIH VIL VIH VCC or VPPH Data Input Output Disable VIH VIH VIH Don’t Care Hi-Z VIL or VIH VIL or VIH VIL Don’t Care Hi-Z Operation Reset Table 7. Manufacturer and Device Codes G W RP A17-A1 A0 DQ7-DQ0 Manufacturer Code VIL VIH VIH VIL VIL 20h Device Code VIL VIH VIH VIL VIH 29h Operation 11/39 M50FW002 Command Cycles Table 8. Commands Bus Write Operations 1st 2nd Addr Data 3rd Addr Data Read Memory Array 1 X FFh Read Status Register 1 X 70h 1 X 90h 1 X 98h 2 X 40h PA PD 2 X 10h PA PD Quadruple Byte Program 5 X 30h A1 PD Chip Erase 2 X 80h X 10h Block Erase 2 X 20h BA D0h Clear Status Register 1 X 50h Program/Erase Suspend 1 X B0h Program/Erase Resume 1 X D0h 1 X 00h 1 X 01h 1 X 60h 1 X 2Fh 1 X C0h 4th 5th Addr Data Addr Data Addr Data A2 PD A3 PD A4 PD Read Electronic Signature Program Invalid/Reserved Note: X Don’t Care, PA Program Address, PD Program Data, A1,2,3,4 Consecutive Addresses, BA Any address in the Block. Read Memory Array: After a Read Memory Array command, read the memory as normal until another command is issued. Read Status Register: After a Read Status Register command, read the Status Register as normal until another command is issued. Read Electronic Signature: After a Read Electronic Signature command, read Manufacturer Code, Device Code until another command is issued. Block Erase, Byte Program: After these commands, read the Status Register until the command completes and another command is issued. Quadruple Byte Program: This command is only valid in A/A Mux mode. Addresses A1, A2, A3 and A4 must be consecutive addresses differing only for address bit A0 and A1. After this command read the Status Register until the command completes and another command is issued. Chip Erase: This command is only valid in A/A Mux mode. After this command, read the Status Register until the command completes and another command is issued. Clear Status Register: After the Clear Status Register command bits 1, 3, 4 and 5 in the Status Register are reset to ‘0’. Program/Erase Suspend: After the Program/Erase Suspend command has been accepted, issue Read Memory Array, Read Status Register, Program (during Erase suspend) and Program/Erase resume commands. Program/Erase Resume: After the Program/Erase Resume command the suspended Program/Erase operation resumes, read the Status Register until the Program/Erase Controller completes and the memory returns to Read Mode. Invalid/Reserved: Do not use Invalid or Reserved commands. 12/39 M50FW002 COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. After power-up or a Reset operation the memory enters Read mode. The commands are summarized in Table 8, Commands. Refer to Table 8 in conjunction with the text descriptions below. Read Memory Array Command. The Read Memory Array command returns the memory to its Read mode where it behaves like a ROM or EPROM. One Bus Write cycle is required to issue the Read Memory Array command and return the memory to Read mode. Once the command is issued the memory remains in Read mode until another command is issued. From Read mode Bus Read operations will access the memory array. While the Program/Erase Controller is executing a Program or Erase operation the memory will not accept the Read Memory Array command until the operation completes. Read Status Register Command. The Read Status Register command is used to read the Status Register. One Bus Write cycle is required to issue the Read Status Register command. Once the command is issued subsequent Bus Read operations read the Status Register until another command is issued. See the section on the Status Register for details on the definitions of the Status Register bits. Read Electronic Signature Command. The Read Electronic Signature command is used to read the Manufacturer Code and the Device Code. One Bus Write cycle is required to issue the Read Electronic Signature command. Once the command is issued subsequent Bus Read operations read the Manufacturer Code or the Device Code until another command is issued. After the Read Electronic Signature Command is issued the Manufacturer Code and Device Code can be read using Bus Read operations using the addresses in Table 9. Table 9. Read Electronic Signature Code Address Data Manufacturer Code 00000h 20h Device Code 00001h 29h Program Command. The Program command can be used to program a value to one address in the memory array at a time. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the address and data in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. If the address falls in a protected block then the Program operation will abort, the data in the memory array will not be changed and the Status Register will output the error. During the Program operation the memory will only accept the Read Status Register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Program times are given in Table 22. Note that the Program command cannot change a bit set at ‘0’ back to ‘1’ and attempting to do so will not cause any modification on its value. One of the Erase commands must be used to set all of the bits in the block to ‘1’. See Figure 14, Program Flowchart and Pseudo Code, for a suggested flowchart on using the Program command. Quadruple Byte Program Command. The Quadruple Byte Program Command can be only used in A/A Mux mode to program four adjacent bytes in the memory array at a time. The four bytes must differ only for the addresses A0 and A1. Programming should not be attempted when VPP is not at V PPH. The operation can also be executed if V PP is below VPPH, but result could be uncertain. Five Bus Write operations are required to issue the command. The second, the third and the fourth Bus Write cycle latches respectively the address and data of the first, the second and the third byte in the internal state machine. The fifth Bus Write cycle latches the address and data of the fourth byte in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. During the Quadruple Byte Program operation the memory will only accept the Read Status register command and the Program/Erase Suspend command. All other commands will be ignored. Typical Quadruple Byte Program times are given in Table 22. Note that the Quadruple Byte Program command cannot change a bit set to ‘0’ back to ‘1’ and attempting to do so will not cause any modification on its value. An Erase command must be used to set all of the bits in the block to ‘1’. See Figure 15, Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only), 13/39 M50FW002 for a suggested flowchart on using the Quadruple Byte Program command. Chip Erase Command. The Chip Erase command can be used in A/A Mux mode to erase the entire chip at a time. Erasing should not be attempted when VPP is not at VPPH. The operation can also be executed if V PP is below VPPH, but result could be uncertain. Two Bus Write operations are required to issue the command and start the Program/Erase Controller. Once the command is issued, subsequent Bus Read operations read the Status Register. (See the section on the Status Register for details of the definitions of the Status Register bits.) During the Chip Erase operation, the memory only accepts the Read Status Register command. All other commands are ignored. Typical Chip Erase times are given in Table 22. The Chip Erase command sets all of the bits in the memory to ‘1’. See Figure 17, Chip Erase Flowchart and Pseudo Code, for a suggested flowchart when using the Chip Erase command. Block Erase Command. The Block Erase command can be used to erase a block. Two Bus Write operations are required to issue the command; the second Bus Write cycle latches the block address in the internal state machine and starts the Program/Erase Controller. Once the command is issued subsequent Bus Read operations read the Status Register. See the section on the Status Register for details on the definitions of the Status Register bits. If the block is protected then the Erase operation will abort, the data in the block will not be changed and the Status Register will output the error. During the Erase operation the memory only accepts the Read Status Register command and the Program/Erase Suspend command. All other commands are ignored. Typical Erase times are given in Table 22. The Erase command sets all of the bits in the block to ‘1’. All previous data in the block is lost. See Figure 18, for a suggested flowchart on using the Erase command. Clear Status Register Command. The Clear Status Register command can be used to reset bits 1, 3, 4 and 5 in the Status Register to ‘0’. One Bus Write is required to issue the Clear Status Register command. Once the command is issued the memory returns to its previous mode, subsequent Bus Read operations continue to output the same data. 14/39 The bits in the Status Register are sticky and do not automatically return to ‘0’ when a new Program or Erase command is issued. If an error occurs then it is essential to clear any error bits in the Status Register by issuing the Clear Status Register command before attempting a new Program or Erase command. Program/Erase Suspend Command. The Program/Erase Suspend command can be used to pause a Program or Erase operation. One Bus Write cycle is required to issue the Program/Erase Suspend command and pause the Program/Erase Controller. Once the command is issued it is necessary to poll the Program/Erase Controller Status bit to find out when the Program/Erase Controller has paused; no other commands will be accepted until the Program/Erase Controller has paused. After the Program/Erase Controller has paused, the memory will continue to output the Status Register until another command is issued. During the polling period between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing it is possible for the operation to complete. Once Program/Erase Controller Status bit indicates that the Program/ Erase Controller is no longer active, the Program Suspend Status bit or the Erase Suspend Status bit can be used to determine if the operation has completed or is suspended. For timing on the delay between issuing the Program/Erase Suspend command and the Program/Erase Controller pausing see Table 22. During Program/Erase Suspend the Read Memory Array, Read Status Register, Read Electronic Signature and Program/Erase Resume commands will be accepted by the Command Interface. Additionally, if the suspended operation was Erase then the Program command will also be accepted; only the blocks not being erased may be read or programmed correctly. See Figures 16, Program Suspend and Resume Flowchart, and Pseudo Code, and 19, Erase Suspend and Resume Flowchart, and Pseudo Code, for suggested flowcharts on using the Program/Erase Suspend command. Program/Erase Resume Command. The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend has paused it. One Bus Write cycle is required to issue the Program/Erase Resume command. Once the command is issued subsequent Bus Read operations read the Status Register. M50FW002 STATUS REGISTER The Status Register provides information on the current or previous Program or Erase operation. Different bits in the Status Register convey different information and errors on the operation. To read the Status Register the Read Status Register command can be issued. The Status Register is automatically read after Program, Erase and Program/Erase Resume commands are issued. The Status Register can be read from any address. The Status Register bits are summarized in Table 10, Status Register Bits. Refer to Table 10 in conjunction with the text descriptions below. Program/Erase Controller Status (Bit 7). The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive. When the Program/Erase Controller Status bit is ‘0’, the Program/Erase Controller is active; when the bit is ‘1’, the Program/Erase Controller is inactive. The Program/Erase Controller Status is ‘0’ immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is ‘1’. During Program and Erase operation the Program/Erase Controller Status bit can be polled to find the end of the operation. The other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is ‘1’. After the Program/Erase Controller completes its operation the Erase Status, Program Status, VPP Status and Block Protection Status bits should be tested for errors. Erase Suspend Status (Bit 6). The Erase Suspend Status bit indicates that an Erase operation has been suspended and is waiting to be resumed. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Erase Suspend Status bit is ‘0’ the Program/Erase Controller is active or has completed its operation; when the bit is ‘1’ a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns to ‘0’. Erase Status (Bit 5). The Erase Status bit can be used to identify if the memory has applied the maximum number of erase pulses to the block and still failed to verify that the block has erased correctly. The Erase Status bit should be read once the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive). When the Erase Status bit is ‘0’ the memory has successfully verified that the block has erased correctly; when the Erase Status bit is ‘1’ the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that the block has erased correctly. Once the Erase Status bit is set to ‘1’ it can only be reset to ‘0’ by a Clear Status Register command or a hardware reset. If it is set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status (Bit 4). The Program Status bit can be used to identify if the memory has applied the maximum number of program pulses to the byte and still failed to verify that the byte has programmed correctly. The Program Status bit should be read once the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive). When the Program Status bit is ‘0’ the memory has successfully verified that the byte has programmed correctly; when the Program Status bit is ‘1’ the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that the byte has programmed correctly. Once the Program Status bit is set to ‘1’ it can only be reset to ‘0’ by a Clear Status Register command or a hardware reset. If it is set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. VPP Status (Bit 3). The VPP Status bit can be used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program or Erase operation. Indeterminate results can occur if VPP becomes invalid during a Program or Erase operation. When the VPP Status bit is ‘0’ the voltage on the VPP pin was sampled at a valid voltage; when the VPP Status bit is ‘1’ the V PP pin has a voltage that is below the V PP Lockout Voltage, VPPLK, the memory is protected; Program and Erase operation cannot be performed. Once the VPP Status bit set to ‘1’ it can only be reset to ‘0’ by a Clear Status Register command or a hardware reset. If it is set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. 15/39 M50FW002 Program Suspend Status (Bit 2). The Program Suspend Status bit indicates that a Program operation has been suspended and is waiting to be resumed. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is ‘1’ (Program/Erase Controller inactive); after a Program/Erase Suspend command is issued the memory may still complete the operation rather than entering the Suspend mode. When the Program Suspend Status bit is ‘0’ the Program/Erase Controller is active or has completed its operation; when the bit is ‘1’ a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. When a Program/Erase Resume command is issued the Program Suspend Status bit returns to ‘0’. Block Protection Status (Bit 1). The Block Protection Status bit can be used to identify if the Pro- gram or Erase operation has tried to modify the contents of a protected block. When the Block Protection Status bit is to ‘0’ no Program or Erase operations have been attempted to protected blocks since the last Clear Status Register command or hardware reset; when the Block Protection Status bit is ‘1’ a Program or Erase operation has been attempted on a protected block. Once it is set to ‘1’ the Block Protection Status bit can only be reset to ‘0’ by a Clear Status Register command or a hardware reset. If it is set to ‘1’ it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Using the A/A Mux Interface the Block Protection Status bit is always ‘0’. Reserved (Bit 0). Bit 0 of the Status Register is reserved. Its value should be masked. Table 10. Status Register Bits Operation Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Program active ‘0’ X1 ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Program suspended ‘1 X1 ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ Program completed successfully ‘1’ X1 ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Program failure due to VPP Error ‘1’ X1 ‘0’ ‘0’ ‘1’ ‘0’ ‘0’ Program failure due to Block Protection (FWH Interface only) ‘1’ X1 ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ Program failure due to cell failure ‘1’ X1 ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ Erase active ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Block Erase suspended ‘1’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Erase completed successfully ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ Erase failure due to VPP Error ‘1’ ‘0’ ‘0’ ‘0’ ‘1’ ‘0’ ‘0’ Block Erase failure due to Block Protection (FWH Interface only) ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ ‘0’ ‘1’ Erase failure due to failed cell(s) ‘1’ ‘0’ ‘1’ ‘0’ ‘0’ ‘0’ ‘0’ Note: 1. For Program operations during Erase Suspend Bit 6 is ‘1’, otherwise Bit 6 is ‘0’. 16/39 M50FW002 FIRMWARE HUB (FWH) INTERFACE CONFIGURATION REGISTERS Read Lock. The Read Lock bit determines When the Firmware Hub Interface is selected sevwhether the contents of the Block can be read eral additional registers can be accessed. These (from Read mode). When the Read Lock Bit is set, registers control the protection status of the ‘1’, the block is read protected; any operation that Blocks, read the General Purpose Input pins and attempts to read the contents of the block will read identify the memory using the Electronic Signature 00h instead. When the Read Lock Bit is reset, ‘0’, codes. See Table 11 for the memory map of the read operations in the Block return the data proConfiguration Registers. grammed into the block as expected. Lock Registers After power-up or reset the Read Lock Bit is alThe Lock Registers control the protection status of ways reset to ‘0’ (not read protected). the Blocks. Each Block has its own Lock Register. Three bits within each Lock Register control the Lock Down. The Lock Down Bit provides a protection of each block, the Write Lock Bit, the mechanism for protecting software data from simRead Lock Bit and the Lock Down Bit. ple hacking and malicious attack. When the Lock Down Bit is set, ‘1’, further modification to the The Lock Registers can be read and written, Write Lock, Read Lock and Lock Down Bits cannot though care should be taken when writing as, once be performed. A reset or power-up is required bethe Lock Down Bit is set, ‘1’, further modifications fore changes to these bits can be made. When the to the Lock Register cannot be made until cleared, Lock Down Bit is reset, ‘0’, the Write Lock, Read to ‘0’, by a reset or power-up. Lock and Lock Down Bits can be changed. See Table 12 for details on the bit definitions of the Firmware Hub (FWH) General Purpose Input Lock Registers. Register Write Lock. The Write Lock Bit determines The Firmware Hub (FWH) General Purpose Input whether the contents of the Block can be modified Register holds the state of the Firmware Hub Inter(using the Program or Erase Command). When face General Purpose Input pins, FGPI0-FGPI4. the Write Lock Bit is set, ‘1’, the block is write proWhen this register is read, the state of these pins tected; any operations that attempt to change the is returned. This register is read-only and writing to data in the block will fail and the Status Register it has no effect. will report the error. When the Write Lock Bit is reset, ‘0’, the block is not write protected through the The signals on the Firmware Hub Interface GenerLock Register and may be modified unless write al Purpose Input pins should remain constant protected through some other means. throughout the whole Bus Read cycle in order to guarantee that the correct data is read. When V PP is less than VPPLK all blocks are protected and cannot be modified, regardless of the Manufacturer Code Register state of the Write Lock Bit. If Top Block Lock, TBL, Reading the Manufacturer Code Register returns is Low, V IL, then the Top Block (Block 6) is write the manufacturer code for the memory. The manprotected and cannot be modified. Similarly, if ufacturer code for STMicroelectronics is 20h. This Write Protect, WP, is Low, VIL, then the blocks 0 to register is read-only and writing to it has no effect. 5 are write protected and cannot be modified. Device Code Register After power-up or reset the Write Lock Bit is alReading the Device Code Register returns the deways set to ‘1’ (write protected). vice code for the memory (29h). This register is read-only and writing to it has no effect. 17/39 M50FW002 Table 11. Firmware Hub Register Configuration Map (1) Memory Address Default Value Access Top Block Lock Register (Block 6) FBFC002h 01h R/W T_MINUS01_LK Top Block [-1] Lock Register (Block 5) FBFA002h 01h R/W T_MINUS02_LK Top Block [-2] Lock Register (Block 4) FBF8002h 01h R/W T_MINUS03_LK Top Block [-3] Lock Register (Block 3) FBF0002h 01h R/W T_MINUS04_LK Top Block [-4] Lock Register (Block 2) FBE0002h 01h R/W T_MINUS05_LK Top Block [-5] Lock Register (Block 1) FBD0002h 01h R/W T_MINUS06_LK Top Block [-6] Lock Register (Block 0) FBC0002h 01h R/W Firmware Hub (FWH) General Purpose Input Register FBC0100h N/A R Manufacturer Code Register FBC0000h 20h R Device Code Register FBC0001h 29h R Mnemonic T_BLOCK_LK FGPI_REG MANUF_REG DEV_REG 18/39 Register Name M50FW002 Table 12. Lock Register Bit Definitions(1) Bit Bit Name Value 7-3 2 1 0 Function Reserved ‘1’ Bus Read operations in this Block always return 00h. ‘0’ Bus read operations in this Block return the Memory Array contents. (Default value). ‘1’ Changes to the Read-Lock bit and the Write-Lock bit cannot be performed. Once a ‘1’ is written to the Lock-Down bit it cannot be cleared to ‘0’; the bit is always reset to ‘0’ following a Reset (using RP or INIT) or after power-up. ‘0’ Read-Lock and Write-Lock can be changed by writing new values to them. (Default value). ‘1’ Program and Erase operations in this Block will set an error in the Status Register. The memory contents will not be changed. (Default value). ‘0’ Program and Erase operations in this Block are executed and will modify the Block contents. Read-Lock Lock-Down Write-Lock Note: 1. Applies to Top Block Lock Register (T_BLOCK_LK) and Top Block [-1] Lock Register (T_MINUS01_LK) to Top Block [-6] Lock Register (T_MINUS06_LK). Table 13. General Purpose Input Register Definition(1) Bit Bit Name Value 7-5 4 3 2 1 0 Function Reserved ‘1’ Input Pin FGPI4 is at VIH ‘0’ Input Pin FGPI4 is at VIL ‘1’ Input Pin FGPI3 is at VIH ‘0’ Input Pin FGPI3 is at VIL ‘1’ Input Pin FGPI2 is at VIH ‘0’ Input Pin FGPI2 is at VIL ‘1’ Input Pin FGPI1 is at VIH ‘0’ Input Pin FGPI1 is at VIL ‘1’ Input Pin FGPI0 is at VIH ‘0’ Input Pin FGPI0 is at VIL FGPI4 FGPI3 FGPI2 FGPI1 FGPI0 Note: 1. Applies to the General Purpose Input Register (FGPI_REG). 19/39 M50FW002 MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 14. Absolute Maximum Ratings Symbol Parameter Min Max Unit TBIAS Temperature Under Bias –50 125 °C TSTG Storage Temperature –65 150 °C VIO Input or Output Voltage (1,2) –0.6 VCC +0.6 V VCC Supply Voltage –0.6 4 V VPP Program Voltage –0.6 13 V Note: 1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions. 2. Maximum voltage may overshoot to V CC +2V during transition and for less than 20ns during transitions. 20/39 M50FW002 DC AND AC PARAMETERS This section summarizes the operating and measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC Characteristic tables that follow are derived from tests performed under the Measure- ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. Table 15. Operating Conditions Symbol VCC Parameter Min. Max. Unit 3.0 3.6 V Ambient Operating Temperature (range 1) 0 70 °C Ambient Operating Temperature (range 5) –20 85 °C Max. Unit Supply Voltage TA Figure 7. AC Measurement I/O Waveform (FWH Interface) 0.6 VCC 0.4 VCC 0.2 VCC Input and Output AC Testing Waveform IO < ILO IO > ILO IO < ILO Output AC Tri-state Testing Waveform AI03404 Table 16. AC Measurement Conditions (FWH Interface) Symbol CL Parameter Load Capacitance Min. 10 Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Reference Voltages pF 1.4 ns 0.2VCC to 0.6VCC V 0.4VCC V 21/39 M50FW002 Figure 8. AC Measurement I/O Waveform (A/A Mux Interface) 3V 1.5V 0V AI01417 Table 17. AC Measurement Conditions (A/A Mux Interface) Symbol CL Parameter Min. Load Capacitance Max. 30 Input Rise and Fall Times pF 10 Input Pulse Voltages Input and Output Timing Reference Voltages Unit ns 0 to 3 V 1.5 V Table 18. Device Impedance Symbol Parameter 1 CIN Input Capacitance 2 VIN = 0V CCLK Clock Capacitance 2 VIN = 0V LPIN Recommended Pin Inductance 3 Note: 1. TA=25°C, f=1 MHz 2. Sampled only, not 100% tested 3. See PCI Specification 22/39 Test Condition Min 3 Max Unit 13 pF 12 pF 20 nH M50FW002 Table 19. DC Characteristics Symbol VIH VIL Parameter Input High Voltage Input Low Voltage Interface Test Condition Min Max Unit FWH 0.5 VCC VCC + 0.5 V A/A Mux 0.7 VCC VCC + 0.3 V FWH –0.5 0.3 VCC V A/A Mux -0.5 0.8 V VIH(INIT) INIT Input High Voltage FWH 1.35 VCC + 0.5 V VIL(INIT) INIT Input Low Voltage FWH –0.5 0.2 VCC V ILI(2) Input Leakage Current 0V ≤ VIN ≤ VCC ±10 µA ILI2 IC, IDx Input Leakage Current IC, ID0, ID1, ID2, ID3 = VCC 200 µA RIL IC, IDx Input Pull Low Resistor 100 kΩ VOH Output High Voltage VOL ILO 20 FWH IOH = –500µA 0.9 VCC V A/A Mux IOH = –100µA VCC – 0.4 V FWH IOL = 1.5mA 0.1 VCC V A/A Mux IOL = 1.8mA 0.45 V 0V ≤ VOUT ≤ VCC ±10 µA 3 3.6 V 12.6 V Output Low Voltage Output Leakage Current VPP1 VPP Voltage VPPH VPP Voltage (Fast Program/Fast Erase) 11.4 VPPLK(1) VPP Lockout Voltage 1.5 VLKO(1) VCC Lockout Voltage 1.8 V 2.3 V ICC1 Supply Current (Standby) FWH FWH4 = 0.9 VCC, VPP = VCC All other inputs 0.9 VCC to 0.1 VCC VCC = 3.6V, f(CLK) = 33MHz 100 µA ICC2 Supply Current (Standby) FWH FWH4 = 0.1 VCC, VPP = VCC All other inputs 0.9 VCC to 0.1 VCC VCC = 3.6V, f(CLK) = 33MHz 10 mA ICC3 Supply Current (Any internal operation active) FWH VCC = VCC max, VPP = VCC f(CLK) = 33MHz IOUT = 0mA 60 mA ICC4 Supply Current (Read) A/A Mux G = VIH, f = 6MHz 20 mA Supply Current (Program/Erase) A/A Mux Program/Erase Controller Active 20 mA VPP Supply Current (Read/Standby) VPP > VCC 400 µA VPP Supply Current (Program/Erase active) VPP = VCC 40 mA VPP = 12V ± 5% 15 mA ICC5(1) IPP IPP1(1) Note: 1. Sampled only, not 100% tested. 2. Input leakage currents include High-Z output leakage for all bi-directional buffers with tri-state outputs. 23/39 M50FW002 Table 20. Clock Characteristics (FWH Interface) Symbol Parameter Test Condition Value Unit tCYC CLK Cycle Time(1) Min 30 ns tHIGH CLK High Time Min 11 ns tLOW CLK Low Time Min 11 ns Min 1 V/ns Max 4 V/ns CLK Slew Rate peak to peak Note: 1. Devices on the PCI Bus must work with any clock frequency between DC and 33MHz. Below 16MHz devices may be guaranteed by design rather than tested. Refer to PCI Specification. Figure 9. Clock Waveform (FWH Interface) tCYC tHIGH 0.6 VCC 0.5 VCC 0.4 VCC tLOW 0.4 VCC, p-to-p (minimum) 0.3 VCC 0.2 VCC AI03403 24/39 M50FW002 Table 21. AC Signal Timing Characteristics (FWH Interface) Symbol PCI Symbol tCHQV tval CLK to Data Out tCHQX(1) ton tCHQZ Parameter Test Condition Value Unit Min 2 ns Max 11 ns CLK to Active (Float to Active Delay) Min 2 ns toff CLK to Inactive (Active to Float Delay) Max 28 ns tAVCH tDVCH tsu Input Set-up Time(2) Min 7 ns tCHAX tCHDX th Input Hold Time(2) Min 0 ns Note: 1. The timing measurements for Active/Float transitions are defined when the current through the pin equals the leakage current specification. 2. Applies to all inputs except CLK. Figure 10. AC Signal Timing Waveforms (FWH Interface) CLK tCHQV tCHQZ tCHQX FWH0-FWH3 tDVCH tCHDX VALID VALID OUTPUT DATA FLOAT OUTPUT DATA VALID INPUT DATA AI03405 25/39 M50FW002 Table 22. Program and Erase Times Parameter Interface Test Condition Byte Program Min Typ (1) Max Unit 10 200 µs 200 µs Quadruple Byte Program A/A Mux VPP = 12V ± 5% 10 Chip Erase A/A Mux VPP = 12V ± 5% 3 A/A Mux VPP = 12V ± 5% 0.1 (2) 5 sec VPP = VCC 0.4 5 sec VPP = 12V ± 5% 0.75 8 sec VPP = VCC 1 10 sec Program/Erase Suspend to Program pause (3) 5 µs Program/Erase Suspend to Block Erase pause (3) 30 µs Block Program (64 KBytes) sec Block Erase (64 KBytes) Note: 1. TA = 25°C, VCC = 3.3V 2. This time is obtained executing the Quadruple Byte Program Command. 3. Sampled only, not 100% tested. Table 23. Reset AC Characteristics Symbol Parameter tPLPH RP or INIT Reset Pulse Width tPLRH RP or INIT Low to Reset RP or INIT Slew Rate(1) tPHFL RP or INIT High to FWH4 Low tPHWL tPHGL RP High to Write Enable or Output Enable Low Note: 1. See Chapter 4 of the PCI Specification. 26/39 Test Condition Value Unit Min 100 ns Program/Erase Inactive Max 100 ns Program/Erase Active Max 30 µs Rising edge only Min 50 mV/ns FWH Interface only Min 30 µs A/A Mux Interface only Min 50 µs M50FW002 Figure 11. Reset AC Waveforms RP, INIT tPLPH W, G, FWH4 tPHWL, tPHGL, tPHFL tPLRH RB AI03420 27/39 M50FW002 Table 24. Read AC Characteristics (A/A Mux Interface) Symbol Parameter Test Condition Value Unit tAVAV Read Cycle Time Min 250 ns tAVCL Row Address Valid to RC Low Min 50 ns tCLAX RC Low to Row Address Transition Min 50 ns tAVCH Column Address Valid to RC high Min 50 ns tCHAX RC High to Column Address Transition Min 50 ns tCHQV(1) RC High to Output Valid Max 150 ns tGLQV(1) Output Enable Low to Output Valid Max 50 ns tPHAV RP High to Row Address Valid Min 1 µs tGLQX Output Enable Low to Output Transition Min 0 ns tGHQZ Output Enable High to Output Hi-Z Max 50 ns tGHQX Output Hold from Output Enable High Min 0 ns Note: 1. G may be delayed up to tCHQV – t GLQV after the rising edge of RC without impact on t CHQV. Figure 12. Read AC Waveforms (A/A Mux Interface) tAVAV ROW ADDR VALID A0-A10 tAVCL NEXT ADDR VALID COLUMN ADDR VALID tAVCH tCLAX tCHAX RC tCHQV G tGLQV tGHQZ tGLQX tGHQX VALID DQ0-DQ7 W tPHAV RP AI03406 28/39 M50FW002 Table 25. Write AC Characteristics (A/A Mux Interface) Symbol Parameter Test Condition Value Unit tWLWH Write Enable Low to Write Enable High Min 100 ns tDVWH Data Valid to Write Enable High Min 50 ns tWHDX Write Enable High to Data Transition Min 5 ns tAVCL Row Address Valid to RC Low Min 50 ns tCLAX RC Low to Row Address Transition Min 50 ns tAVCH Column Address Valid to RC High Min 50 ns tCHAX RC High to Column Address Transition Min 50 ns tWHWL Write Enable High to Write Enable Low Min 100 ns tCHWH RC High to Write Enable High Min 50 ns tVPHWH(1) VPP High to Write Enable High Min 100 ns tWHGL Write Enable High to Output Enable Low Min 30 ns tWHRL Write Enable High to RB Low Min 0 ns Output Valid, RB High to VPP Low Min 0 ns tQVVPL(1,2) Note: 1. Sampled only, not 100% tested. 2. Applicable if VPP is seen as a logic input (V PP < 3.6V). Figure 13. Write AC Waveforms (A/A Mux Interface) Write erase or program setup A0-A10 Write erase confirm or valid address and data C1 R2 tCLAX tAVCH R1 tAVCL Automated erase or program delay Read Status Register Data Ready to write another command C2 tCHAX RC tWHWL tWLWH tCHWH W tVPHWH tWHGL G tWHRL RB tQVVPL VPP tDVWH DQ0-DQ7 DIN1 tWHDX DIN2 VALID SRD AI04194 29/39 M50FW002 Figure 14. Program Flowchart and Pseudo Code Start Program command: – write 40h or 10h – write Address & Data (memory enters read status state after the Program command) Write 40h or 10h Write Address & Data do: –read Status Register if Program/Erase Suspend command given execute suspend program loop NO Read Status Register Suspend b7 = 1 NO YES Suspend Loop while b7 = 1 YES b3 = 0 NO VPP Invalid Error (1, 2) If b3 = 1, VPP invalid error: – error handler NO Program Error (1, 2) If b4 = 1, Program error: – error handler NO Program to Protected Block Error (1, 2) YES b4 = 0 YES FWH Interface Only b1 = 0 If b1 = 1, Program to protected block error: – error handler YES End AI03407 Note: 1. A Status check of b1 (Protected Block), b3 (V PP invalid) and b4 (Program Error) can be made after each Program operation by following the correct command sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 30/39 M50FW002 Figure 15. Quadruple Byte Program Flowchart and Pseudo Code (A/A Mux Interface Only) Start Write 30h Write Address 1 & Data 1 (3) Quadruple Byte Program command: – write 30h – write Address 1 & Data 1 (3) – write Address 2 & Data 2 (3) – write Address 3 & Data 3 (3) – write Address 4 & Data 4 (3) Write Address 2 & Data 2 (3) (memory enters read status state after the Quadruple Byte Program command) Write Address 3 & Data 3 (3) Write Address 4 & Data 4 (3) do: – read Status Register if Program/Erase Suspend command given execute suspend program loop NO Read Status Register Suspend b7 = 1 NO YES Suspend Loop while b7 = 1 YES b3 = 0 NO VPP Invalid Error (1, 2) If b3 = 1, VPP invalid error: – error handler NO Program Error (1, 2) If b4 = 1, Program error: – error handler YES b4 = 0 YES End AI03982 Note: 1. A Status check of b3 (VPP invalid) and b4 (Program Error) can be made after each Program operation by following the correct command sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Address 1, Address 2, Address 3 and Address 4 must be consecutive addresses differing only for address bits A0 and A1. 31/39 M50FW002 Figure 16. Program Suspend and Resume Flowchart, and Pseudo Code Start Write B0h Program/Erase Suspend command: – write B0h – write 70h Write 70h do: – read Status Register Read Status Register b7 = 1 NO while b7 = 1 YES b2 = 1 NO Program Complete If b2 = 0 Program completed YES Write a read Command Read data from another address Write D0h Write FFh Program Continues Read Data Program/Erase Resume command: – write D0h to resume the program – if the Program operation completed then this is not necessary. The device returns to Read as normal (as if the Program/Erase suspend was not issued). AI03408 32/39 M50FW002 Figure 17. Chip Erase Flowchart and Pseudo Code (A/A Mux Interface Only) Start Chip Erase command: – write 80h – write 10h (memory enters read Status Register after the Chip Erase command) Write 80h Write 10h do: – read Status Register Read Status Register b7 = 1 NO while b7 = 1 YES b3 = 0 NO VPP Invalid Error (1) NO Command Sequence Error (1) If b3 = 1, VPP invalid error: – error handler YES b4, b5 = 0 If b4, b5 = 1, Command sequence error: – error handler YES b5 = 0 NO Erase Error (1) If b5 = 1, Erase error: – error handler YES End AI04195 Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 33/39 M50FW002 Figure 18. Block Erase Flowchart and Pseudo Code Start Erase command: – write 20h – write Block Address & D0h (memory enters read Status Register after the Erase command) Write 20h Write Block Address & D0h Suspend b7 = 1 do: – read Status Register – if Program/Erase Suspend command given execute suspend erase loop NO Read Status Register NO YES Suspend Loop while b7 = 1 YES b3 = 0 NO VPP Invalid Error (1) NO Command Sequence Error (1) If b3 = 1, VPP invalid error: – error handler YES b4, b5 = 0 If b4, b5 = 1, Command sequence error: – error handler YES b5 = 0 NO Erase Error (1) If b5 = 1, Erase error: – error handler YES FWH Interface Only b1 = 0 NO Erase to Protected Block Error (1) If b1 = 1, Erase to protected block error: – error handler YES End AI05433 Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 34/39 M50FW002 Figure 19. Erase Suspend and Resume Flowchart, and Pseudo Code Start Write B0h Program/Erase Suspend command: – write B0h – write 70h Write 70h do: – read Status Register Read Status Register b7 = 1 NO while b7 = 1 YES b6 = 1 NO Erase Complete If b6 = 0, Erase completed YES Read data from another block or Program Write D0h Write FFh Erase Continues Read Data Program/Erase Resume command: – write D0h to resume erase – if the Erase operation completed then this is not necessary. The device returns to Read as normal (as if the Program/Erase suspend was not issued). AI03410 35/39 M50FW002 PACKAGE MECHANICAL PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Outline D D1 A1 A2 1 N B1 E2 E3 e E1 E F B 0.51 (.020) E2 1.14 (.045) A D3 R D2 CP D2 PLCC-A Note: Drawing is not to scale. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data Symbol millimeters Typ Min Max Min Max A 3.18 3.56 0.125 0.140 A1 1.53 2.41 0.060 0.095 A2 0.38 – 0.015 – B 0.33 0.53 0.013 0.021 B1 0.66 0.81 0.026 0.032 CP Typ 0.10 0.004 D 12.32 12.57 D1 11.35 11.51 0.447 0.453 D2 4.78 5.66 0.188 0.223 – – – – E 14.86 15.11 0.585 0.595 E1 13.89 14.05 0.547 0.553 E2 6.05 6.93 0.238 0.273 D3 7.62 0.485 0.300 0.495 E3 10.16 – – 0.400 – – e 1.27 – – 0.050 – – F 0.00 0.13 0.000 0.005 N 32 R 36/39 inches 0.89 – 32 – 0.035 – – M50FW002 PART NUMBERING Table 26. Ordering Information Scheme Example: M50FW002 K 1 T Device Type M50 Architecture F = Firmware Hub Interface Operating Voltage W = 3.0 to 3.6V Device Function 002 = 2 Mbit (256Kb x8), Boot Block Package K = PLCC32 Temperature Range 1 = 0 to 70 °C 5 = –20 to 85°C Option T = Tape & Reel Packing Devices are shipped from the factory with the memory content bits erased to 1. For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact your nearest ST Sales Office. 37/39 M50FW002 REVISION HISTORY Table 27. Document Revision History Date Version 18-Dec-2001 -01 Document released 22-Jan-2002 -02 Details of Chip Erase command added 01-Mar-2002 -03 RFU pins must be left disconnected 12-Mar-2002 -04 Specification of PLCC32 package mechanical data revised 31-May-2002 -05 Document promoted from Product Preview to Preliminary Data 38/39 Revision Details M50FW002 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is registered trademark of STMicroelectronics All other names are the property of their respective owners © 2002 STMicroelectronics - All Rights Reserved STMicroelectronics group of companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. www.st.com 39/39